git.sur5r.net Git - u-boot/blob - arch/arm/dts/r8a7796.dtsi

   1 /*
   2  * Device Tree Source for the r8a7796 SoC
   3  *
   4  * Copyright (C) 2016 Renesas Electronics Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/power/r8a7796-sysc.h>
  14
  15 / {
  16         compatible = "renesas,r8a7796";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 i2c0 = &i2c0;
  22                 i2c1 = &i2c1;
  23                 i2c2 = &i2c2;
  24                 i2c3 = &i2c3;
  25                 i2c4 = &i2c4;
  26                 i2c5 = &i2c5;
  27                 i2c6 = &i2c6;
  28                 i2c7 = &i2c_dvfs;
  29         };
  30
  31         psci {
  32                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  33                 method = "smc";
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 a57_0: cpu@0 {
  41                         compatible = "arm,cortex-a57", "arm,armv8";
  42                         reg = <0x0>;
  43                         device_type = "cpu";
  44                         power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
  45                         next-level-cache = <&L2_CA57>;
  46                         enable-method = "psci";
  47                 };
  48
  49                 a57_1: cpu@1 {
  50                         compatible = "arm,cortex-a57","arm,armv8";
  51                         reg = <0x1>;
  52                         device_type = "cpu";
  53                         power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
  54                         next-level-cache = <&L2_CA57>;
  55                         enable-method = "psci";
  56                 };
  57
  58                 a53_0: cpu@100 {
  59                         compatible = "arm,cortex-a53", "arm,armv8";
  60                         reg = <0x100>;
  61                         device_type = "cpu";
  62                         power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
  63                         next-level-cache = <&L2_CA53>;
  64                         enable-method = "psci";
  65                 };
  66
  67                 a53_1: cpu@101 {
  68                         compatible = "arm,cortex-a53","arm,armv8";
  69                         reg = <0x101>;
  70                         device_type = "cpu";
  71                         power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
  72                         next-level-cache = <&L2_CA53>;
  73                         enable-method = "psci";
  74                 };
  75
  76                 a53_2: cpu@102 {
  77                         compatible = "arm,cortex-a53","arm,armv8";
  78                         reg = <0x102>;
  79                         device_type = "cpu";
  80                         power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
  81                         next-level-cache = <&L2_CA53>;
  82                         enable-method = "psci";
  83                 };
  84
  85                 a53_3: cpu@103 {
  86                         compatible = "arm,cortex-a53","arm,armv8";
  87                         reg = <0x103>;
  88                         device_type = "cpu";
  89                         power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
  90                         next-level-cache = <&L2_CA53>;
  91                         enable-method = "psci";
  92                 };
  93
  94                 L2_CA57: cache-controller-0 {
  95                         compatible = "cache";
  96                         power-domains = <&sysc R8A7796_PD_CA57_SCU>;
  97                         cache-unified;
  98                         cache-level = <2>;
  99                 };
 100
 101                 L2_CA53: cache-controller-1 {
 102                         compatible = "cache";
 103                         power-domains = <&sysc R8A7796_PD_CA53_SCU>;
 104                         cache-unified;
 105                         cache-level = <2>;
 106                 };
 107         };
 108
 109         extal_clk: extal {
 110                 compatible = "fixed-clock";
 111                 #clock-cells = <0>;
 112                 /* This value must be overridden by the board */
 113                 clock-frequency = <0>;
 114                 u-boot,dm-pre-reloc;
 115         };
 116
 117         extalr_clk: extalr {
 118                 compatible = "fixed-clock";
 119                 #clock-cells = <0>;
 120                 /* This value must be overridden by the board */
 121                 clock-frequency = <0>;
 122                 u-boot,dm-pre-reloc;
 123         };
 124
 125         /* External CAN clock - to be overridden by boards that provide it */
 126         can_clk: can {
 127                 compatible = "fixed-clock";
 128                 #clock-cells = <0>;
 129                 clock-frequency = <0>;
 130         };
 131
 132         /* External SCIF clock - to be overridden by boards that provide it */
 133         scif_clk: scif {
 134                 compatible = "fixed-clock";
 135                 #clock-cells = <0>;
 136                 clock-frequency = <0>;
 137         };
 138
 139         soc {
 140                 compatible = "simple-bus";
 141                 interrupt-parent = <&gic>;
 142                 #address-cells = <2>;
 143                 #size-cells = <2>;
 144                 ranges;
 145                 u-boot,dm-pre-reloc;
 146
 147                 gic: interrupt-controller@f1010000 {
 148                         compatible = "arm,gic-400";
 149                         #interrupt-cells = <3>;
 150                         #address-cells = <0>;
 151                         interrupt-controller;
 152                         reg = <0x0 0xf1010000 0 0x1000>,
 153                               <0x0 0xf1020000 0 0x20000>,
 154                               <0x0 0xf1040000 0 0x20000>,
 155                               <0x0 0xf1060000 0 0x20000>;
 156                         interrupts = <GIC_PPI 9
 157                                         (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
 158                         clocks = <&cpg CPG_MOD 408>;
 159                         clock-names = "clk";
 160                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 161                         resets = <&cpg 408>;
 162                 };
 163
 164                 timer {
 165                         compatible = "arm,armv8-timer";
 166                         interrupts = <GIC_PPI 13
 167                                         (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 168                                      <GIC_PPI 14
 169                                         (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 170                                      <GIC_PPI 11
 171                                         (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 172                                      <GIC_PPI 10
 173                                         (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
 174                 };
 175
 176                 wdt0: watchdog@e6020000 {
 177                         compatible = "renesas,r8a7796-wdt",
 178                                      "renesas,rcar-gen3-wdt";
 179                         reg = <0 0xe6020000 0 0x0c>;
 180                         clocks = <&cpg CPG_MOD 402>;
 181                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 182                         resets = <&cpg 402>;
 183                         status = "disabled";
 184                 };
 185
 186                 gpio0: gpio@e6050000 {
 187                         compatible = "renesas,gpio-r8a7796",
 188                                      "renesas,gpio-rcar";
 189                         reg = <0 0xe6050000 0 0x50>;
 190                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 191                         #gpio-cells = <2>;
 192                         gpio-controller;
 193                         gpio-ranges = <&pfc 0 0 16>;
 194                         #interrupt-cells = <2>;
 195                         interrupt-controller;
 196                         clocks = <&cpg CPG_MOD 912>;
 197                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 198                         resets = <&cpg 912>;
 199                 };
 200
 201                 gpio1: gpio@e6051000 {
 202                         compatible = "renesas,gpio-r8a7796",
 203                                      "renesas,gpio-rcar";
 204                         reg = <0 0xe6051000 0 0x50>;
 205                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 206                         #gpio-cells = <2>;
 207                         gpio-controller;
 208                         gpio-ranges = <&pfc 0 32 29>;
 209                         #interrupt-cells = <2>;
 210                         interrupt-controller;
 211                         clocks = <&cpg CPG_MOD 911>;
 212                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 213                         resets = <&cpg 911>;
 214                 };
 215
 216                 gpio2: gpio@e6052000 {
 217                         compatible = "renesas,gpio-r8a7796",
 218                                      "renesas,gpio-rcar";
 219                         reg = <0 0xe6052000 0 0x50>;
 220                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 221                         #gpio-cells = <2>;
 222                         gpio-controller;
 223                         gpio-ranges = <&pfc 0 64 15>;
 224                         #interrupt-cells = <2>;
 225                         interrupt-controller;
 226                         clocks = <&cpg CPG_MOD 910>;
 227                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 228                         resets = <&cpg 910>;
 229                 };
 230
 231                 gpio3: gpio@e6053000 {
 232                         compatible = "renesas,gpio-r8a7796",
 233                                      "renesas,gpio-rcar";
 234                         reg = <0 0xe6053000 0 0x50>;
 235                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 236                         #gpio-cells = <2>;
 237                         gpio-controller;
 238                         gpio-ranges = <&pfc 0 96 16>;
 239                         #interrupt-cells = <2>;
 240                         interrupt-controller;
 241                         clocks = <&cpg CPG_MOD 909>;
 242                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 243                         resets = <&cpg 909>;
 244                 };
 245
 246                 gpio4: gpio@e6054000 {
 247                         compatible = "renesas,gpio-r8a7796",
 248                                      "renesas,gpio-rcar";
 249                         reg = <0 0xe6054000 0 0x50>;
 250                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 251                         #gpio-cells = <2>;
 252                         gpio-controller;
 253                         gpio-ranges = <&pfc 0 128 18>;
 254                         #interrupt-cells = <2>;
 255                         interrupt-controller;
 256                         clocks = <&cpg CPG_MOD 908>;
 257                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 258                         resets = <&cpg 908>;
 259                 };
 260
 261                 gpio5: gpio@e6055000 {
 262                         compatible = "renesas,gpio-r8a7796",
 263                                      "renesas,gpio-rcar";
 264                         reg = <0 0xe6055000 0 0x50>;
 265                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 266                         #gpio-cells = <2>;
 267                         gpio-controller;
 268                         gpio-ranges = <&pfc 0 160 26>;
 269                         #interrupt-cells = <2>;
 270                         interrupt-controller;
 271                         clocks = <&cpg CPG_MOD 907>;
 272                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 273                         resets = <&cpg 907>;
 274                 };
 275
 276                 gpio6: gpio@e6055400 {
 277                         compatible = "renesas,gpio-r8a7796",
 278                                      "renesas,gpio-rcar";
 279                         reg = <0 0xe6055400 0 0x50>;
 280                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 281                         #gpio-cells = <2>;
 282                         gpio-controller;
 283                         gpio-ranges = <&pfc 0 192 32>;
 284                         #interrupt-cells = <2>;
 285                         interrupt-controller;
 286                         clocks = <&cpg CPG_MOD 906>;
 287                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 288                         resets = <&cpg 906>;
 289                 };
 290
 291                 gpio7: gpio@e6055800 {
 292                         compatible = "renesas,gpio-r8a7796",
 293                                      "renesas,gpio-rcar";
 294                         reg = <0 0xe6055800 0 0x50>;
 295                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 296                         #gpio-cells = <2>;
 297                         gpio-controller;
 298                         gpio-ranges = <&pfc 0 224 4>;
 299                         #interrupt-cells = <2>;
 300                         interrupt-controller;
 301                         clocks = <&cpg CPG_MOD 905>;
 302                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 303                         resets = <&cpg 905>;
 304                 };
 305
 306                 pfc: pin-controller@e6060000 {
 307                         compatible = "renesas,pfc-r8a7796";
 308                         reg = <0 0xe6060000 0 0x50c>;
 309                 };
 310
 311                 pmu_a57 {
 312                         compatible = "arm,cortex-a57-pmu";
 313                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 314                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 315                         interrupt-affinity = <&a57_0>,
 316                                              <&a57_1>;
 317                 };
 318
 319                 pmu_a53 {
 320                         compatible = "arm,cortex-a53-pmu";
 321                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 322                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 323                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
 324                                      <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 325                         interrupt-affinity = <&a53_0>,
 326                                              <&a53_1>,
 327                                              <&a53_2>,
 328                                              <&a53_3>;
 329                 };
 330
 331                 cpg: clock-controller@e6150000 {
 332                         compatible = "renesas,r8a7796-cpg-mssr";
 333                         reg = <0 0xe6150000 0 0x1000>;
 334                         clocks = <&extal_clk>, <&extalr_clk>;
 335                         clock-names = "extal", "extalr";
 336                         #clock-cells = <2>;
 337                         #power-domain-cells = <0>;
 338                         #reset-cells = <1>;
 339                         u-boot,dm-pre-reloc;
 340                 };
 341
 342                 rst: reset-controller@e6160000 {
 343                         compatible = "renesas,r8a7796-rst";
 344                         reg = <0 0xe6160000 0 0x0200>;
 345                 };
 346
 347                 prr: chipid@fff00044 {
 348                         compatible = "renesas,prr";
 349                         reg = <0 0xfff00044 0 4>;
 350                 };
 351
 352                 sysc: system-controller@e6180000 {
 353                         compatible = "renesas,r8a7796-sysc";
 354                         reg = <0 0xe6180000 0 0x0400>;
 355                         #power-domain-cells = <1>;
 356                 };
 357
 358                 i2c_dvfs: i2c@e60b0000 {
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         compatible = "renesas,iic-r8a7796",
 362                                      "renesas,rcar-gen3-iic",
 363                                      "renesas,rmobile-iic";
 364                         reg = <0 0xe60b0000 0 0x425>;
 365                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 366                         clocks = <&cpg CPG_MOD 926>;
 367                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 368                         resets = <&cpg 926>;
 369                         status = "disabled";
 370                 };
 371
 372                 i2c0: i2c@e6500000 {
 373                         #address-cells = <1>;
 374                         #size-cells = <0>;
 375                         compatible = "renesas,i2c-r8a7796",
 376                                      "renesas,rcar-gen3-i2c";
 377                         reg = <0 0xe6500000 0 0x40>;
 378                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 379                         clocks = <&cpg CPG_MOD 931>;
 380                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 381                         resets = <&cpg 931>;
 382                         dmas = <&dmac1 0x91>, <&dmac1 0x90>,
 383                                <&dmac2 0x91>, <&dmac2 0x90>;
 384                         dma-names = "tx", "rx", "tx", "rx";
 385                         i2c-scl-internal-delay-ns = <110>;
 386                         status = "disabled";
 387                 };
 388
 389                 i2c1: i2c@e6508000 {
 390                         #address-cells = <1>;
 391                         #size-cells = <0>;
 392                         compatible = "renesas,i2c-r8a7796",
 393                                      "renesas,rcar-gen3-i2c";
 394                         reg = <0 0xe6508000 0 0x40>;
 395                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 396                         clocks = <&cpg CPG_MOD 930>;
 397                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 398                         resets = <&cpg 930>;
 399                         dmas = <&dmac1 0x93>, <&dmac1 0x92>,
 400                                <&dmac2 0x93>, <&dmac2 0x92>;
 401                         dma-names = "tx", "rx", "tx", "rx";
 402                         i2c-scl-internal-delay-ns = <6>;
 403                         status = "disabled";
 404                 };
 405
 406                 i2c2: i2c@e6510000 {
 407                         #address-cells = <1>;
 408                         #size-cells = <0>;
 409                         compatible = "renesas,i2c-r8a7796",
 410                                      "renesas,rcar-gen3-i2c";
 411                         reg = <0 0xe6510000 0 0x40>;
 412                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 413                         clocks = <&cpg CPG_MOD 929>;
 414                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 415                         resets = <&cpg 929>;
 416                         dmas = <&dmac1 0x95>, <&dmac1 0x94>,
 417                                <&dmac2 0x95>, <&dmac2 0x94>;
 418                         dma-names = "tx", "rx", "tx", "rx";
 419                         i2c-scl-internal-delay-ns = <6>;
 420                         status = "disabled";
 421                 };
 422
 423                 i2c3: i2c@e66d0000 {
 424                         #address-cells = <1>;
 425                         #size-cells = <0>;
 426                         compatible = "renesas,i2c-r8a7796",
 427                                      "renesas,rcar-gen3-i2c";
 428                         reg = <0 0xe66d0000 0 0x40>;
 429                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 430                         clocks = <&cpg CPG_MOD 928>;
 431                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 432                         resets = <&cpg 928>;
 433                         dmas = <&dmac0 0x97>, <&dmac0 0x96>;
 434                         dma-names = "tx", "rx";
 435                         i2c-scl-internal-delay-ns = <110>;
 436                         status = "disabled";
 437                 };
 438
 439                 i2c4: i2c@e66d8000 {
 440                         #address-cells = <1>;
 441                         #size-cells = <0>;
 442                         compatible = "renesas,i2c-r8a7796",
 443                                      "renesas,rcar-gen3-i2c";
 444                         reg = <0 0xe66d8000 0 0x40>;
 445                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 446                         clocks = <&cpg CPG_MOD 927>;
 447                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 448                         resets = <&cpg 927>;
 449                         dmas = <&dmac0 0x99>, <&dmac0 0x98>;
 450                         dma-names = "tx", "rx";
 451                         i2c-scl-internal-delay-ns = <110>;
 452                         status = "disabled";
 453                 };
 454
 455                 i2c5: i2c@e66e0000 {
 456                         #address-cells = <1>;
 457                         #size-cells = <0>;
 458                         compatible = "renesas,i2c-r8a7796",
 459                                      "renesas,rcar-gen3-i2c";
 460                         reg = <0 0xe66e0000 0 0x40>;
 461                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 462                         clocks = <&cpg CPG_MOD 919>;
 463                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 464                         resets = <&cpg 919>;
 465                         dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
 466                         dma-names = "tx", "rx";
 467                         i2c-scl-internal-delay-ns = <110>;
 468                         status = "disabled";
 469                 };
 470
 471                 i2c6: i2c@e66e8000 {
 472                         #address-cells = <1>;
 473                         #size-cells = <0>;
 474                         compatible = "renesas,i2c-r8a7796",
 475                                      "renesas,rcar-gen3-i2c";
 476                         reg = <0 0xe66e8000 0 0x40>;
 477                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 478                         clocks = <&cpg CPG_MOD 918>;
 479                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 480                         resets = <&cpg 918>;
 481                         dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
 482                         dma-names = "tx", "rx";
 483                         i2c-scl-internal-delay-ns = <6>;
 484                         status = "disabled";
 485                 };
 486
 487                 can0: can@e6c30000 {
 488                         compatible = "renesas,can-r8a7796",
 489                                      "renesas,rcar-gen3-can";
 490                         reg = <0 0xe6c30000 0 0x1000>;
 491                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 492                         clocks = <&cpg CPG_MOD 916>,
 493                                <&cpg CPG_CORE R8A7796_CLK_CANFD>,
 494                                <&can_clk>;
 495                         clock-names = "clkp1", "clkp2", "can_clk";
 496                         assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
 497                         assigned-clock-rates = <40000000>;
 498                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 499                         resets = <&cpg 916>;
 500                         status = "disabled";
 501                 };
 502
 503                 can1: can@e6c38000 {
 504                         compatible = "renesas,can-r8a7796",
 505                                      "renesas,rcar-gen3-can";
 506                         reg = <0 0xe6c38000 0 0x1000>;
 507                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 508                         clocks = <&cpg CPG_MOD 915>,
 509                                <&cpg CPG_CORE R8A7796_CLK_CANFD>,
 510                                <&can_clk>;
 511                         clock-names = "clkp1", "clkp2", "can_clk";
 512                         assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
 513                         assigned-clock-rates = <40000000>;
 514                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 515                         resets = <&cpg 915>;
 516                         status = "disabled";
 517                 };
 518
 519                 canfd: can@e66c0000 {
 520                         compatible = "renesas,r8a7796-canfd",
 521                                      "renesas,rcar-gen3-canfd";
 522                         reg = <0 0xe66c0000 0 0x8000>;
 523                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
 524                                    <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 525                         clocks = <&cpg CPG_MOD 914>,
 526                                <&cpg CPG_CORE R8A7796_CLK_CANFD>,
 527                                <&can_clk>;
 528                         clock-names = "fck", "canfd", "can_clk";
 529                         assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
 530                         assigned-clock-rates = <40000000>;
 531                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 532                         resets = <&cpg 914>;
 533                         status = "disabled";
 534
 535                         channel0 {
 536                                 status = "disabled";
 537                         };
 538
 539                         channel1 {
 540                                 status = "disabled";
 541                         };
 542                 };
 543
 544                 avb: ethernet@e6800000 {
 545                         compatible = "renesas,etheravb-r8a7796",
 546                                      "renesas,etheravb-rcar-gen3";
 547                         reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
 548                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 549                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 550                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 551                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 552                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 553                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 554                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 555                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 556                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 557                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 558                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 559                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 560                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 561                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 562                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 563                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 564                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 565                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 566                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 567                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 568                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 569                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 570                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 571                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 572                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 573                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 574                                           "ch4", "ch5", "ch6", "ch7",
 575                                           "ch8", "ch9", "ch10", "ch11",
 576                                           "ch12", "ch13", "ch14", "ch15",
 577                                           "ch16", "ch17", "ch18", "ch19",
 578                                           "ch20", "ch21", "ch22", "ch23",
 579                                           "ch24";
 580                         clocks = <&cpg CPG_MOD 812>;
 581                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 582                         resets = <&cpg 812>;
 583                         phy-mode = "rgmii-txid";
 584                         #address-cells = <1>;
 585                         #size-cells = <0>;
 586                         status = "disabled";
 587                 };
 588
 589                 hscif0: serial@e6540000 {
 590                         compatible = "renesas,hscif-r8a7796",
 591                                      "renesas,rcar-gen3-hscif",
 592                                      "renesas,hscif";
 593                         reg = <0 0xe6540000 0 0x60>;
 594                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 595                         clocks = <&cpg CPG_MOD 520>,
 596                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 597                                  <&scif_clk>;
 598                         clock-names = "fck", "brg_int", "scif_clk";
 599                         dmas = <&dmac1 0x31>, <&dmac1 0x30>,
 600                                <&dmac2 0x31>, <&dmac2 0x30>;
 601                         dma-names = "tx", "rx", "tx", "rx";
 602                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 603                         resets = <&cpg 520>;
 604                         status = "disabled";
 605                 };
 606
 607                 hscif1: serial@e6550000 {
 608                         compatible = "renesas,hscif-r8a7796",
 609                                      "renesas,rcar-gen3-hscif",
 610                                      "renesas,hscif";
 611                         reg = <0 0xe6550000 0 0x60>;
 612                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 613                         clocks = <&cpg CPG_MOD 519>,
 614                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 615                                  <&scif_clk>;
 616                         clock-names = "fck", "brg_int", "scif_clk";
 617                         dmas = <&dmac1 0x33>, <&dmac1 0x32>,
 618                                <&dmac2 0x33>, <&dmac2 0x32>;
 619                         dma-names = "tx", "rx", "tx", "rx";
 620                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 621                         resets = <&cpg 519>;
 622                         status = "disabled";
 623                 };
 624
 625                 hscif2: serial@e6560000 {
 626                         compatible = "renesas,hscif-r8a7796",
 627                                      "renesas,rcar-gen3-hscif",
 628                                      "renesas,hscif";
 629                         reg = <0 0xe6560000 0 0x60>;
 630                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 631                         clocks = <&cpg CPG_MOD 518>,
 632                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 633                                  <&scif_clk>;
 634                         clock-names = "fck", "brg_int", "scif_clk";
 635                         dmas = <&dmac1 0x35>, <&dmac1 0x34>,
 636                                <&dmac2 0x35>, <&dmac2 0x34>;
 637                         dma-names = "tx", "rx", "tx", "rx";
 638                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 639                         resets = <&cpg 518>;
 640                         status = "disabled";
 641                 };
 642
 643                 hscif3: serial@e66a0000 {
 644                         compatible = "renesas,hscif-r8a7796",
 645                                      "renesas,rcar-gen3-hscif",
 646                                      "renesas,hscif";
 647                         reg = <0 0xe66a0000 0 0x60>;
 648                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 649                         clocks = <&cpg CPG_MOD 517>,
 650                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 651                                  <&scif_clk>;
 652                         clock-names = "fck", "brg_int", "scif_clk";
 653                         dmas = <&dmac0 0x37>, <&dmac0 0x36>;
 654                         dma-names = "tx", "rx";
 655                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 656                         resets = <&cpg 517>;
 657                         status = "disabled";
 658                 };
 659
 660                 hscif4: serial@e66b0000 {
 661                         compatible = "renesas,hscif-r8a7796",
 662                                      "renesas,rcar-gen3-hscif",
 663                                      "renesas,hscif";
 664                         reg = <0 0xe66b0000 0 0x60>;
 665                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 666                         clocks = <&cpg CPG_MOD 516>,
 667                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 668                                  <&scif_clk>;
 669                         clock-names = "fck", "brg_int", "scif_clk";
 670                         dmas = <&dmac0 0x39>, <&dmac0 0x38>;
 671                         dma-names = "tx", "rx";
 672                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 673                         resets = <&cpg 516>;
 674                         status = "disabled";
 675                 };
 676
 677                 scif0: serial@e6e60000 {
 678                         compatible = "renesas,scif-r8a7796",
 679                                      "renesas,rcar-gen3-scif", "renesas,scif";
 680                         reg = <0 0xe6e60000 0 64>;
 681                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 682                         clocks = <&cpg CPG_MOD 207>,
 683                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 684                                  <&scif_clk>;
 685                         clock-names = "fck", "brg_int", "scif_clk";
 686                         dmas = <&dmac1 0x51>, <&dmac1 0x50>,
 687                                <&dmac2 0x51>, <&dmac2 0x50>;
 688                         dma-names = "tx", "rx", "tx", "rx";
 689                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 690                         resets = <&cpg 207>;
 691                         status = "disabled";
 692                 };
 693
 694                 scif1: serial@e6e68000 {
 695                         compatible = "renesas,scif-r8a7796",
 696                                      "renesas,rcar-gen3-scif", "renesas,scif";
 697                         reg = <0 0xe6e68000 0 64>;
 698                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 699                         clocks = <&cpg CPG_MOD 206>,
 700                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 701                                  <&scif_clk>;
 702                         clock-names = "fck", "brg_int", "scif_clk";
 703                         dmas = <&dmac1 0x53>, <&dmac1 0x52>,
 704                                <&dmac2 0x53>, <&dmac2 0x52>;
 705                         dma-names = "tx", "rx", "tx", "rx";
 706                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 707                         resets = <&cpg 206>;
 708                         status = "disabled";
 709                 };
 710
 711                 scif2: serial@e6e88000 {
 712                         compatible = "renesas,scif-r8a7796",
 713                                      "renesas,rcar-gen3-scif", "renesas,scif";
 714                         reg = <0 0xe6e88000 0 64>;
 715                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 716                         clocks = <&cpg CPG_MOD 310>,
 717                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 718                                  <&scif_clk>;
 719                         clock-names = "fck", "brg_int", "scif_clk";
 720                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 721                         resets = <&cpg 310>;
 722                         status = "disabled";
 723                 };
 724
 725                 scif3: serial@e6c50000 {
 726                         compatible = "renesas,scif-r8a7796",
 727                                      "renesas,rcar-gen3-scif", "renesas,scif";
 728                         reg = <0 0xe6c50000 0 64>;
 729                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 730                         clocks = <&cpg CPG_MOD 204>,
 731                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 732                                  <&scif_clk>;
 733                         clock-names = "fck", "brg_int", "scif_clk";
 734                         dmas = <&dmac0 0x57>, <&dmac0 0x56>;
 735                         dma-names = "tx", "rx";
 736                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 737                         resets = <&cpg 204>;
 738                         status = "disabled";
 739                 };
 740
 741                 scif4: serial@e6c40000 {
 742                         compatible = "renesas,scif-r8a7796",
 743                                      "renesas,rcar-gen3-scif", "renesas,scif";
 744                         reg = <0 0xe6c40000 0 64>;
 745                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 746                         clocks = <&cpg CPG_MOD 203>,
 747                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 748                                  <&scif_clk>;
 749                         clock-names = "fck", "brg_int", "scif_clk";
 750                         dmas = <&dmac0 0x59>, <&dmac0 0x58>;
 751                         dma-names = "tx", "rx";
 752                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 753                         resets = <&cpg 203>;
 754                         status = "disabled";
 755                 };
 756
 757                 scif5: serial@e6f30000 {
 758                         compatible = "renesas,scif-r8a7796",
 759                                      "renesas,rcar-gen3-scif", "renesas,scif";
 760                         reg = <0 0xe6f30000 0 64>;
 761                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 762                         clocks = <&cpg CPG_MOD 202>,
 763                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 764                                  <&scif_clk>;
 765                         clock-names = "fck", "brg_int", "scif_clk";
 766                         dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
 767                                <&dmac2 0x5b>, <&dmac2 0x5a>;
 768                         dma-names = "tx", "rx", "tx", "rx";
 769                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 770                         resets = <&cpg 202>;
 771                         status = "disabled";
 772                 };
 773
 774                 msiof0: spi@e6e90000 {
 775                         compatible = "renesas,msiof-r8a7796",
 776                                      "renesas,rcar-gen3-msiof";
 777                         reg = <0 0xe6e90000 0 0x0064>;
 778                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 779                         clocks = <&cpg CPG_MOD 211>;
 780                         dmas = <&dmac1 0x41>, <&dmac1 0x40>,
 781                                <&dmac2 0x41>, <&dmac2 0x40>;
 782                         dma-names = "tx", "rx";
 783                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 784                         resets = <&cpg 211>;
 785                         #address-cells = <1>;
 786                         #size-cells = <0>;
 787                         status = "disabled";
 788                 };
 789
 790                 msiof1: spi@e6ea0000 {
 791                         compatible = "renesas,msiof-r8a7796",
 792                                      "renesas,rcar-gen3-msiof";
 793                         reg = <0 0xe6ea0000 0 0x0064>;
 794                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 795                         clocks = <&cpg CPG_MOD 210>;
 796                         dmas = <&dmac1 0x43>, <&dmac1 0x42>,
 797                                <&dmac2 0x43>, <&dmac2 0x42>;
 798                         dma-names = "tx", "rx";
 799                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 800                         resets = <&cpg 210>;
 801                         #address-cells = <1>;
 802                         #size-cells = <0>;
 803                         status = "disabled";
 804                 };
 805
 806                 msiof2: spi@e6c00000 {
 807                         compatible = "renesas,msiof-r8a7796",
 808                                      "renesas,rcar-gen3-msiof";
 809                         reg = <0 0xe6c00000 0 0x0064>;
 810                         interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 811                         clocks = <&cpg CPG_MOD 209>;
 812                         dmas = <&dmac0 0x45>, <&dmac0 0x44>;
 813                         dma-names = "tx", "rx";
 814                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 815                         resets = <&cpg 209>;
 816                         #address-cells = <1>;
 817                         #size-cells = <0>;
 818                         status = "disabled";
 819                 };
 820
 821                 msiof3: spi@e6c10000 {
 822                         compatible = "renesas,msiof-r8a7796",
 823                                      "renesas,rcar-gen3-msiof";
 824                         reg = <0 0xe6c10000 0 0x0064>;
 825                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 826                         clocks = <&cpg CPG_MOD 208>;
 827                         dmas = <&dmac0 0x47>, <&dmac0 0x46>;
 828                         dma-names = "tx", "rx";
 829                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 830                         resets = <&cpg 208>;
 831                         #address-cells = <1>;
 832                         #size-cells = <0>;
 833                         status = "disabled";
 834                 };
 835
 836                 dmac0: dma-controller@e6700000 {
 837                         compatible = "renesas,dmac-r8a7796",
 838                                      "renesas,rcar-dmac";
 839                         reg = <0 0xe6700000 0 0x10000>;
 840                         interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
 841                                       GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 842                                       GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 843                                       GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 844                                       GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 845                                       GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 846                                       GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 847                                       GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 848                                       GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 849                                       GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 850                                       GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 851                                       GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 852                                       GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 853                                       GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 854                                       GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 855                                       GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
 856                                       GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
 857                         interrupt-names = "error",
 858                                         "ch0", "ch1", "ch2", "ch3",
 859                                         "ch4", "ch5", "ch6", "ch7",
 860                                         "ch8", "ch9", "ch10", "ch11",
 861                                         "ch12", "ch13", "ch14", "ch15";
 862                         clocks = <&cpg CPG_MOD 219>;
 863                         clock-names = "fck";
 864                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 865                         resets = <&cpg 219>;
 866                         #dma-cells = <1>;
 867                         dma-channels = <16>;
 868                 };
 869
 870                 dmac1: dma-controller@e7300000 {
 871                         compatible = "renesas,dmac-r8a7796",
 872                                      "renesas,rcar-dmac";
 873                         reg = <0 0xe7300000 0 0x10000>;
 874                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 875                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 876                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 877                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 878                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 879                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 880                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 881                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 882                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 883                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 884                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 885                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 886                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 887                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 888                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 889                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
 890                                       GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
 891                         interrupt-names = "error",
 892                                         "ch0", "ch1", "ch2", "ch3",
 893                                         "ch4", "ch5", "ch6", "ch7",
 894                                         "ch8", "ch9", "ch10", "ch11",
 895                                         "ch12", "ch13", "ch14", "ch15";
 896                         clocks = <&cpg CPG_MOD 218>;
 897                         clock-names = "fck";
 898                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 899                         resets = <&cpg 218>;
 900                         #dma-cells = <1>;
 901                         dma-channels = <16>;
 902                 };
 903
 904                 dmac2: dma-controller@e7310000 {
 905                         compatible = "renesas,dmac-r8a7796",
 906                                      "renesas,rcar-dmac";
 907                         reg = <0 0xe7310000 0 0x10000>;
 908                         interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
 909                                       GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
 910                                       GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
 911                                       GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
 912                                       GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
 913                                       GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
 914                                       GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
 915                                       GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
 916                                       GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
 917                                       GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
 918                                       GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
 919                                       GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
 920                                       GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
 921                                       GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
 922                                       GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
 923                                       GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
 924                                       GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
 925                         interrupt-names = "error",
 926                                         "ch0", "ch1", "ch2", "ch3",
 927                                         "ch4", "ch5", "ch6", "ch7",
 928                                         "ch8", "ch9", "ch10", "ch11",
 929                                         "ch12", "ch13", "ch14", "ch15";
 930                         clocks = <&cpg CPG_MOD 217>;
 931                         clock-names = "fck";
 932                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 933                         resets = <&cpg 217>;
 934                         #dma-cells = <1>;
 935                         dma-channels = <16>;
 936                 };
 937
 938                 sdhi0: sd@ee100000 {
 939                         compatible = "renesas,sdhi-r8a7796";
 940                         reg = <0 0xee100000 0 0x2000>;
 941                         interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 942                         clocks = <&cpg CPG_MOD 314>;
 943                         max-frequency = <200000000>;
 944                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 945                         resets = <&cpg 314>;
 946                         status = "disabled";
 947                 };
 948
 949                 sdhi1: sd@ee120000 {
 950                         compatible = "renesas,sdhi-r8a7796";
 951                         reg = <0 0xee120000 0 0x2000>;
 952                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 953                         clocks = <&cpg CPG_MOD 313>;
 954                         max-frequency = <200000000>;
 955                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 956                         resets = <&cpg 313>;
 957                         status = "disabled";
 958                 };
 959
 960                 sdhi2: sd@ee140000 {
 961                         compatible = "renesas,sdhi-r8a7796";
 962                         reg = <0 0xee140000 0 0x2000>;
 963                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 964                         clocks = <&cpg CPG_MOD 312>;
 965                         max-frequency = <200000000>;
 966                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 967                         resets = <&cpg 312>;
 968                         status = "disabled";
 969                 };
 970
 971                 sdhi3: sd@ee160000 {
 972                         compatible = "renesas,sdhi-r8a7796";
 973                         reg = <0 0xee160000 0 0x2000>;
 974                         interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 975                         clocks = <&cpg CPG_MOD 311>;
 976                         max-frequency = <200000000>;
 977                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 978                         resets = <&cpg 311>;
 979                         status = "disabled";
 980                 };
 981
 982                 tsc: thermal@e6198000 {
 983                         compatible = "renesas,r8a7796-thermal";
 984                         reg = <0 0xe6198000 0 0x68>,
 985                               <0 0xe61a0000 0 0x5c>,
 986                               <0 0xe61a8000 0 0x5c>;
 987                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 988                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 989                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 990                         clocks = <&cpg CPG_MOD 522>;
 991                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 992                         resets = <&cpg 522>;
 993                         #thermal-sensor-cells = <1>;
 994                         status = "okay";
 995                 };
 996
 997                 thermal-zones {
 998                         sensor_thermal1: sensor-thermal1 {
 999                                 polling-delay-passive = <250>;
1000                                 polling-delay = <1000>;
1001                                 thermal-sensors = <&tsc 0>;
1002
1003                                 trips {
1004                                         sensor1_crit: sensor1-crit {
1005                                                 temperature = <120000>;
1006                                                 hysteresis = <2000>;
1007                                                 type = "critical";
1008                                         };
1009                                 };
1010                         };
1011
1012                         sensor_thermal2: sensor-thermal2 {
1013                                 polling-delay-passive = <250>;
1014                                 polling-delay = <1000>;
1015                                 thermal-sensors = <&tsc 1>;
1016
1017                                 trips {
1018                                         sensor2_crit: sensor2-crit {
1019                                                 temperature = <120000>;
1020                                                 hysteresis = <2000>;
1021                                                 type = "critical";
1022                                         };
1023                                 };
1024                         };
1025
1026                         sensor_thermal3: sensor-thermal3 {
1027                                 polling-delay-passive = <250>;
1028                                 polling-delay = <1000>;
1029                                 thermal-sensors = <&tsc 2>;
1030
1031                                 trips {
1032                                         sensor3_crit: sensor3-crit {
1033                                                 temperature = <120000>;
1034                                                 hysteresis = <2000>;
1035                                                 type = "critical";
1036                                         };
1037                                 };
1038                         };
1039                 };
1040         };
1041 };