git.sur5r.net Git - u-boot/blob - arch/arm/dts/r8a7796.dtsi

   1 /*
   2  * Device Tree Source for the r8a7796 SoC
   3  *
   4  * Copyright (C) 2016 Renesas Electronics Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/power/r8a7796-sysc.h>
  14
  15 / {
  16         compatible = "renesas,r8a7796";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 i2c0 = &i2c0;
  22                 i2c1 = &i2c1;
  23                 i2c2 = &i2c2;
  24                 i2c3 = &i2c3;
  25                 i2c4 = &i2c4;
  26                 i2c5 = &i2c5;
  27                 i2c6 = &i2c6;
  28                 i2c7 = &i2c_dvfs;
  29         };
  30
  31         psci {
  32                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  33                 method = "smc";
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 a57_0: cpu@0 {
  41                         compatible = "arm,cortex-a57", "arm,armv8";
  42                         reg = <0x0>;
  43                         device_type = "cpu";
  44                         power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
  45                         next-level-cache = <&L2_CA57>;
  46                         enable-method = "psci";
  47                 };
  48
  49                 a57_1: cpu@1 {
  50                         compatible = "arm,cortex-a57","arm,armv8";
  51                         reg = <0x1>;
  52                         device_type = "cpu";
  53                         power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
  54                         next-level-cache = <&L2_CA57>;
  55                         enable-method = "psci";
  56                 };
  57
  58                 a53_0: cpu@100 {
  59                         compatible = "arm,cortex-a53", "arm,armv8";
  60                         reg = <0x100>;
  61                         device_type = "cpu";
  62                         power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
  63                         next-level-cache = <&L2_CA53>;
  64                         enable-method = "psci";
  65                 };
  66
  67                 a53_1: cpu@101 {
  68                         compatible = "arm,cortex-a53","arm,armv8";
  69                         reg = <0x101>;
  70                         device_type = "cpu";
  71                         power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
  72                         next-level-cache = <&L2_CA53>;
  73                         enable-method = "psci";
  74                 };
  75
  76                 a53_2: cpu@102 {
  77                         compatible = "arm,cortex-a53","arm,armv8";
  78                         reg = <0x102>;
  79                         device_type = "cpu";
  80                         power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
  81                         next-level-cache = <&L2_CA53>;
  82                         enable-method = "psci";
  83                 };
  84
  85                 a53_3: cpu@103 {
  86                         compatible = "arm,cortex-a53","arm,armv8";
  87                         reg = <0x103>;
  88                         device_type = "cpu";
  89                         power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
  90                         next-level-cache = <&L2_CA53>;
  91                         enable-method = "psci";
  92                 };
  93
  94                 L2_CA57: cache-controller-0 {
  95                         compatible = "cache";
  96                         power-domains = <&sysc R8A7796_PD_CA57_SCU>;
  97                         cache-unified;
  98                         cache-level = <2>;
  99                 };
 100
 101                 L2_CA53: cache-controller-1 {
 102                         compatible = "cache";
 103                         power-domains = <&sysc R8A7796_PD_CA53_SCU>;
 104                         cache-unified;
 105                         cache-level = <2>;
 106                 };
 107         };
 108
 109         extal_clk: extal {
 110                 compatible = "fixed-clock";
 111                 #clock-cells = <0>;
 112                 /* This value must be overridden by the board */
 113                 clock-frequency = <0>;
 114         };
 115
 116         extalr_clk: extalr {
 117                 compatible = "fixed-clock";
 118                 #clock-cells = <0>;
 119                 /* This value must be overridden by the board */
 120                 clock-frequency = <0>;
 121         };
 122
 123         /* External CAN clock - to be overridden by boards that provide it */
 124         can_clk: can {
 125                 compatible = "fixed-clock";
 126                 #clock-cells = <0>;
 127                 clock-frequency = <0>;
 128         };
 129
 130         /* External SCIF clock - to be overridden by boards that provide it */
 131         scif_clk: scif {
 132                 compatible = "fixed-clock";
 133                 #clock-cells = <0>;
 134                 clock-frequency = <0>;
 135         };
 136
 137         soc {
 138                 compatible = "simple-bus";
 139                 interrupt-parent = <&gic>;
 140                 #address-cells = <2>;
 141                 #size-cells = <2>;
 142                 ranges;
 143
 144                 gic: interrupt-controller@f1010000 {
 145                         compatible = "arm,gic-400";
 146                         #interrupt-cells = <3>;
 147                         #address-cells = <0>;
 148                         interrupt-controller;
 149                         reg = <0x0 0xf1010000 0 0x1000>,
 150                               <0x0 0xf1020000 0 0x20000>,
 151                               <0x0 0xf1040000 0 0x20000>,
 152                               <0x0 0xf1060000 0 0x20000>;
 153                         interrupts = <GIC_PPI 9
 154                                         (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
 155                         clocks = <&cpg CPG_MOD 408>;
 156                         clock-names = "clk";
 157                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 158                         resets = <&cpg 408>;
 159                 };
 160
 161                 timer {
 162                         compatible = "arm,armv8-timer";
 163                         interrupts = <GIC_PPI 13
 164                                         (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 165                                      <GIC_PPI 14
 166                                         (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 167                                      <GIC_PPI 11
 168                                         (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 169                                      <GIC_PPI 10
 170                                         (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
 171                 };
 172
 173                 wdt0: watchdog@e6020000 {
 174                         compatible = "renesas,r8a7796-wdt",
 175                                      "renesas,rcar-gen3-wdt";
 176                         reg = <0 0xe6020000 0 0x0c>;
 177                         clocks = <&cpg CPG_MOD 402>;
 178                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 179                         resets = <&cpg 402>;
 180                         status = "disabled";
 181                 };
 182
 183                 gpio0: gpio@e6050000 {
 184                         compatible = "renesas,gpio-r8a7796",
 185                                      "renesas,gpio-rcar";
 186                         reg = <0 0xe6050000 0 0x50>;
 187                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 188                         #gpio-cells = <2>;
 189                         gpio-controller;
 190                         gpio-ranges = <&pfc 0 0 16>;
 191                         #interrupt-cells = <2>;
 192                         interrupt-controller;
 193                         clocks = <&cpg CPG_MOD 912>;
 194                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 195                         resets = <&cpg 912>;
 196                 };
 197
 198                 gpio1: gpio@e6051000 {
 199                         compatible = "renesas,gpio-r8a7796",
 200                                      "renesas,gpio-rcar";
 201                         reg = <0 0xe6051000 0 0x50>;
 202                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 203                         #gpio-cells = <2>;
 204                         gpio-controller;
 205                         gpio-ranges = <&pfc 0 32 29>;
 206                         #interrupt-cells = <2>;
 207                         interrupt-controller;
 208                         clocks = <&cpg CPG_MOD 911>;
 209                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 210                         resets = <&cpg 911>;
 211                 };
 212
 213                 gpio2: gpio@e6052000 {
 214                         compatible = "renesas,gpio-r8a7796",
 215                                      "renesas,gpio-rcar";
 216                         reg = <0 0xe6052000 0 0x50>;
 217                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 218                         #gpio-cells = <2>;
 219                         gpio-controller;
 220                         gpio-ranges = <&pfc 0 64 15>;
 221                         #interrupt-cells = <2>;
 222                         interrupt-controller;
 223                         clocks = <&cpg CPG_MOD 910>;
 224                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 225                         resets = <&cpg 910>;
 226                 };
 227
 228                 gpio3: gpio@e6053000 {
 229                         compatible = "renesas,gpio-r8a7796",
 230                                      "renesas,gpio-rcar";
 231                         reg = <0 0xe6053000 0 0x50>;
 232                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 233                         #gpio-cells = <2>;
 234                         gpio-controller;
 235                         gpio-ranges = <&pfc 0 96 16>;
 236                         #interrupt-cells = <2>;
 237                         interrupt-controller;
 238                         clocks = <&cpg CPG_MOD 909>;
 239                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 240                         resets = <&cpg 909>;
 241                 };
 242
 243                 gpio4: gpio@e6054000 {
 244                         compatible = "renesas,gpio-r8a7796",
 245                                      "renesas,gpio-rcar";
 246                         reg = <0 0xe6054000 0 0x50>;
 247                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 248                         #gpio-cells = <2>;
 249                         gpio-controller;
 250                         gpio-ranges = <&pfc 0 128 18>;
 251                         #interrupt-cells = <2>;
 252                         interrupt-controller;
 253                         clocks = <&cpg CPG_MOD 908>;
 254                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 255                         resets = <&cpg 908>;
 256                 };
 257
 258                 gpio5: gpio@e6055000 {
 259                         compatible = "renesas,gpio-r8a7796",
 260                                      "renesas,gpio-rcar";
 261                         reg = <0 0xe6055000 0 0x50>;
 262                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 263                         #gpio-cells = <2>;
 264                         gpio-controller;
 265                         gpio-ranges = <&pfc 0 160 26>;
 266                         #interrupt-cells = <2>;
 267                         interrupt-controller;
 268                         clocks = <&cpg CPG_MOD 907>;
 269                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 270                         resets = <&cpg 907>;
 271                 };
 272
 273                 gpio6: gpio@e6055400 {
 274                         compatible = "renesas,gpio-r8a7796",
 275                                      "renesas,gpio-rcar";
 276                         reg = <0 0xe6055400 0 0x50>;
 277                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 278                         #gpio-cells = <2>;
 279                         gpio-controller;
 280                         gpio-ranges = <&pfc 0 192 32>;
 281                         #interrupt-cells = <2>;
 282                         interrupt-controller;
 283                         clocks = <&cpg CPG_MOD 906>;
 284                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 285                         resets = <&cpg 906>;
 286                 };
 287
 288                 gpio7: gpio@e6055800 {
 289                         compatible = "renesas,gpio-r8a7796",
 290                                      "renesas,gpio-rcar";
 291                         reg = <0 0xe6055800 0 0x50>;
 292                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 293                         #gpio-cells = <2>;
 294                         gpio-controller;
 295                         gpio-ranges = <&pfc 0 224 4>;
 296                         #interrupt-cells = <2>;
 297                         interrupt-controller;
 298                         clocks = <&cpg CPG_MOD 905>;
 299                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 300                         resets = <&cpg 905>;
 301                 };
 302
 303                 pfc: pin-controller@e6060000 {
 304                         compatible = "renesas,pfc-r8a7796";
 305                         reg = <0 0xe6060000 0 0x50c>;
 306                 };
 307
 308                 pmu_a57 {
 309                         compatible = "arm,cortex-a57-pmu";
 310                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 311                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 312                         interrupt-affinity = <&a57_0>,
 313                                              <&a57_1>;
 314                 };
 315
 316                 pmu_a53 {
 317                         compatible = "arm,cortex-a53-pmu";
 318                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 319                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 320                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
 321                                      <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 322                         interrupt-affinity = <&a53_0>,
 323                                              <&a53_1>,
 324                                              <&a53_2>,
 325                                              <&a53_3>;
 326                 };
 327
 328                 cpg: clock-controller@e6150000 {
 329                         compatible = "renesas,r8a7796-cpg-mssr";
 330                         reg = <0 0xe6150000 0 0x1000>;
 331                         clocks = <&extal_clk>, <&extalr_clk>;
 332                         clock-names = "extal", "extalr";
 333                         #clock-cells = <2>;
 334                         #power-domain-cells = <0>;
 335                         #reset-cells = <1>;
 336                 };
 337
 338                 rst: reset-controller@e6160000 {
 339                         compatible = "renesas,r8a7796-rst";
 340                         reg = <0 0xe6160000 0 0x0200>;
 341                 };
 342
 343                 prr: chipid@fff00044 {
 344                         compatible = "renesas,prr";
 345                         reg = <0 0xfff00044 0 4>;
 346                 };
 347
 348                 sysc: system-controller@e6180000 {
 349                         compatible = "renesas,r8a7796-sysc";
 350                         reg = <0 0xe6180000 0 0x0400>;
 351                         #power-domain-cells = <1>;
 352                 };
 353
 354                 i2c_dvfs: i2c@e60b0000 {
 355                         #address-cells = <1>;
 356                         #size-cells = <0>;
 357                         compatible = "renesas,iic-r8a7796",
 358                                      "renesas,rcar-gen3-iic",
 359                                      "renesas,rmobile-iic";
 360                         reg = <0 0xe60b0000 0 0x425>;
 361                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 362                         clocks = <&cpg CPG_MOD 926>;
 363                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 364                         resets = <&cpg 926>;
 365                         status = "disabled";
 366                 };
 367
 368                 i2c0: i2c@e6500000 {
 369                         #address-cells = <1>;
 370                         #size-cells = <0>;
 371                         compatible = "renesas,i2c-r8a7796",
 372                                      "renesas,rcar-gen3-i2c";
 373                         reg = <0 0xe6500000 0 0x40>;
 374                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 375                         clocks = <&cpg CPG_MOD 931>;
 376                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 377                         resets = <&cpg 931>;
 378                         dmas = <&dmac1 0x91>, <&dmac1 0x90>,
 379                                <&dmac2 0x91>, <&dmac2 0x90>;
 380                         dma-names = "tx", "rx", "tx", "rx";
 381                         i2c-scl-internal-delay-ns = <110>;
 382                         status = "disabled";
 383                 };
 384
 385                 i2c1: i2c@e6508000 {
 386                         #address-cells = <1>;
 387                         #size-cells = <0>;
 388                         compatible = "renesas,i2c-r8a7796",
 389                                      "renesas,rcar-gen3-i2c";
 390                         reg = <0 0xe6508000 0 0x40>;
 391                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 392                         clocks = <&cpg CPG_MOD 930>;
 393                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 394                         resets = <&cpg 930>;
 395                         dmas = <&dmac1 0x93>, <&dmac1 0x92>,
 396                                <&dmac2 0x93>, <&dmac2 0x92>;
 397                         dma-names = "tx", "rx", "tx", "rx";
 398                         i2c-scl-internal-delay-ns = <6>;
 399                         status = "disabled";
 400                 };
 401
 402                 i2c2: i2c@e6510000 {
 403                         #address-cells = <1>;
 404                         #size-cells = <0>;
 405                         compatible = "renesas,i2c-r8a7796",
 406                                      "renesas,rcar-gen3-i2c";
 407                         reg = <0 0xe6510000 0 0x40>;
 408                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 409                         clocks = <&cpg CPG_MOD 929>;
 410                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 411                         resets = <&cpg 929>;
 412                         dmas = <&dmac1 0x95>, <&dmac1 0x94>,
 413                                <&dmac2 0x95>, <&dmac2 0x94>;
 414                         dma-names = "tx", "rx", "tx", "rx";
 415                         i2c-scl-internal-delay-ns = <6>;
 416                         status = "disabled";
 417                 };
 418
 419                 i2c3: i2c@e66d0000 {
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422                         compatible = "renesas,i2c-r8a7796",
 423                                      "renesas,rcar-gen3-i2c";
 424                         reg = <0 0xe66d0000 0 0x40>;
 425                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 426                         clocks = <&cpg CPG_MOD 928>;
 427                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 428                         resets = <&cpg 928>;
 429                         dmas = <&dmac0 0x97>, <&dmac0 0x96>;
 430                         dma-names = "tx", "rx";
 431                         i2c-scl-internal-delay-ns = <110>;
 432                         status = "disabled";
 433                 };
 434
 435                 i2c4: i2c@e66d8000 {
 436                         #address-cells = <1>;
 437                         #size-cells = <0>;
 438                         compatible = "renesas,i2c-r8a7796",
 439                                      "renesas,rcar-gen3-i2c";
 440                         reg = <0 0xe66d8000 0 0x40>;
 441                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 442                         clocks = <&cpg CPG_MOD 927>;
 443                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 444                         resets = <&cpg 927>;
 445                         dmas = <&dmac0 0x99>, <&dmac0 0x98>;
 446                         dma-names = "tx", "rx";
 447                         i2c-scl-internal-delay-ns = <110>;
 448                         status = "disabled";
 449                 };
 450
 451                 i2c5: i2c@e66e0000 {
 452                         #address-cells = <1>;
 453                         #size-cells = <0>;
 454                         compatible = "renesas,i2c-r8a7796",
 455                                      "renesas,rcar-gen3-i2c";
 456                         reg = <0 0xe66e0000 0 0x40>;
 457                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 458                         clocks = <&cpg CPG_MOD 919>;
 459                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 460                         resets = <&cpg 919>;
 461                         dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
 462                         dma-names = "tx", "rx";
 463                         i2c-scl-internal-delay-ns = <110>;
 464                         status = "disabled";
 465                 };
 466
 467                 i2c6: i2c@e66e8000 {
 468                         #address-cells = <1>;
 469                         #size-cells = <0>;
 470                         compatible = "renesas,i2c-r8a7796",
 471                                      "renesas,rcar-gen3-i2c";
 472                         reg = <0 0xe66e8000 0 0x40>;
 473                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 474                         clocks = <&cpg CPG_MOD 918>;
 475                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 476                         resets = <&cpg 918>;
 477                         dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
 478                         dma-names = "tx", "rx";
 479                         i2c-scl-internal-delay-ns = <6>;
 480                         status = "disabled";
 481                 };
 482
 483                 can0: can@e6c30000 {
 484                         compatible = "renesas,can-r8a7796",
 485                                      "renesas,rcar-gen3-can";
 486                         reg = <0 0xe6c30000 0 0x1000>;
 487                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 488                         clocks = <&cpg CPG_MOD 916>,
 489                                <&cpg CPG_CORE R8A7796_CLK_CANFD>,
 490                                <&can_clk>;
 491                         clock-names = "clkp1", "clkp2", "can_clk";
 492                         assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
 493                         assigned-clock-rates = <40000000>;
 494                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 495                         resets = <&cpg 916>;
 496                         status = "disabled";
 497                 };
 498
 499                 can1: can@e6c38000 {
 500                         compatible = "renesas,can-r8a7796",
 501                                      "renesas,rcar-gen3-can";
 502                         reg = <0 0xe6c38000 0 0x1000>;
 503                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 504                         clocks = <&cpg CPG_MOD 915>,
 505                                <&cpg CPG_CORE R8A7796_CLK_CANFD>,
 506                                <&can_clk>;
 507                         clock-names = "clkp1", "clkp2", "can_clk";
 508                         assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
 509                         assigned-clock-rates = <40000000>;
 510                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 511                         resets = <&cpg 915>;
 512                         status = "disabled";
 513                 };
 514
 515                 canfd: can@e66c0000 {
 516                         compatible = "renesas,r8a7796-canfd",
 517                                      "renesas,rcar-gen3-canfd";
 518                         reg = <0 0xe66c0000 0 0x8000>;
 519                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
 520                                    <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 521                         clocks = <&cpg CPG_MOD 914>,
 522                                <&cpg CPG_CORE R8A7796_CLK_CANFD>,
 523                                <&can_clk>;
 524                         clock-names = "fck", "canfd", "can_clk";
 525                         assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
 526                         assigned-clock-rates = <40000000>;
 527                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 528                         resets = <&cpg 914>;
 529                         status = "disabled";
 530
 531                         channel0 {
 532                                 status = "disabled";
 533                         };
 534
 535                         channel1 {
 536                                 status = "disabled";
 537                         };
 538                 };
 539
 540                 avb: ethernet@e6800000 {
 541                         compatible = "renesas,etheravb-r8a7796",
 542                                      "renesas,etheravb-rcar-gen3";
 543                         reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
 544                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 545                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 546                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 547                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 548                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 549                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 550                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 551                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 552                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 553                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 554                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 555                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 556                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 557                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 558                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 559                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 560                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 561                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 562                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 563                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 564                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 565                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 566                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 567                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 568                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 569                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 570                                           "ch4", "ch5", "ch6", "ch7",
 571                                           "ch8", "ch9", "ch10", "ch11",
 572                                           "ch12", "ch13", "ch14", "ch15",
 573                                           "ch16", "ch17", "ch18", "ch19",
 574                                           "ch20", "ch21", "ch22", "ch23",
 575                                           "ch24";
 576                         clocks = <&cpg CPG_MOD 812>;
 577                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 578                         resets = <&cpg 812>;
 579                         phy-mode = "rgmii-txid";
 580                         #address-cells = <1>;
 581                         #size-cells = <0>;
 582                         status = "disabled";
 583                 };
 584
 585                 hscif0: serial@e6540000 {
 586                         compatible = "renesas,hscif-r8a7796",
 587                                      "renesas,rcar-gen3-hscif",
 588                                      "renesas,hscif";
 589                         reg = <0 0xe6540000 0 0x60>;
 590                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 591                         clocks = <&cpg CPG_MOD 520>,
 592                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 593                                  <&scif_clk>;
 594                         clock-names = "fck", "brg_int", "scif_clk";
 595                         dmas = <&dmac1 0x31>, <&dmac1 0x30>,
 596                                <&dmac2 0x31>, <&dmac2 0x30>;
 597                         dma-names = "tx", "rx", "tx", "rx";
 598                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 599                         resets = <&cpg 520>;
 600                         status = "disabled";
 601                 };
 602
 603                 hscif1: serial@e6550000 {
 604                         compatible = "renesas,hscif-r8a7796",
 605                                      "renesas,rcar-gen3-hscif",
 606                                      "renesas,hscif";
 607                         reg = <0 0xe6550000 0 0x60>;
 608                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 609                         clocks = <&cpg CPG_MOD 519>,
 610                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 611                                  <&scif_clk>;
 612                         clock-names = "fck", "brg_int", "scif_clk";
 613                         dmas = <&dmac1 0x33>, <&dmac1 0x32>,
 614                                <&dmac2 0x33>, <&dmac2 0x32>;
 615                         dma-names = "tx", "rx", "tx", "rx";
 616                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 617                         resets = <&cpg 519>;
 618                         status = "disabled";
 619                 };
 620
 621                 hscif2: serial@e6560000 {
 622                         compatible = "renesas,hscif-r8a7796",
 623                                      "renesas,rcar-gen3-hscif",
 624                                      "renesas,hscif";
 625                         reg = <0 0xe6560000 0 0x60>;
 626                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 627                         clocks = <&cpg CPG_MOD 518>,
 628                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 629                                  <&scif_clk>;
 630                         clock-names = "fck", "brg_int", "scif_clk";
 631                         dmas = <&dmac1 0x35>, <&dmac1 0x34>,
 632                                <&dmac2 0x35>, <&dmac2 0x34>;
 633                         dma-names = "tx", "rx", "tx", "rx";
 634                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 635                         resets = <&cpg 518>;
 636                         status = "disabled";
 637                 };
 638
 639                 hscif3: serial@e66a0000 {
 640                         compatible = "renesas,hscif-r8a7796",
 641                                      "renesas,rcar-gen3-hscif",
 642                                      "renesas,hscif";
 643                         reg = <0 0xe66a0000 0 0x60>;
 644                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 645                         clocks = <&cpg CPG_MOD 517>,
 646                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 647                                  <&scif_clk>;
 648                         clock-names = "fck", "brg_int", "scif_clk";
 649                         dmas = <&dmac0 0x37>, <&dmac0 0x36>;
 650                         dma-names = "tx", "rx";
 651                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 652                         resets = <&cpg 517>;
 653                         status = "disabled";
 654                 };
 655
 656                 hscif4: serial@e66b0000 {
 657                         compatible = "renesas,hscif-r8a7796",
 658                                      "renesas,rcar-gen3-hscif",
 659                                      "renesas,hscif";
 660                         reg = <0 0xe66b0000 0 0x60>;
 661                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 662                         clocks = <&cpg CPG_MOD 516>,
 663                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 664                                  <&scif_clk>;
 665                         clock-names = "fck", "brg_int", "scif_clk";
 666                         dmas = <&dmac0 0x39>, <&dmac0 0x38>;
 667                         dma-names = "tx", "rx";
 668                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 669                         resets = <&cpg 516>;
 670                         status = "disabled";
 671                 };
 672
 673                 scif0: serial@e6e60000 {
 674                         compatible = "renesas,scif-r8a7796",
 675                                      "renesas,rcar-gen3-scif", "renesas,scif";
 676                         reg = <0 0xe6e60000 0 64>;
 677                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 678                         clocks = <&cpg CPG_MOD 207>,
 679                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 680                                  <&scif_clk>;
 681                         clock-names = "fck", "brg_int", "scif_clk";
 682                         dmas = <&dmac1 0x51>, <&dmac1 0x50>,
 683                                <&dmac2 0x51>, <&dmac2 0x50>;
 684                         dma-names = "tx", "rx", "tx", "rx";
 685                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 686                         resets = <&cpg 207>;
 687                         status = "disabled";
 688                 };
 689
 690                 scif1: serial@e6e68000 {
 691                         compatible = "renesas,scif-r8a7796",
 692                                      "renesas,rcar-gen3-scif", "renesas,scif";
 693                         reg = <0 0xe6e68000 0 64>;
 694                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 695                         clocks = <&cpg CPG_MOD 206>,
 696                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 697                                  <&scif_clk>;
 698                         clock-names = "fck", "brg_int", "scif_clk";
 699                         dmas = <&dmac1 0x53>, <&dmac1 0x52>,
 700                                <&dmac2 0x53>, <&dmac2 0x52>;
 701                         dma-names = "tx", "rx", "tx", "rx";
 702                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 703                         resets = <&cpg 206>;
 704                         status = "disabled";
 705                 };
 706
 707                 scif2: serial@e6e88000 {
 708                         compatible = "renesas,scif-r8a7796",
 709                                      "renesas,rcar-gen3-scif", "renesas,scif";
 710                         reg = <0 0xe6e88000 0 64>;
 711                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 712                         clocks = <&cpg CPG_MOD 310>,
 713                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 714                                  <&scif_clk>;
 715                         clock-names = "fck", "brg_int", "scif_clk";
 716                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 717                         resets = <&cpg 310>;
 718                         status = "disabled";
 719                 };
 720
 721                 scif3: serial@e6c50000 {
 722                         compatible = "renesas,scif-r8a7796",
 723                                      "renesas,rcar-gen3-scif", "renesas,scif";
 724                         reg = <0 0xe6c50000 0 64>;
 725                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 726                         clocks = <&cpg CPG_MOD 204>,
 727                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 728                                  <&scif_clk>;
 729                         clock-names = "fck", "brg_int", "scif_clk";
 730                         dmas = <&dmac0 0x57>, <&dmac0 0x56>;
 731                         dma-names = "tx", "rx";
 732                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 733                         resets = <&cpg 204>;
 734                         status = "disabled";
 735                 };
 736
 737                 scif4: serial@e6c40000 {
 738                         compatible = "renesas,scif-r8a7796",
 739                                      "renesas,rcar-gen3-scif", "renesas,scif";
 740                         reg = <0 0xe6c40000 0 64>;
 741                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 742                         clocks = <&cpg CPG_MOD 203>,
 743                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 744                                  <&scif_clk>;
 745                         clock-names = "fck", "brg_int", "scif_clk";
 746                         dmas = <&dmac0 0x59>, <&dmac0 0x58>;
 747                         dma-names = "tx", "rx";
 748                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 749                         resets = <&cpg 203>;
 750                         status = "disabled";
 751                 };
 752
 753                 scif5: serial@e6f30000 {
 754                         compatible = "renesas,scif-r8a7796",
 755                                      "renesas,rcar-gen3-scif", "renesas,scif";
 756                         reg = <0 0xe6f30000 0 64>;
 757                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 758                         clocks = <&cpg CPG_MOD 202>,
 759                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 760                                  <&scif_clk>;
 761                         clock-names = "fck", "brg_int", "scif_clk";
 762                         dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
 763                                <&dmac2 0x5b>, <&dmac2 0x5a>;
 764                         dma-names = "tx", "rx", "tx", "rx";
 765                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 766                         resets = <&cpg 202>;
 767                         status = "disabled";
 768                 };
 769
 770                 msiof0: spi@e6e90000 {
 771                         compatible = "renesas,msiof-r8a7796",
 772                                      "renesas,rcar-gen3-msiof";
 773                         reg = <0 0xe6e90000 0 0x0064>;
 774                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 775                         clocks = <&cpg CPG_MOD 211>;
 776                         dmas = <&dmac1 0x41>, <&dmac1 0x40>,
 777                                <&dmac2 0x41>, <&dmac2 0x40>;
 778                         dma-names = "tx", "rx";
 779                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 780                         resets = <&cpg 211>;
 781                         #address-cells = <1>;
 782                         #size-cells = <0>;
 783                         status = "disabled";
 784                 };
 785
 786                 msiof1: spi@e6ea0000 {
 787                         compatible = "renesas,msiof-r8a7796",
 788                                      "renesas,rcar-gen3-msiof";
 789                         reg = <0 0xe6ea0000 0 0x0064>;
 790                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 791                         clocks = <&cpg CPG_MOD 210>;
 792                         dmas = <&dmac1 0x43>, <&dmac1 0x42>,
 793                                <&dmac2 0x43>, <&dmac2 0x42>;
 794                         dma-names = "tx", "rx";
 795                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 796                         resets = <&cpg 210>;
 797                         #address-cells = <1>;
 798                         #size-cells = <0>;
 799                         status = "disabled";
 800                 };
 801
 802                 msiof2: spi@e6c00000 {
 803                         compatible = "renesas,msiof-r8a7796",
 804                                      "renesas,rcar-gen3-msiof";
 805                         reg = <0 0xe6c00000 0 0x0064>;
 806                         interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 807                         clocks = <&cpg CPG_MOD 209>;
 808                         dmas = <&dmac0 0x45>, <&dmac0 0x44>;
 809                         dma-names = "tx", "rx";
 810                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 811                         resets = <&cpg 209>;
 812                         #address-cells = <1>;
 813                         #size-cells = <0>;
 814                         status = "disabled";
 815                 };
 816
 817                 msiof3: spi@e6c10000 {
 818                         compatible = "renesas,msiof-r8a7796",
 819                                      "renesas,rcar-gen3-msiof";
 820                         reg = <0 0xe6c10000 0 0x0064>;
 821                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 822                         clocks = <&cpg CPG_MOD 208>;
 823                         dmas = <&dmac0 0x47>, <&dmac0 0x46>;
 824                         dma-names = "tx", "rx";
 825                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 826                         resets = <&cpg 208>;
 827                         #address-cells = <1>;
 828                         #size-cells = <0>;
 829                         status = "disabled";
 830                 };
 831
 832                 dmac0: dma-controller@e6700000 {
 833                         compatible = "renesas,dmac-r8a7796",
 834                                      "renesas,rcar-dmac";
 835                         reg = <0 0xe6700000 0 0x10000>;
 836                         interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
 837                                       GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 838                                       GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 839                                       GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 840                                       GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 841                                       GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 842                                       GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 843                                       GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 844                                       GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 845                                       GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 846                                       GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 847                                       GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 848                                       GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 849                                       GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 850                                       GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 851                                       GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
 852                                       GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
 853                         interrupt-names = "error",
 854                                         "ch0", "ch1", "ch2", "ch3",
 855                                         "ch4", "ch5", "ch6", "ch7",
 856                                         "ch8", "ch9", "ch10", "ch11",
 857                                         "ch12", "ch13", "ch14", "ch15";
 858                         clocks = <&cpg CPG_MOD 219>;
 859                         clock-names = "fck";
 860                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 861                         resets = <&cpg 219>;
 862                         #dma-cells = <1>;
 863                         dma-channels = <16>;
 864                 };
 865
 866                 dmac1: dma-controller@e7300000 {
 867                         compatible = "renesas,dmac-r8a7796",
 868                                      "renesas,rcar-dmac";
 869                         reg = <0 0xe7300000 0 0x10000>;
 870                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 871                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 872                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 873                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 874                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 875                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 876                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 877                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 878                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 879                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 880                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 881                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 882                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 883                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 884                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 885                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
 886                                       GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
 887                         interrupt-names = "error",
 888                                         "ch0", "ch1", "ch2", "ch3",
 889                                         "ch4", "ch5", "ch6", "ch7",
 890                                         "ch8", "ch9", "ch10", "ch11",
 891                                         "ch12", "ch13", "ch14", "ch15";
 892                         clocks = <&cpg CPG_MOD 218>;
 893                         clock-names = "fck";
 894                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 895                         resets = <&cpg 218>;
 896                         #dma-cells = <1>;
 897                         dma-channels = <16>;
 898                 };
 899
 900                 dmac2: dma-controller@e7310000 {
 901                         compatible = "renesas,dmac-r8a7796",
 902                                      "renesas,rcar-dmac";
 903                         reg = <0 0xe7310000 0 0x10000>;
 904                         interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
 905                                       GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
 906                                       GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
 907                                       GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
 908                                       GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
 909                                       GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
 910                                       GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
 911                                       GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
 912                                       GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
 913                                       GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
 914                                       GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
 915                                       GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
 916                                       GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
 917                                       GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
 918                                       GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
 919                                       GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
 920                                       GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
 921                         interrupt-names = "error",
 922                                         "ch0", "ch1", "ch2", "ch3",
 923                                         "ch4", "ch5", "ch6", "ch7",
 924                                         "ch8", "ch9", "ch10", "ch11",
 925                                         "ch12", "ch13", "ch14", "ch15";
 926                         clocks = <&cpg CPG_MOD 217>;
 927                         clock-names = "fck";
 928                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 929                         resets = <&cpg 217>;
 930                         #dma-cells = <1>;
 931                         dma-channels = <16>;
 932                 };
 933
 934                 sdhi0: sd@ee100000 {
 935                         compatible = "renesas,sdhi-r8a7796";
 936                         reg = <0 0xee100000 0 0x2000>;
 937                         interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 938                         clocks = <&cpg CPG_MOD 314>;
 939                         max-frequency = <200000000>;
 940                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 941                         resets = <&cpg 314>;
 942                         status = "disabled";
 943                 };
 944
 945                 sdhi1: sd@ee120000 {
 946                         compatible = "renesas,sdhi-r8a7796";
 947                         reg = <0 0xee120000 0 0x2000>;
 948                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 949                         clocks = <&cpg CPG_MOD 313>;
 950                         max-frequency = <200000000>;
 951                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 952                         resets = <&cpg 313>;
 953                         status = "disabled";
 954                 };
 955
 956                 sdhi2: sd@ee140000 {
 957                         compatible = "renesas,sdhi-r8a7796";
 958                         reg = <0 0xee140000 0 0x2000>;
 959                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 960                         clocks = <&cpg CPG_MOD 312>;
 961                         max-frequency = <200000000>;
 962                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 963                         resets = <&cpg 312>;
 964                         status = "disabled";
 965                 };
 966
 967                 sdhi3: sd@ee160000 {
 968                         compatible = "renesas,sdhi-r8a7796";
 969                         reg = <0 0xee160000 0 0x2000>;
 970                         interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 971                         clocks = <&cpg CPG_MOD 311>;
 972                         max-frequency = <200000000>;
 973                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 974                         resets = <&cpg 311>;
 975                         status = "disabled";
 976                 };
 977
 978                 tsc: thermal@e6198000 {
 979                         compatible = "renesas,r8a7796-thermal";
 980                         reg = <0 0xe6198000 0 0x68>,
 981                               <0 0xe61a0000 0 0x5c>,
 982                               <0 0xe61a8000 0 0x5c>;
 983                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 984                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 985                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 986                         clocks = <&cpg CPG_MOD 522>;
 987                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
 988                         resets = <&cpg 522>;
 989                         #thermal-sensor-cells = <1>;
 990                         status = "okay";
 991                 };
 992
 993                 thermal-zones {
 994                         sensor_thermal1: sensor-thermal1 {
 995                                 polling-delay-passive = <250>;
 996                                 polling-delay = <1000>;
 997                                 thermal-sensors = <&tsc 0>;
 998
 999                                 trips {
1000                                         sensor1_crit: sensor1-crit {
1001                                                 temperature = <120000>;
1002                                                 hysteresis = <2000>;
1003                                                 type = "critical";
1004                                         };
1005                                 };
1006                         };
1007
1008                         sensor_thermal2: sensor-thermal2 {
1009                                 polling-delay-passive = <250>;
1010                                 polling-delay = <1000>;
1011                                 thermal-sensors = <&tsc 1>;
1012
1013                                 trips {
1014                                         sensor2_crit: sensor2-crit {
1015                                                 temperature = <120000>;
1016                                                 hysteresis = <2000>;
1017                                                 type = "critical";
1018                                         };
1019                                 };
1020                         };
1021
1022                         sensor_thermal3: sensor-thermal3 {
1023                                 polling-delay-passive = <250>;
1024                                 polling-delay = <1000>;
1025                                 thermal-sensors = <&tsc 2>;
1026
1027                                 trips {
1028                                         sensor3_crit: sensor3-crit {
1029                                                 temperature = <120000>;
1030                                                 hysteresis = <2000>;
1031                                                 type = "critical";
1032                                         };
1033                                 };
1034                         };
1035                 };
1036         };
1037 };