git.sur5r.net Git - u-boot/blob - arch/arm/dts/r8a77990.dtsi

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Device Tree Source for the r8a77990 SoC
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10
  11 / {
  12         compatible = "renesas,r8a77990";
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 /* 1 core only at this point */
  21                 a53_0: cpu@0 {
  22                         compatible = "arm,cortex-a53", "arm,armv8";
  23                         reg = <0x0>;
  24                         device_type = "cpu";
  25                         power-domains = <&sysc 5>;
  26                         next-level-cache = <&L2_CA53>;
  27                         enable-method = "psci";
  28                 };
  29
  30                 L2_CA53: cache-controller-0 {
  31                         compatible = "cache";
  32                         power-domains = <&sysc 21>;
  33                         cache-unified;
  34                         cache-level = <2>;
  35                 };
  36         };
  37
  38         extal_clk: extal {
  39                 compatible = "fixed-clock";
  40                 #clock-cells = <0>;
  41                 /* This value must be overridden by the board */
  42                 clock-frequency = <0>;
  43         };
  44
  45         pmu_a53 {
  46                 compatible = "arm,cortex-a53-pmu";
  47                 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
  48                 interrupt-affinity = <&a53_0>;
  49         };
  50
  51         psci {
  52                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  53                 method = "smc";
  54         };
  55
  56         soc: soc {
  57                 compatible = "simple-bus";
  58                 interrupt-parent = <&gic>;
  59                 #address-cells = <2>;
  60                 #size-cells = <2>;
  61                 ranges;
  62
  63                 gpio0: gpio@e6050000 {
  64                         compatible = "renesas,gpio-r8a77990",
  65                                      "renesas,rcar-gen3-gpio";
  66                         reg = <0 0xe6050000 0 0x50>;
  67                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  68                         #gpio-cells = <2>;
  69                         gpio-controller;
  70                         gpio-ranges = <&pfc 0 0 18>;
  71                         #interrupt-cells = <2>;
  72                         interrupt-controller;
  73                         clocks = <&cpg CPG_MOD 912>;
  74                         power-domains = <&sysc 32>;
  75                         resets = <&cpg 912>;
  76                 };
  77
  78                 gpio1: gpio@e6051000 {
  79                         compatible = "renesas,gpio-r8a77990",
  80                                      "renesas,rcar-gen3-gpio";
  81                         reg = <0 0xe6051000 0 0x50>;
  82                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  83                         #gpio-cells = <2>;
  84                         gpio-controller;
  85                         gpio-ranges = <&pfc 0 32 23>;
  86                         #interrupt-cells = <2>;
  87                         interrupt-controller;
  88                         clocks = <&cpg CPG_MOD 911>;
  89                         power-domains = <&sysc 32>;
  90                         resets = <&cpg 911>;
  91                 };
  92
  93                 gpio2: gpio@e6052000 {
  94                         compatible = "renesas,gpio-r8a77990",
  95                                      "renesas,rcar-gen3-gpio";
  96                         reg = <0 0xe6052000 0 0x50>;
  97                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  98                         #gpio-cells = <2>;
  99                         gpio-controller;
 100                         gpio-ranges = <&pfc 0 64 26>;
 101                         #interrupt-cells = <2>;
 102                         interrupt-controller;
 103                         clocks = <&cpg CPG_MOD 910>;
 104                         power-domains = <&sysc 32>;
 105                         resets = <&cpg 910>;
 106                 };
 107
 108                 gpio3: gpio@e6053000 {
 109                         compatible = "renesas,gpio-r8a77990",
 110                                      "renesas,rcar-gen3-gpio";
 111                         reg = <0 0xe6053000 0 0x50>;
 112                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 113                         #gpio-cells = <2>;
 114                         gpio-controller;
 115                         gpio-ranges = <&pfc 0 96 16>;
 116                         #interrupt-cells = <2>;
 117                         interrupt-controller;
 118                         clocks = <&cpg CPG_MOD 909>;
 119                         power-domains = <&sysc 32>;
 120                         resets = <&cpg 909>;
 121                 };
 122
 123                 gpio4: gpio@e6054000 {
 124                         compatible = "renesas,gpio-r8a77990",
 125                                      "renesas,rcar-gen3-gpio";
 126                         reg = <0 0xe6054000 0 0x50>;
 127                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 128                         #gpio-cells = <2>;
 129                         gpio-controller;
 130                         gpio-ranges = <&pfc 0 128 11>;
 131                         #interrupt-cells = <2>;
 132                         interrupt-controller;
 133                         clocks = <&cpg CPG_MOD 908>;
 134                         power-domains = <&sysc 32>;
 135                         resets = <&cpg 908>;
 136                 };
 137
 138                 gpio5: gpio@e6055000 {
 139                         compatible = "renesas,gpio-r8a77990",
 140                                      "renesas,rcar-gen3-gpio";
 141                         reg = <0 0xe6055000 0 0x50>;
 142                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 143                         #gpio-cells = <2>;
 144                         gpio-controller;
 145                         gpio-ranges = <&pfc 0 160 20>;
 146                         #interrupt-cells = <2>;
 147                         interrupt-controller;
 148                         clocks = <&cpg CPG_MOD 907>;
 149                         power-domains = <&sysc 32>;
 150                         resets = <&cpg 907>;
 151                 };
 152
 153                 gpio6: gpio@e6055400 {
 154                         compatible = "renesas,gpio-r8a77990",
 155                                      "renesas,rcar-gen3-gpio";
 156                         reg = <0 0xe6055400 0 0x50>;
 157                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 158                         #gpio-cells = <2>;
 159                         gpio-controller;
 160                         gpio-ranges = <&pfc 0 192 18>;
 161                         #interrupt-cells = <2>;
 162                         interrupt-controller;
 163                         clocks = <&cpg CPG_MOD 906>;
 164                         power-domains = <&sysc 32>;
 165                         resets = <&cpg 906>;
 166                 };
 167
 168                 pfc: pin-controller@e6060000 {
 169                         compatible = "renesas,pfc-r8a77990";
 170                         reg = <0 0xe6060000 0 0x508>;
 171                 };
 172
 173                 cpg: clock-controller@e6150000 {
 174                         compatible = "renesas,r8a77990-cpg-mssr";
 175                         reg = <0 0xe6150000 0 0x1000>;
 176                         clocks = <&extal_clk>;
 177                         clock-names = "extal";
 178                         #clock-cells = <2>;
 179                         #power-domain-cells = <0>;
 180                         #reset-cells = <1>;
 181                 };
 182
 183                 rst: reset-controller@e6160000 {
 184                         compatible = "renesas,r8a77990-rst";
 185                         reg = <0 0xe6160000 0 0x0200>;
 186                 };
 187
 188                 sdhi0: sd@ee100000 {
 189                         compatible = "renesas,sdhi-r8a77990";
 190                         reg = <0 0xee100000 0 0x2000>;
 191                         clocks = <&cpg CPG_MOD 314>;
 192                         max-frequency = <200000000>;
 193                         status = "disabled";
 194                 };
 195
 196                 sdhi1: sd@ee120000 {
 197                         compatible = "renesas,sdhi-r8a77990";
 198                         reg = <0 0xee120000 0 0x2000>;
 199                         clocks = <&cpg CPG_MOD 313>;
 200                         max-frequency = <200000000>;
 201                         status = "disabled";
 202                 };
 203
 204                 sdhi3: sd@ee160000 {
 205                         compatible = "renesas,sdhi-r8a77990";
 206                         reg = <0 0xee160000 0 0x2000>;
 207                         clocks = <&cpg CPG_MOD 311>;
 208                         max-frequency = <200000000>;
 209                         status = "disabled";
 210                 };
 211
 212                 sysc: system-controller@e6180000 {
 213                         compatible = "renesas,r8a77990-sysc";
 214                         reg = <0 0xe6180000 0 0x0400>;
 215                         #power-domain-cells = <1>;
 216                 };
 217
 218                 avb: ethernet@e6800000 {
 219                         compatible = "renesas,etheravb-r8a77990",
 220                                      "renesas,etheravb-rcar-gen3";
 221                         reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
 222                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 223                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 224                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 225                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 226                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 227                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 228                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 229                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 230                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 231                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 232                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 233                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 234                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 235                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 236                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 237                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 238                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 239                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 240                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 241                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 242                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 243                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 244                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 245                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 246                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 247                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 248                                           "ch4", "ch5", "ch6", "ch7",
 249                                           "ch8", "ch9", "ch10", "ch11",
 250                                           "ch12", "ch13", "ch14", "ch15",
 251                                           "ch16", "ch17", "ch18", "ch19",
 252                                           "ch20", "ch21", "ch22", "ch23",
 253                                           "ch24";
 254                         clocks = <&cpg CPG_MOD 812>;
 255                         power-domains = <&sysc 32>;
 256                         resets = <&cpg 812>;
 257                         phy-mode = "rgmii";
 258                         #address-cells = <1>;
 259                         #size-cells = <0>;
 260                         status = "disabled";
 261                 };
 262
 263                 scif2: serial@e6e88000 {
 264                         compatible = "renesas,scif-r8a77990",
 265                                      "renesas,rcar-gen3-scif", "renesas,scif";
 266                         reg = <0 0xe6e88000 0 64>;
 267                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 268                         clocks = <&cpg CPG_MOD 310>;
 269                         clock-names = "fck";
 270                         power-domains = <&sysc 32>;
 271                         resets = <&cpg 310>;
 272                         status = "disabled";
 273                 };
 274
 275                 gic: interrupt-controller@f1010000 {
 276                         compatible = "arm,gic-400";
 277                         #interrupt-cells = <3>;
 278                         #address-cells = <0>;
 279                         interrupt-controller;
 280                         reg = <0x0 0xf1010000 0 0x1000>,
 281                               <0x0 0xf1020000 0 0x20000>,
 282                               <0x0 0xf1040000 0 0x20000>,
 283                               <0x0 0xf1060000 0 0x20000>;
 284                         interrupts = <GIC_PPI 9
 285                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
 286                         clocks = <&cpg CPG_MOD 408>;
 287                         clock-names = "clk";
 288                         power-domains = <&sysc 32>;
 289                         resets = <&cpg 408>;
 290                 };
 291
 292                 prr: chipid@fff00044 {
 293                         compatible = "renesas,prr";
 294                         reg = <0 0xfff00044 0 4>;
 295                 };
 296
 297                 rpc: rpc@0xee200000 {
 298                         compatible = "renesas,rpc-r8a77990", "renesas,rpc";
 299                         reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
 300                         clocks = <&cpg CPG_MOD 917>;
 301                         bank-width = <2>;
 302                         status = "disabled";
 303                 };
 304         };
 305
 306         timer {
 307                 compatible = "arm,armv8-timer";
 308                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 309                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 310                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 311                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
 312         };
 313 };