git.sur5r.net Git - u-boot/blob - arch/arm/dts/r8a77995.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the r8a77995 SoC
   4  *
   5  * Copyright (C) 2016 Renesas Electronics Corp.
   6  * Copyright (C) 2017 Glider bvba
   7  */
   8
   9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/power/r8a77995-sysc.h>
  12
  13 / {
  14         compatible = "renesas,r8a77995";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         psci {
  19                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  20                 method = "smc";
  21         };
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 a53_0: cpu@0 {
  28                         compatible = "arm,cortex-a53", "arm,armv8";
  29                         reg = <0x0>;
  30                         device_type = "cpu";
  31                         power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
  32                         next-level-cache = <&L2_CA53>;
  33                         enable-method = "psci";
  34                 };
  35
  36                 L2_CA53: cache-controller-1 {
  37                         compatible = "cache";
  38                         power-domains = <&sysc R8A77995_PD_CA53_SCU>;
  39                         cache-unified;
  40                         cache-level = <2>;
  41                 };
  42         };
  43
  44         extal_clk: extal {
  45                 compatible = "fixed-clock";
  46                 #clock-cells = <0>;
  47                 /* This value must be overridden by the board */
  48                 clock-frequency = <0>;
  49         };
  50
  51         scif_clk: scif {
  52                 compatible = "fixed-clock";
  53                 #clock-cells = <0>;
  54                 clock-frequency = <0>;
  55         };
  56
  57         soc {
  58                 compatible = "simple-bus";
  59                 interrupt-parent = <&gic>;
  60                 #address-cells = <2>;
  61                 #size-cells = <2>;
  62                 ranges;
  63
  64                 gic: interrupt-controller@f1010000 {
  65                         compatible = "arm,gic-400";
  66                         #interrupt-cells = <3>;
  67                         #address-cells = <0>;
  68                         interrupt-controller;
  69                         reg = <0x0 0xf1010000 0 0x1000>,
  70                               <0x0 0xf1020000 0 0x20000>,
  71                               <0x0 0xf1040000 0 0x20000>,
  72                               <0x0 0xf1060000 0 0x20000>;
  73                         interrupts = <GIC_PPI 9
  74                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
  75                         clocks = <&cpg CPG_MOD 408>;
  76                         clock-names = "clk";
  77                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
  78                         resets = <&cpg 408>;
  79                 };
  80
  81                 timer {
  82                         compatible = "arm,armv8-timer";
  83                         interrupts = <GIC_PPI 13
  84                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  85                                      <GIC_PPI 14
  86                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  87                                      <GIC_PPI 11
  88                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  89                                      <GIC_PPI 10
  90                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
  91                 };
  92
  93                 rwdt: watchdog@e6020000 {
  94                         compatible = "renesas,r8a77995-wdt",
  95                                      "renesas,rcar-gen3-wdt";
  96                         reg = <0 0xe6020000 0 0x0c>;
  97                         clocks = <&cpg CPG_MOD 402>;
  98                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
  99                         resets = <&cpg 402>;
 100                         status = "disabled";
 101                 };
 102
 103                 pmu_a53 {
 104                         compatible = "arm,cortex-a53-pmu";
 105                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 106                 };
 107
 108                 cpg: clock-controller@e6150000 {
 109                         compatible = "renesas,r8a77995-cpg-mssr";
 110                         reg = <0 0xe6150000 0 0x1000>;
 111                         clocks = <&extal_clk>;
 112                         clock-names = "extal";
 113                         #clock-cells = <2>;
 114                         #power-domain-cells = <0>;
 115                         #reset-cells = <1>;
 116                 };
 117
 118                 rst: reset-controller@e6160000 {
 119                         compatible = "renesas,r8a77995-rst";
 120                         reg = <0 0xe6160000 0 0x0200>;
 121                 };
 122
 123                 pfc: pin-controller@e6060000 {
 124                         compatible = "renesas,pfc-r8a77995";
 125                         reg = <0 0xe6060000 0 0x508>;
 126                 };
 127
 128                 prr: chipid@fff00044 {
 129                         compatible = "renesas,prr";
 130                         reg = <0 0xfff00044 0 4>;
 131                 };
 132
 133                 sysc: system-controller@e6180000 {
 134                         compatible = "renesas,r8a77995-sysc";
 135                         reg = <0 0xe6180000 0 0x0400>;
 136                         #power-domain-cells = <1>;
 137                 };
 138
 139                 intc_ex: interrupt-controller@e61c0000 {
 140                         compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
 141                         #interrupt-cells = <2>;
 142                         interrupt-controller;
 143                         reg = <0 0xe61c0000 0 0x200>;
 144                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
 145                                       GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
 146                                       GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
 147                                       GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
 148                                       GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
 149                                       GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 150                         clocks = <&cpg CPG_MOD 407>;
 151                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 152                         resets = <&cpg 407>;
 153                 };
 154
 155                 gpio0: gpio@e6050000 {
 156                         compatible = "renesas,gpio-r8a77995",
 157                                      "renesas,rcar-gen3-gpio",
 158                                      "renesas,gpio-rcar";
 159                         reg = <0 0xe6050000 0 0x50>;
 160                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 161                         #gpio-cells = <2>;
 162                         gpio-controller;
 163                         gpio-ranges = <&pfc 0 0 9>;
 164                         #interrupt-cells = <2>;
 165                         interrupt-controller;
 166                         clocks = <&cpg CPG_MOD 912>;
 167                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 168                         resets = <&cpg 912>;
 169                 };
 170
 171                 gpio1: gpio@e6051000 {
 172                         compatible = "renesas,gpio-r8a77995",
 173                                      "renesas,rcar-gen3-gpio",
 174                                      "renesas,gpio-rcar";
 175                         reg = <0 0xe6051000 0 0x50>;
 176                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 177                         #gpio-cells = <2>;
 178                         gpio-controller;
 179                         gpio-ranges = <&pfc 0 32 32>;
 180                         #interrupt-cells = <2>;
 181                         interrupt-controller;
 182                         clocks = <&cpg CPG_MOD 911>;
 183                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 184                         resets = <&cpg 911>;
 185                 };
 186
 187                 gpio2: gpio@e6052000 {
 188                         compatible = "renesas,gpio-r8a77995",
 189                                      "renesas,rcar-gen3-gpio",
 190                                      "renesas,gpio-rcar";
 191                         reg = <0 0xe6052000 0 0x50>;
 192                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 193                         #gpio-cells = <2>;
 194                         gpio-controller;
 195                         gpio-ranges = <&pfc 0 64 32>;
 196                         #interrupt-cells = <2>;
 197                         interrupt-controller;
 198                         clocks = <&cpg CPG_MOD 910>;
 199                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 200                         resets = <&cpg 910>;
 201                 };
 202
 203                 gpio3: gpio@e6053000 {
 204                         compatible = "renesas,gpio-r8a77995",
 205                                      "renesas,rcar-gen3-gpio",
 206                                      "renesas,gpio-rcar";
 207                         reg = <0 0xe6053000 0 0x50>;
 208                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 209                         #gpio-cells = <2>;
 210                         gpio-controller;
 211                         gpio-ranges = <&pfc 0 96 10>;
 212                         #interrupt-cells = <2>;
 213                         interrupt-controller;
 214                         clocks = <&cpg CPG_MOD 909>;
 215                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 216                         resets = <&cpg 909>;
 217                 };
 218
 219                 gpio4: gpio@e6054000 {
 220                         compatible = "renesas,gpio-r8a77995",
 221                                      "renesas,rcar-gen3-gpio",
 222                                      "renesas,gpio-rcar";
 223                         reg = <0 0xe6054000 0 0x50>;
 224                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 225                         #gpio-cells = <2>;
 226                         gpio-controller;
 227                         gpio-ranges = <&pfc 0 128 32>;
 228                         #interrupt-cells = <2>;
 229                         interrupt-controller;
 230                         clocks = <&cpg CPG_MOD 908>;
 231                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 232                         resets = <&cpg 908>;
 233                 };
 234
 235                 gpio5: gpio@e6055000 {
 236                         compatible = "renesas,gpio-r8a77995",
 237                                      "renesas,rcar-gen3-gpio",
 238                                      "renesas,gpio-rcar";
 239                         reg = <0 0xe6055000 0 0x50>;
 240                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 241                         #gpio-cells = <2>;
 242                         gpio-controller;
 243                         gpio-ranges = <&pfc 0 160 21>;
 244                         #interrupt-cells = <2>;
 245                         interrupt-controller;
 246                         clocks = <&cpg CPG_MOD 907>;
 247                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 248                         resets = <&cpg 907>;
 249                 };
 250
 251                 gpio6: gpio@e6055400 {
 252                         compatible = "renesas,gpio-r8a77995",
 253                                      "renesas,rcar-gen3-gpio",
 254                                      "renesas,gpio-rcar";
 255                         reg = <0 0xe6055400 0 0x50>;
 256                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 257                         #gpio-cells = <2>;
 258                         gpio-controller;
 259                         gpio-ranges = <&pfc 0 192 14>;
 260                         #interrupt-cells = <2>;
 261                         interrupt-controller;
 262                         clocks = <&cpg CPG_MOD 906>;
 263                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 264                         resets = <&cpg 906>;
 265                 };
 266
 267                 avb: ethernet@e6800000 {
 268                         compatible = "renesas,etheravb-r8a77995",
 269                                      "renesas,etheravb-rcar-gen3";
 270                         reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
 271                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 272                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 273                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 274                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 275                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 276                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 277                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 278                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 279                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 280                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 281                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 282                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 283                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 284                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 285                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 286                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 287                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 288                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 289                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 290                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 291                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 292                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 293                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 294                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 295                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 296                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 297                                           "ch4", "ch5", "ch6", "ch7",
 298                                           "ch8", "ch9", "ch10", "ch11",
 299                                           "ch12", "ch13", "ch14", "ch15",
 300                                           "ch16", "ch17", "ch18", "ch19",
 301                                           "ch20", "ch21", "ch22", "ch23",
 302                                           "ch24";
 303                         clocks = <&cpg CPG_MOD 812>;
 304                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 305                         resets = <&cpg 812>;
 306                         phy-mode = "rgmii-txid";
 307                         #address-cells = <1>;
 308                         #size-cells = <0>;
 309                         status = "disabled";
 310                 };
 311
 312                 scif2: serial@e6e88000 {
 313                         compatible = "renesas,scif-r8a77995",
 314                                      "renesas,rcar-gen3-scif", "renesas,scif";
 315                         reg = <0 0xe6e88000 0 64>;
 316                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 317                         clocks = <&cpg CPG_MOD 310>,
 318                                  <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
 319                                  <&scif_clk>;
 320                         clock-names = "fck", "brg_int", "scif_clk";
 321                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 322                         resets = <&cpg 310>;
 323                         status = "disabled";
 324                 };
 325
 326                 pwm0: pwm@e6e30000 {
 327                         compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
 328                         reg = <0 0xe6e30000 0 0x8>;
 329                         #pwm-cells = <2>;
 330                         clocks = <&cpg CPG_MOD 523>;
 331                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 332                         resets = <&cpg 523>;
 333                         status = "disabled";
 334                 };
 335
 336                 pwm1: pwm@e6e31000 {
 337                         compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
 338                         reg = <0 0xe6e31000 0 0x8>;
 339                         #pwm-cells = <2>;
 340                         clocks = <&cpg CPG_MOD 523>;
 341                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 342                         resets = <&cpg 523>;
 343                         status = "disabled";
 344                 };
 345
 346                 pwm2: pwm@e6e32000 {
 347                         compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
 348                         reg = <0 0xe6e32000 0 0x8>;
 349                         #pwm-cells = <2>;
 350                         clocks = <&cpg CPG_MOD 523>;
 351                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 352                         resets = <&cpg 523>;
 353                         status = "disabled";
 354                 };
 355
 356                 pwm3: pwm@e6e33000 {
 357                         compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
 358                         reg = <0 0xe6e33000 0 0x8>;
 359                         #pwm-cells = <2>;
 360                         clocks = <&cpg CPG_MOD 523>;
 361                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 362                         resets = <&cpg 523>;
 363                         status = "disabled";
 364                 };
 365
 366                 ehci0: usb@ee080100 {
 367                         compatible = "generic-ehci";
 368                         reg = <0 0xee080100 0 0x100>;
 369                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 370                         clocks = <&cpg CPG_MOD 703>;
 371                         phys = <&usb2_phy0>;
 372                         phy-names = "usb";
 373                         companion = <&ohci0>;
 374                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 375                         resets = <&cpg 703>;
 376                         status = "disabled";
 377                 };
 378
 379                 ohci0: usb@ee080000 {
 380                         compatible = "generic-ohci";
 381                         reg = <0 0xee080000 0 0x100>;
 382                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 383                         clocks = <&cpg CPG_MOD 703>;
 384                         phys = <&usb2_phy0>;
 385                         phy-names = "usb";
 386                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 387                         resets = <&cpg 703>;
 388                         status = "disabled";
 389                 };
 390
 391                 usb2_phy0: usb-phy@ee080200 {
 392                         compatible = "renesas,usb2-phy-r8a77995",
 393                                      "renesas,rcar-gen3-usb2-phy";
 394                         reg = <0 0xee080200 0 0x700>;
 395                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 396                         clocks = <&cpg CPG_MOD 703>;
 397                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 398                         resets = <&cpg 703>;
 399                         #phy-cells = <0>;
 400                         status = "disabled";
 401                 };
 402
 403                 rpc: rpc@0xee200000 {
 404                         compatible = "renesas,rpc-r8a77995", "renesas,rpc";
 405                         reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
 406                         clocks = <&cpg CPG_MOD 917>;
 407                         bank-width = <2>;
 408                         status = "disabled";
 409                 };
 410         };
 411 };