2 * Google Veyron Jerry Rev 3+ board device tree source
4 * Copyright 2014 Google, Inc
6 * SPDX-License-Identifier: GPL-2.0
10 #include "rk3288-veyron-chromebook.dtsi"
11 #include "cros-ec-sbs.dtsi"
14 model = "Google Jerry";
15 compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
16 "google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
17 "google,veyron-jerry-rev3", "google,veyron-jerry",
18 "google,veyron", "rockchip,rk3288";
24 panel_regulator: panel-regualtor {
25 compatible = "regulator-fixed";
27 gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
28 pinctrl-names = "default";
29 pinctrl-0 = <&lcd_enable_h>;
30 regulator-name = "panel_regulator";
31 vin-supply = <&vcc33_sys>;
34 vcc18_lcd: vcc18-lcd {
35 compatible = "regulator-fixed";
37 gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
38 pinctrl-names = "default";
39 pinctrl-0 = <&avdd_1v8_disp_en>;
40 regulator-name = "vcc18_lcd";
43 vin-supply = <&vcc18_wl>;
46 backlight_regulator: backlight-regulator {
47 compatible = "regulator-fixed";
49 gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
50 pinctrl-names = "default";
51 pinctrl-0 = <&bl_pwr_en>;
52 regulator-name = "backlight_regulator";
53 vin-supply = <&vcc33_sys>;
54 startup-delay-us = <15000>;
59 rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
60 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
61 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
62 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
64 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
66 rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
71 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
76 power-supply = <&backlight_regulator>;
80 power-supply= <&panel_regulator>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
86 dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
87 <&gpio7 15 GPIO_ACTIVE_HIGH>;
93 regulator-min-microvolt = <1800000>;
94 regulator-max-microvolt = <1800000>;
95 regulator-name = "mic_vcc";
96 regulator-suspend-mem-disabled;
102 pinctrl-names = "default";
103 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
110 gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
111 pinctrl-names = "default";
112 pinctrl-0 = <&drv_5v>;
117 gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
118 pinctrl-names = "default";
119 pinctrl-0 = <&vcc50_hdmi_en>;
123 pinctrl-names = "default";
124 pinctrl-0 = <&edp_hpd>;
129 bl_pwr_en: bl_pwr_en {
130 rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
136 rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
142 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
147 /* Make sure eMMC is not in reset */
148 emmc_deassert_reset: emmc-deassert-reset {
149 rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
154 vcc50_hdmi_en: vcc50-hdmi-en {
155 rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
160 lcd_enable_h: lcd-en {
161 rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
164 avdd_1v8_disp_en: avdd-1v8-disp-en {
165 rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
171 rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
175 rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
184 * Trackpad pin control is shared between Elan and Synaptics devices
185 * so we have to pull it up to the bus level.
187 pinctrl-names = "default";
188 pinctrl-0 = <&i2c4_xfer &trackpad_int>;
191 compatible = "elan,i2c_touchpad";
192 interrupt-parent = <&gpio7>;
193 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
195 * Remove the inherited pinctrl settings to avoid clashing
196 * with bus-wide ones.
198 /delete-property/pinctrl-names;
199 /delete-property/pinctrl-0;
201 vcc-supply = <&vcc33_io>;
206 compatible = "hid-over-i2c";
207 interrupt-parent = <&gpio7>;
208 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
210 hid-descr-addr = <0x0020>;
211 vcc-supply = <&vcc33_io>;