2 * Google Veyron (and derivatives) board device tree source
4 * Copyright 2014 Google, Inc
6 * SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/rockchip,rk808.h>
10 #include <dt-bindings/input/input.h>
11 #include "rk3288.dtsi"
15 reg = <0x0 0x80000000>;
24 u-boot,boot0 = &spi_flash;
29 pinctrl-names = "default";
30 pinctrl-0 = <&fw_wp_ap>;
31 write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>;
35 backlight: backlight {
36 compatible = "pwm-backlight";
40 16 17 18 19 20 21 22 23
41 24 25 26 27 28 29 30 31
42 32 33 34 35 36 37 38 39
43 40 41 42 43 44 45 46 47
44 48 49 50 51 52 53 54 55
45 56 57 58 59 60 61 62 63
46 64 65 66 67 68 69 70 71
47 72 73 74 75 76 77 78 79
48 80 81 82 83 84 85 86 87
49 88 89 90 91 92 93 94 95
50 96 97 98 99 100 101 102 103
51 104 105 106 107 108 109 110 111
52 112 113 114 115 116 117 118 119
53 120 121 122 123 124 125 126 127
54 128 129 130 131 132 133 134 135
55 136 137 138 139 140 141 142 143
56 144 145 146 147 148 149 150 151
57 152 153 154 155 156 157 158 159
58 160 161 162 163 164 165 166 167
59 168 169 170 171 172 173 174 175
60 176 177 178 179 180 181 182 183
61 184 185 186 187 188 189 190 191
62 192 193 194 195 196 197 198 199
63 200 201 202 203 204 205 206 207
64 208 209 210 211 212 213 214 215
65 216 217 218 219 220 221 222 223
66 224 225 226 227 228 229 230 231
67 232 233 234 235 236 237 238 239
68 240 241 242 243 244 245 246 247
69 248 249 250 251 252 253 254 255>;
70 default-brightness-level = <128>;
71 enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
73 pinctrl-names = "default";
75 pwms = <&pwm0 0 1000000 0>;
79 compatible ="cnm,n116bgeea2","simple-panel";
81 power-supply = <&vcc33_lcd>;
82 backlight = <&backlight>;
85 gpio_keys: gpio-keys {
86 compatible = "gpio-keys";
90 pinctrl-names = "default";
91 pinctrl-0 = <&pwr_key_h>;
94 gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
95 linux,code = <KEY_POWER>;
96 debounce-interval = <100>;
102 compatible = "gpio-restart";
103 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&ap_warm_reset_h>;
106 priority = /bits/ 8 <200>;
110 compatible = "rockchip,rockchip-audio-max98090";
111 rockchip,model = "ROCKCHIP-I2S";
112 rockchip,i2s-controller = <&i2s>;
113 rockchip,audio-codec = <&max98090>;
114 rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
115 rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
116 rockchip,headset-codec = <&headsetcodec>;
117 pinctrl-names = "default";
118 pinctrl-0 = <&mic_det>, <&hp_det>;
121 vdd_logic: pwm-regulator {
122 compatible = "pwm-regulator";
123 pwms = <&pwm1 0 2000 0>;
125 voltage-table = <1350000 0>,
135 regulator-min-microvolt = <950000>;
136 regulator-max-microvolt = <1350000>;
137 regulator-name = "vdd_logic";
138 regulator-ramp-delay = <4000>;
141 vcc33_sys: vcc33-sys {
142 compatible = "regulator-fixed";
143 regulator-name = "vcc33_sys";
146 regulator-min-microvolt = <3300000>;
147 regulator-max-microvolt = <3300000>;
148 vin-supply = <&vccsys>;
152 compatible = "regulator-fixed";
153 regulator-name = "vcc_5v";
156 regulator-min-microvolt = <5000000>;
157 regulator-max-microvolt = <5000000>;
160 vcc50_hdmi: vcc50-hdmi {
161 compatible = "regulator-fixed";
162 regulator-name = "vcc50_hdmi";
165 vin-supply = <&vcc_5v>;
168 bt_regulator: bt-regulator {
170 * On the module itself this is one of these (depending
171 * on the actual card pouplated):
172 * - BT_I2S_WS_BT_RFDISABLE_L
176 compatible = "regulator-fixed";
178 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
179 pinctrl-names = "default";
180 pinctrl-0 = <&bt_enable_l>;
181 regulator-name = "bt_regulator";
184 wifi_regulator: wifi-regulator {
186 * On the module itself this is one of these (depending
187 * on the actual card populated):
188 * - SDIO_RESET_L_WL_REG_ON
189 * - PDN (power down when low)
192 compatible = "regulator-fixed";
194 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
195 pinctrl-names = "default";
196 pinctrl-0 = <&wifi_enable_h>;
197 regulator-name = "wifi_regulator";
199 /* Faux input supply. See bt_regulator description. */
200 vin-supply = <&bt_regulator>;
204 compatible = "rockchip,rk3288-io-voltage-domain";
205 rockchip,grf = <&grf>;
207 audio-supply = <&vcc18_codec>;
208 bb-supply = <&vcc33_io>;
209 dvp-supply = <&vcc_18>;
210 flash0-supply = <&vcc18_flashio>;
211 gpio1830-supply = <&vcc33_io>;
212 gpio30-supply = <&vcc33_io>;
213 lcdc-supply = <&vcc33_lcd>;
214 sdcard-supply = <&vccio_sd>;
215 wifi-supply = <&vcc18_wl>;
220 cpu0-supply = <&vdd_cpu>;
224 logic-supply = <&vdd_logic>;
225 rockchip,odt-disable-freq = <333000000>;
226 rockchip,dll-disable-freq = <333000000>;
227 rockchip,sr-enable-freq = <333000000>;
228 rockchip,pd-enable-freq = <666000000>;
229 rockchip,auto-self-refresh-cnt = <0>;
230 rockchip,auto-power-down-cnt = <64>;
231 rockchip,ddr-speed-bin = <21>;
232 rockchip,trcd = <10>;
241 rockchip,num-channels = <2>;
242 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
243 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
244 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
245 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
247 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
248 0xa60 0x40 0x10 0x0>;
249 rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
250 rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_deassert_reset>;
279 card-external-vcc-supply = <&wifi_regulator>;
280 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>,
281 <&cru SCLK_SDIO0_SAMPLE>, <&rk808 RK808_CLKOUT1>;
282 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample", "card_ext_clock";
283 keep-power-in-suspend;
286 pinctrl-names = "default";
287 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
289 vmmc-supply = <&vcc33_sys>;
290 vqmmc-supply = <&vcc18_wl>;
301 card-detect-delay = <200>;
302 cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
305 vmmc-supply = <&vcc33_sd>;
306 vqmmc-supply = <&vccio_sd>;
313 spi_flash: spiflash@0 {
315 compatible = "spidev", "spi-flash";
316 spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */
324 clock-frequency = <400000>;
325 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
326 i2c-scl-rising-time-ns = <100>; /* 45ns measured */
329 compatible = "rockchip,rk808";
330 clock-output-names = "xin32k", "wifibt_32kin";
331 interrupt-parent = <&gpio0>;
332 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
333 pinctrl-names = "default";
334 pinctrl-0 = <&pmic_int_l>;
336 rockchip,system-power-controller;
340 vcc1-supply = <&vcc33_sys>;
341 vcc2-supply = <&vcc33_sys>;
342 vcc3-supply = <&vcc33_sys>;
343 vcc4-supply = <&vcc33_sys>;
344 vcc6-supply = <&vcc_5v>;
345 vcc7-supply = <&vcc33_sys>;
346 vcc8-supply = <&vcc33_sys>;
347 vcc9-supply = <&vcc_5v>;
348 vcc10-supply = <&vcc33_sys>;
349 vcc11-supply = <&vcc_5v>;
350 vcc12-supply = <&vcc_18>;
352 vddio-supply = <&vcc33_io>;
358 regulator-min-microvolt = <750000>;
359 regulator-max-microvolt = <1450000>;
360 regulator-name = "vdd_arm";
361 regulator-ramp-delay = <6001>;
362 regulator-suspend-mem-disabled;
368 regulator-min-microvolt = <800000>;
369 regulator-max-microvolt = <1250000>;
370 regulator-name = "vdd_gpu";
371 regulator-ramp-delay = <6001>;
372 regulator-suspend-mem-disabled;
375 vcc135_ddr: DCDC_REG3 {
378 regulator-name = "vcc135_ddr";
379 regulator-suspend-mem-enabled;
383 * vcc_18 has several aliases. (vcc18_flashio and
384 * vcc18_wl). We'll add those aliases here just to
385 * make it easier to follow the schematic. The signals
386 * are actually hooked together and only separated for
387 * power measurement purposes).
389 vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
392 regulator-min-microvolt = <1800000>;
393 regulator-max-microvolt = <1800000>;
394 regulator-name = "vcc_18";
395 regulator-suspend-mem-microvolt = <1800000>;
399 * Note that both vcc33_io and vcc33_pmuio are always
400 * powered together. To simplify the logic in the dts
401 * we just refer to vcc33_io every time something is
402 * powered from vcc33_pmuio. In fact, on later boards
403 * (such as danger) they're the same net.
408 regulator-min-microvolt = <3300000>;
409 regulator-max-microvolt = <3300000>;
410 regulator-name = "vcc33_io";
411 regulator-suspend-mem-microvolt = <3300000>;
417 regulator-min-microvolt = <1000000>;
418 regulator-max-microvolt = <1000000>;
419 regulator-name = "vdd_10";
420 regulator-suspend-mem-microvolt = <1000000>;
424 regulator-min-microvolt = <1800000>;
425 regulator-max-microvolt = <3300000>;
426 regulator-name = "vccio_sd";
427 regulator-suspend-mem-disabled;
431 regulator-min-microvolt = <3300000>;
432 regulator-max-microvolt = <3300000>;
433 regulator-name = "vcc33_sd";
434 regulator-suspend-mem-disabled;
437 vcc18_codec: LDO_REG6 {
440 regulator-min-microvolt = <1800000>;
441 regulator-max-microvolt = <1800000>;
442 regulator-name = "vcc18_codec";
443 regulator-suspend-mem-disabled;
446 vdd10_lcd_pwren_h: LDO_REG7 {
449 regulator-min-microvolt = <2500000>;
450 regulator-max-microvolt = <2500000>;
451 regulator-name = "vdd10_lcd_pwren_h";
452 regulator-suspend-mem-disabled;
455 vcc33_lcd: SWITCH_REG1 {
458 regulator-name = "vcc33_lcd";
459 regulator-suspend-mem-disabled;
468 clock-frequency = <400000>;
469 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
470 i2c-scl-rising-time-ns = <100>; /* 40ns measured */
473 compatible = "infineon,slb9645tt";
475 powered-while-suspended;
482 /* 100kHz since 4.7k resistors don't rise fast enough */
483 clock-frequency = <100000>;
484 i2c-scl-falling-time-ns = <50>; /* 10ns measured */
485 i2c-scl-rising-time-ns = <800>; /* 600ns measured */
487 max98090: max98090@10 {
488 compatible = "maxim,max98090";
490 interrupt-parent = <&gpio6>;
491 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
492 pinctrl-names = "default";
493 pinctrl-0 = <&int_codec>;
500 clock-frequency = <400000>;
501 i2c-scl-falling-time-ns = <50>;
502 i2c-scl-rising-time-ns = <300>;
508 clock-frequency = <400000>;
509 i2c-scl-falling-time-ns = <50>; /* 11ns measured */
510 i2c-scl-rising-time-ns = <300>; /* 225ns measured */
512 headsetcodec: ts3a227e@3b {
513 compatible = "ti,ts3a227e";
515 interrupt-parent = <&gpio0>;
516 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
517 pinctrl-names = "default";
518 pinctrl-0 = <&ts3a227e_int_l>;
519 ti,micbias = <7>; /* MICBIAS = 2.8V */
526 clock-frequency = <100000>;
527 i2c-scl-falling-time-ns = <300>;
528 i2c-scl-rising-time-ns = <1000>;
533 clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
534 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
552 /* Pins don't include flow control by default; add that in */
553 pinctrl-names = "default";
554 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
555 /* We need to go faster than 24MHz, so adjust clock parents / rates */
556 assigned-clocks = <&cru SCLK_UART0>;
557 assigned-clock-rates = <48000000>;
588 rockchip,panel = <&panel>;
604 tsadc-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
605 tsadc-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
611 pinctrl-names = "default", "sleep";
613 /* Common for sleep and wake, but no owners */
622 /* Common for sleep and wake, but no owners */
631 /* Add this for sdmmc pins to SD card */
632 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
633 drive-strength = <8>;
636 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
638 drive-strength = <8>;
641 pcfg_output_high: pcfg-output-high {
645 pcfg_output_low: pcfg-output-low {
651 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
656 pwr_key_h: pwr-key-h {
657 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>;
663 rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>;
665 int_codec: int-codec {
666 rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_up>;
669 rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>;
674 /* Make sure eMMC is not in reset */
675 emmc_deassert_reset: emmc-deassert-reset {
676 rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_up>;
680 * We run eMMC at max speed; bump up drive strength.
681 * We also have external pulls, so disable the internal ones.
684 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
688 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
691 emmc_bus8: emmc-bus8 {
692 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
693 <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
694 <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
695 <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
696 <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
697 <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
698 <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
699 <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
704 ts3a227e_int_l: ts3a227e-int-l {
705 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
710 pmic_int_l: pmic-int-l {
711 rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
716 ap_warm_reset_h: ap-warm-reset-h {
717 rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
722 wifi_enable_h: wifienable-h {
723 rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
726 /* NOTE: mislabelled on schematic; should be bt_enable_h */
727 bt_enable_l: bt-enable-l {
728 rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
732 * We run sdio0 at max speed; bump up drive strength.
733 * We also have external pulls, so disable the internal ones.
735 sdio0_bus4: sdio0-bus4 {
736 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
737 <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
738 <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
739 <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
742 sdio0_cmd: sdio0-cmd {
743 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
746 sdio0_clk: sdio0-clk {
747 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
751 * These pins are only present on very new veyron boards; on
752 * older boards bt_dev_wake is simply always high. Note that
753 * gpio4_26 is a NC on old veyron boards, so it doesn't hurt
754 * to map this pin everywhere
756 bt_dev_wake_sleep: bt-dev-wake-sleep {
757 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_low>;
760 bt_dev_wake_awake: bt-dev-wake-awake {
761 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_high>;
767 * We run sdmmc at max speed; bump up drive strength.
768 * We also have external pulls, so disable the internal ones.
770 sdmmc_bus4: sdmmc-bus4 {
771 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
772 <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
773 <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
774 <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
777 sdmmc_clk: sdmmc-clk {
778 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
781 sdmmc_cmd: sdmmc-cmd {
782 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
786 * Builtin CD line is hooked to ground to prevent JTAG at boot
787 * (and also to get the voltage rail correct). Make we
788 * configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
789 * think there's a card inserted
791 sdmmc_cd_disabled: sdmmc-cd-disabled {
792 rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>;
795 /* This is where we actually hook up CD */
796 sdmmc_cd_gpio: sdmmc-cd-gpio {
797 rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>;
802 tpm_int_h: tpm-int-h {
803 rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
809 rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
820 needs-reset-on-resume;
830 assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
831 assigned-clock-parents = <&cru SCLK_OTGPHY0>;