2 * SPDX-License-Identifier: GPL-2.0+
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3288-cru.h>
10 #include <dt-bindings/power-domain/rk3288.h>
11 #include <dt-bindings/thermal/thermal.h>
12 #include "skeleton.dtsi"
15 compatible = "rockchip,rk3288";
17 interrupt-parent = <&gic>;
55 enable-method = "rockchip,rk3066-smp";
56 rockchip,pmu = <&pmu>;
60 compatible = "arm,cortex-a12";
78 #cooling-cells = <2>; /* min followed by max */
79 clock-latency = <40000>;
80 clocks = <&cru ARMCLK>;
81 resets = <&cru SRST_CORE0>;
85 compatible = "arm,cortex-a12";
87 resets = <&cru SRST_CORE1>;
91 compatible = "arm,cortex-a12";
93 resets = <&cru SRST_CORE2>;
97 compatible = "arm,cortex-a12";
99 resets = <&cru SRST_CORE3>;
104 compatible = "arm,amba-bus";
105 #address-cells = <1>;
109 dmac_peri: dma-controller@ff250000 {
110 compatible = "arm,pl330", "arm,primecell";
112 reg = <0xff250000 0x4000>;
113 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
114 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&cru ACLK_DMAC2>;
117 clock-names = "apb_pclk";
120 dmac_bus_ns: dma-controller@ff600000 {
121 compatible = "arm,pl330", "arm,primecell";
123 reg = <0xff600000 0x4000>;
124 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
127 clocks = <&cru ACLK_DMAC1>;
128 clock-names = "apb_pclk";
132 dmac_bus_s: dma-controller@ffb20000 {
133 compatible = "arm,pl330", "arm,primecell";
135 reg = <0xffb20000 0x4000>;
136 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&cru ACLK_DMAC1>;
140 clock-names = "apb_pclk";
145 compatible = "fixed-clock";
146 clock-frequency = <24000000>;
147 clock-output-names = "xin24m";
152 arm,use-physical-timer;
153 compatible = "arm,armv7-timer";
154 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
155 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
156 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
157 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
158 clock-frequency = <24000000>;
163 compatible = "rockchip,display-subsystem";
164 ports = <&vopl_out>, <&vopb_out>;
167 sdmmc: dwmmc@ff0c0000 {
168 compatible = "rockchip,rk3288-dw-mshc";
169 clock-freq-min-max = <400000 150000000>;
170 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
171 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
172 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
173 fifo-depth = <0x100>;
174 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
175 reg = <0xff0c0000 0x4000>;
179 sdio0: dwmmc@ff0d0000 {
180 compatible = "rockchip,rk3288-dw-mshc";
181 clock-freq-min-max = <400000 150000000>;
182 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
183 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
184 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
185 fifo-depth = <0x100>;
186 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
187 reg = <0xff0d0000 0x4000>;
191 sdio1: dwmmc@ff0e0000 {
192 compatible = "rockchip,rk3288-dw-mshc";
193 clock-freq-min-max = <400000 150000000>;
194 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
195 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
196 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
197 fifo-depth = <0x100>;
198 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
199 reg = <0xff0e0000 0x4000>;
203 emmc: dwmmc@ff0f0000 {
204 compatible = "rockchip,rk3288-dw-mshc";
205 clock-freq-min-max = <400000 150000000>;
206 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
207 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
208 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
209 fifo-depth = <0x100>;
210 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
211 reg = <0xff0f0000 0x4000>;
215 saradc: saradc@ff100000 {
216 compatible = "rockchip,saradc";
217 reg = <0xff100000 0x100>;
218 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
219 #io-channel-cells = <1>;
220 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
221 clock-names = "saradc", "apb_pclk";
226 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
227 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
228 clock-names = "spiclk", "apb_pclk";
229 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
230 dma-names = "tx", "rx";
231 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
234 reg = <0xff110000 0x1000>;
235 #address-cells = <1>;
241 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
242 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
243 clock-names = "spiclk", "apb_pclk";
244 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
245 dma-names = "tx", "rx";
246 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
249 reg = <0xff120000 0x1000>;
250 #address-cells = <1>;
256 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
257 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
258 clock-names = "spiclk", "apb_pclk";
259 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
260 dma-names = "tx", "rx";
261 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
264 reg = <0xff130000 0x1000>;
265 #address-cells = <1>;
271 compatible = "rockchip,rk3288-i2c";
272 reg = <0xff140000 0x1000>;
273 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
274 #address-cells = <1>;
277 clocks = <&cru PCLK_I2C1>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&i2c1_xfer>;
284 compatible = "rockchip,rk3288-i2c";
285 reg = <0xff150000 0x1000>;
286 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
287 #address-cells = <1>;
290 clocks = <&cru PCLK_I2C3>;
291 pinctrl-names = "default";
292 pinctrl-0 = <&i2c3_xfer>;
297 compatible = "rockchip,rk3288-i2c";
298 reg = <0xff160000 0x1000>;
299 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
300 #address-cells = <1>;
303 clocks = <&cru PCLK_I2C4>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&i2c4_xfer>;
310 compatible = "rockchip,rk3288-i2c";
311 reg = <0xff170000 0x1000>;
312 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
313 #address-cells = <1>;
316 clocks = <&cru PCLK_I2C5>;
317 pinctrl-names = "default";
318 pinctrl-0 = <&i2c5_xfer>;
321 uart0: serial@ff180000 {
322 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
323 reg = <0xff180000 0x100>;
324 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
328 clock-names = "baudclk", "apb_pclk";
329 pinctrl-names = "default";
330 pinctrl-0 = <&uart0_xfer>;
334 uart1: serial@ff190000 {
335 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
336 reg = <0xff190000 0x100>;
337 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
341 clock-names = "baudclk", "apb_pclk";
342 pinctrl-names = "default";
343 pinctrl-0 = <&uart1_xfer>;
347 uart2: serial@ff690000 {
348 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
349 reg = <0xff690000 0x100>;
350 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
354 clock-names = "baudclk", "apb_pclk";
355 pinctrl-names = "default";
356 pinctrl-0 = <&uart2_xfer>;
359 uart3: serial@ff1b0000 {
360 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
361 reg = <0xff1b0000 0x100>;
362 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
366 clock-names = "baudclk", "apb_pclk";
367 pinctrl-names = "default";
368 pinctrl-0 = <&uart3_xfer>;
372 uart4: serial@ff1c0000 {
373 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
374 reg = <0xff1c0000 0x100>;
375 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
379 clock-names = "baudclk", "apb_pclk";
380 pinctrl-names = "default";
381 pinctrl-0 = <&uart4_xfer>;
384 thermal: thermal-zones {
385 #include "rk3288-thermal.dtsi"
388 tsadc: tsadc@ff280000 {
389 compatible = "rockchip,rk3288-tsadc";
390 reg = <0xff280000 0x100>;
391 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
393 clock-names = "tsadc", "apb_pclk";
394 resets = <&cru SRST_TSADC>;
395 reset-names = "tsadc-apb";
396 pinctrl-names = "otp_out";
397 pinctrl-0 = <&otp_out>;
398 #thermal-sensor-cells = <1>;
399 hw-shut-temp = <125000>;
403 gmac: ethernet@ff290000 {
404 compatible = "rockchip,rk3288-gmac";
405 reg = <0xff290000 0x10000>;
406 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
407 interrupt-names = "macirq";
408 rockchip,grf = <&grf>;
409 clocks = <&cru SCLK_MAC>,
410 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
411 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
412 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
413 clock-names = "stmmaceth",
414 "mac_clk_rx", "mac_clk_tx",
415 "clk_mac_ref", "clk_mac_refout",
416 "aclk_mac", "pclk_mac";
419 usb_host0_ehci: usb@ff500000 {
420 compatible = "generic-ehci";
421 reg = <0xff500000 0x100>;
422 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&cru HCLK_USBHOST0>;
424 clock-names = "usbhost";
430 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
432 usb_host1: usb@ff540000 {
433 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
435 reg = <0xff540000 0x40000>;
436 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&cru HCLK_USBHOST1>;
440 phy-names = "usb2-phy";
444 usb_otg: usb@ff580000 {
445 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
447 reg = <0xff580000 0x40000>;
448 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&cru HCLK_OTG0>;
452 phy-names = "usb2-phy";
456 usb_hsic: usb@ff5c0000 {
457 compatible = "generic-ehci";
458 reg = <0xff5c0000 0x100>;
459 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&cru HCLK_HSIC>;
461 clock-names = "usbhost";
467 compatible = "rockchip,rk3288-dmc", "syscon";
468 rockchip,cru = <&cru>;
469 rockchip,grf = <&grf>;
470 rockchip,pmu = <&pmu>;
471 rockchip,sgrf = <&sgrf>;
472 rockchip,noc = <&noc>;
473 reg = <0xff610000 0x3fc
477 rockchip,sram = <&ddr_sram>;
478 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
479 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
481 clock-names = "pclk_ddrupctl0", "pclk_publ0",
482 "pclk_ddrupctl1", "pclk_publ1",
487 compatible = "rockchip,rk3288-i2c";
488 reg = <0xff650000 0x1000>;
489 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
490 #address-cells = <1>;
493 clocks = <&cru PCLK_I2C0>;
494 pinctrl-names = "default";
495 pinctrl-0 = <&i2c0_xfer>;
500 compatible = "rockchip,rk3288-i2c";
501 reg = <0xff660000 0x1000>;
502 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
503 #address-cells = <1>;
506 clocks = <&cru PCLK_I2C2>;
507 pinctrl-names = "default";
508 pinctrl-0 = <&i2c2_xfer>;
513 compatible = "rockchip,rk3288-pwm";
514 reg = <0xff680000 0x10>;
516 pinctrl-names = "default";
517 pinctrl-0 = <&pwm0_pin>;
518 clocks = <&cru PCLK_PWM>;
520 rockchip,grf = <&grf>;
525 compatible = "rockchip,rk3288-pwm";
526 reg = <0xff680010 0x10>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&pwm1_pin>;
530 clocks = <&cru PCLK_PWM>;
532 rockchip,grf = <&grf>;
537 compatible = "rockchip,rk3288-pwm";
538 reg = <0xff680020 0x10>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&pwm2_pin>;
542 clocks = <&cru PCLK_PWM>;
544 rockchip,grf = <&grf>;
549 compatible = "rockchip,rk3288-pwm";
550 reg = <0xff680030 0x10>;
552 pinctrl-names = "default";
553 pinctrl-0 = <&pwm3_pin>;
554 clocks = <&cru PCLK_PWM>;
556 rockchip,grf = <&grf>;
560 bus_intmem@ff700000 {
561 compatible = "mmio-sram";
562 reg = <0xff700000 0x18000>;
563 #address-cells = <1>;
565 ranges = <0 0xff700000 0x18000>;
567 compatible = "rockchip,rk3066-smp-sram";
570 ddr_sram: ddr-sram@1000 {
571 compatible = "rockchip,rk3288-ddr-sram";
572 reg = <0x1000 0x4000>;
577 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
578 reg = <0xff720000 0x1000>;
581 pmu: power-management@ff730000 {
583 compatible = "rockchip,rk3288-pmu", "syscon";
584 reg = <0xff730000 0x100>;
587 sgrf: syscon@ff740000 {
589 compatible = "rockchip,rk3288-sgrf", "syscon";
590 reg = <0xff740000 0x1000>;
593 cru: clock-controller@ff760000 {
594 compatible = "rockchip,rk3288-cru";
595 reg = <0xff760000 0x1000>;
596 rockchip,grf = <&grf>;
600 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
601 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
602 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
603 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
604 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
606 assigned-clock-rates = <0>, <0>,
607 <594000000>, <400000000>,
608 <500000000>, <300000000>,
609 <150000000>, <75000000>,
610 <300000000>, <150000000>,
612 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
615 grf: syscon@ff770000 {
617 compatible = "rockchip,rk3288-grf", "syscon";
618 reg = <0xff770000 0x1000>;
621 wdt: watchdog@ff800000 {
622 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
623 reg = <0xff800000 0x100>;
624 clocks = <&cru PCLK_WDT>;
625 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
630 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
631 reg = <0xff890000 0x10000>;
632 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
633 #address-cells = <1>;
635 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
636 dma-names = "tx", "rx";
637 clock-names = "i2s_hclk", "i2s_clk";
638 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
639 pinctrl-names = "default";
640 pinctrl-0 = <&i2s0_bus>;
645 compatible = "rockchip,rk3288-vop";
646 reg = <0xff930000 0x19c>;
647 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
649 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
650 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
651 reset-names = "axi", "ahb", "dclk";
652 iommus = <&vopb_mmu>;
653 power-domains = <&power RK3288_PD_VIO>;
656 #address-cells = <1>;
658 vopb_out_edp: endpoint@0 {
660 remote-endpoint = <&edp_in_vopb>;
662 vopb_out_hdmi: endpoint@1 {
664 remote-endpoint = <&hdmi_in_vopb>;
669 vopb_mmu: iommu@ff930300 {
670 compatible = "rockchip,iommu";
671 reg = <0xff930300 0x100>;
672 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
673 interrupt-names = "vopb_mmu";
674 power-domains = <&power RK3288_PD_VIO>;
680 compatible = "rockchip,rk3288-vop";
681 reg = <0xff940000 0x19c>;
682 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
684 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
685 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
686 reset-names = "axi", "ahb", "dclk";
687 iommus = <&vopl_mmu>;
688 power-domains = <&power RK3288_PD_VIO>;
691 #address-cells = <1>;
693 vopl_out_edp: endpoint@0 {
695 remote-endpoint = <&edp_in_vopl>;
697 vopl_out_hdmi: endpoint@1 {
699 remote-endpoint = <&hdmi_in_vopl>;
705 vopl_mmu: iommu@ff940300 {
706 compatible = "rockchip,iommu";
707 reg = <0xff940300 0x100>;
708 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
709 interrupt-names = "vopl_mmu";
710 power-domains = <&power RK3288_PD_VIO>;
716 compatible = "rockchip,rk3288-edp";
717 reg = <0xff970000 0x4000>;
718 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
719 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
720 rockchip,grf = <&grf>;
721 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
724 power-domains = <&power RK3288_PD_VIO>;
728 #address-cells = <1>;
730 edp_in_vopb: endpoint@0 {
732 remote-endpoint = <&vopb_out_edp>;
734 edp_in_vopl: endpoint@1 {
736 remote-endpoint = <&vopl_out_edp>;
742 hdmi: hdmi@ff980000 {
743 compatible = "rockchip,rk3288-dw-hdmi";
744 reg = <0xff980000 0x20000>;
746 ddc-i2c-bus = <&i2c5>;
747 rockchip,grf = <&grf>;
748 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
749 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
750 clock-names = "iahb", "isfr";
754 #address-cells = <1>;
756 hdmi_in_vopb: endpoint@0 {
758 remote-endpoint = <&vopb_out_hdmi>;
760 hdmi_in_vopl: endpoint@1 {
762 remote-endpoint = <&vopl_out_hdmi>;
768 hdmi_audio: hdmi_audio {
769 compatible = "rockchip,rk3288-hdmi-audio";
770 i2s-controller = <&i2s>;
774 vpu: video-codec@ff9a0000 {
775 compatible = "rockchip,rk3288-vpu";
776 reg = <0xff9a0000 0x800>;
777 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
779 interrupt-names = "vepu", "vdpu";
780 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
781 clock-names = "aclk_vcodec", "hclk_vcodec";
782 power-domains = <&power RK3288_PD_VIDEO>;
786 vpu_mmu: iommu@ff9a0800 {
787 compatible = "rockchip,iommu";
788 reg = <0xff9a0800 0x100>;
789 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
790 interrupt-names = "vpu_mmu";
791 power-domains = <&power RK3288_PD_VIDEO>;
796 compatible = "arm,malit764",
800 reg = <0xffa30000 0x10000>;
801 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
802 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
803 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
804 interrupt-names = "JOB", "MMU", "GPU";
805 clocks = <&cru ACLK_GPU>;
806 clock-names = "aclk_gpu";
813 /* 500000 1200000 - See crosbug.com/p/33857 */
816 power-domains = <&power RK3288_PD_GPU>;
820 noc: syscon@ffac0000 {
822 compatible = "rockchip,rk3288-noc", "syscon";
823 reg = <0xffac0000 0x2000>;
826 efuse: efuse@ffb40000 {
827 compatible = "rockchip,rk3288-efuse";
828 reg = <0xffb40000 0x10000>;
832 gic: interrupt-controller@ffc01000 {
833 compatible = "arm,gic-400";
834 interrupt-controller;
835 #interrupt-cells = <3>;
836 #address-cells = <0>;
838 reg = <0xffc01000 0x1000>,
842 interrupts = <GIC_PPI 9 0xf04>;
846 compatible = "rockchip,rk3288-cpuidle";
850 compatible = "rockchip,rk3288-usb-phy";
851 rockchip,grf = <&grf>;
852 #address-cells = <1>;
859 clocks = <&cru SCLK_OTGPHY0>;
860 clock-names = "phyclk";
866 clocks = <&cru SCLK_OTGPHY1>;
867 clock-names = "phyclk";
873 clocks = <&cru SCLK_OTGPHY2>;
874 clock-names = "phyclk";
879 compatible = "rockchip,rk3288-pinctrl";
880 rockchip,grf = <&grf>;
881 rockchip,pmu = <&pmu>;
882 #address-cells = <1>;
886 gpio0: gpio0@ff750000 {
887 compatible = "rockchip,gpio-bank";
888 reg = <0xff750000 0x100>;
889 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
890 clocks = <&cru PCLK_GPIO0>;
895 interrupt-controller;
896 #interrupt-cells = <2>;
899 gpio1: gpio1@ff780000 {
900 compatible = "rockchip,gpio-bank";
901 reg = <0xff780000 0x100>;
902 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
903 clocks = <&cru PCLK_GPIO1>;
908 interrupt-controller;
909 #interrupt-cells = <2>;
912 gpio2: gpio2@ff790000 {
913 compatible = "rockchip,gpio-bank";
914 reg = <0xff790000 0x100>;
915 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
916 clocks = <&cru PCLK_GPIO2>;
921 interrupt-controller;
922 #interrupt-cells = <2>;
925 gpio3: gpio3@ff7a0000 {
926 compatible = "rockchip,gpio-bank";
927 reg = <0xff7a0000 0x100>;
928 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&cru PCLK_GPIO3>;
934 interrupt-controller;
935 #interrupt-cells = <2>;
938 gpio4: gpio4@ff7b0000 {
939 compatible = "rockchip,gpio-bank";
940 reg = <0xff7b0000 0x100>;
941 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
942 clocks = <&cru PCLK_GPIO4>;
947 interrupt-controller;
948 #interrupt-cells = <2>;
951 gpio5: gpio5@ff7c0000 {
952 compatible = "rockchip,gpio-bank";
953 reg = <0xff7c0000 0x100>;
954 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&cru PCLK_GPIO5>;
960 interrupt-controller;
961 #interrupt-cells = <2>;
964 gpio6: gpio6@ff7d0000 {
965 compatible = "rockchip,gpio-bank";
966 reg = <0xff7d0000 0x100>;
967 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
968 clocks = <&cru PCLK_GPIO6>;
973 interrupt-controller;
974 #interrupt-cells = <2>;
977 gpio7: gpio7@ff7e0000 {
978 compatible = "rockchip,gpio-bank";
979 reg = <0xff7e0000 0x100>;
980 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&cru PCLK_GPIO7>;
986 interrupt-controller;
987 #interrupt-cells = <2>;
990 gpio8: gpio8@ff7f0000 {
991 compatible = "rockchip,gpio-bank";
992 reg = <0xff7f0000 0x100>;
993 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&cru PCLK_GPIO8>;
999 interrupt-controller;
1000 #interrupt-cells = <2>;
1003 pcfg_pull_up: pcfg-pull-up {
1007 pcfg_pull_down: pcfg-pull-down {
1011 pcfg_pull_none: pcfg-pull-none {
1015 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1017 drive-strength = <12>;
1021 global_pwroff: global-pwroff {
1022 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1025 ddrio_pwroff: ddrio-pwroff {
1026 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1029 ddr0_retention: ddr0-retention {
1030 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1033 ddr1_retention: ddr1-retention {
1034 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1039 i2c0_xfer: i2c0-xfer {
1040 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1041 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1046 i2c1_xfer: i2c1-xfer {
1047 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1048 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1053 i2c2_xfer: i2c2-xfer {
1054 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1055 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1060 i2c3_xfer: i2c3-xfer {
1061 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1062 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1067 i2c4_xfer: i2c4-xfer {
1068 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1069 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1074 i2c5_xfer: i2c5-xfer {
1075 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1076 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1081 i2s0_bus: i2s0-bus {
1082 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1083 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1084 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1085 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1086 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1087 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1092 sdmmc_clk: sdmmc-clk {
1093 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1096 sdmmc_cmd: sdmmc-cmd {
1097 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1100 sdmmc_cd: sdmcc-cd {
1101 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1104 sdmmc_bus1: sdmmc-bus1 {
1105 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1108 sdmmc_bus4: sdmmc-bus4 {
1109 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1110 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1111 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1112 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1117 sdio0_bus1: sdio0-bus1 {
1118 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1121 sdio0_bus4: sdio0-bus4 {
1122 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1123 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1124 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1125 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1128 sdio0_cmd: sdio0-cmd {
1129 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1132 sdio0_clk: sdio0-clk {
1133 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1136 sdio0_cd: sdio0-cd {
1137 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1140 sdio0_wp: sdio0-wp {
1141 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1144 sdio0_pwr: sdio0-pwr {
1145 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1148 sdio0_bkpwr: sdio0-bkpwr {
1149 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1152 sdio0_int: sdio0-int {
1153 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1158 sdio1_bus1: sdio1-bus1 {
1159 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
1162 sdio1_bus4: sdio1-bus4 {
1163 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
1164 <3 25 RK_FUNC_4 &pcfg_pull_up>,
1165 <3 26 RK_FUNC_4 &pcfg_pull_up>,
1166 <3 27 RK_FUNC_4 &pcfg_pull_up>;
1169 sdio1_cd: sdio1-cd {
1170 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
1173 sdio1_wp: sdio1-wp {
1174 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
1177 sdio1_bkpwr: sdio1-bkpwr {
1178 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
1181 sdio1_int: sdio1-int {
1182 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
1185 sdio1_cmd: sdio1-cmd {
1186 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
1189 sdio1_clk: sdio1-clk {
1190 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
1193 sdio1_pwr: sdio1-pwr {
1194 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
1199 emmc_clk: emmc-clk {
1200 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1203 emmc_cmd: emmc-cmd {
1204 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1207 emmc_pwr: emmc-pwr {
1208 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1211 emmc_bus1: emmc-bus1 {
1212 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1215 emmc_bus4: emmc-bus4 {
1216 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1217 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1218 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1219 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1222 emmc_bus8: emmc-bus8 {
1223 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1224 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1225 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1226 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1227 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1228 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1229 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1230 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1235 spi0_clk: spi0-clk {
1236 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1238 spi0_cs0: spi0-cs0 {
1239 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1242 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1245 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1247 spi0_cs1: spi0-cs1 {
1248 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1252 spi1_clk: spi1-clk {
1253 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1255 spi1_cs0: spi1-cs0 {
1256 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1259 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1262 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1267 spi2_cs1: spi2-cs1 {
1268 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1270 spi2_clk: spi2-clk {
1271 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1273 spi2_cs0: spi2-cs0 {
1274 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1277 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1280 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1285 uart0_xfer: uart0-xfer {
1286 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1287 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1290 uart0_cts: uart0-cts {
1291 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1294 uart0_rts: uart0-rts {
1295 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1300 uart1_xfer: uart1-xfer {
1301 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1302 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1305 uart1_cts: uart1-cts {
1306 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1309 uart1_rts: uart1-rts {
1310 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1315 uart2_xfer: uart2-xfer {
1316 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1317 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1319 /* no rts / cts for uart2 */
1323 uart3_xfer: uart3-xfer {
1324 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1325 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1328 uart3_cts: uart3-cts {
1329 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1332 uart3_rts: uart3-rts {
1333 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1338 uart4_xfer: uart4-xfer {
1339 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1340 <5 13 3 &pcfg_pull_none>;
1343 uart4_cts: uart4-cts {
1344 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1347 uart4_rts: uart4-rts {
1348 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1354 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1359 pwm0_pin: pwm0-pin {
1360 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1365 pwm1_pin: pwm1-pin {
1366 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1371 pwm2_pin: pwm2-pin {
1372 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
1377 pwm3_pin: pwm3-pin {
1378 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
1383 rgmii_pins: rgmii-pins {
1384 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1385 <3 31 3 &pcfg_pull_none>,
1386 <3 26 3 &pcfg_pull_none>,
1387 <3 27 3 &pcfg_pull_none>,
1388 <3 28 3 &pcfg_pull_none_12ma>,
1389 <3 29 3 &pcfg_pull_none_12ma>,
1390 <3 24 3 &pcfg_pull_none_12ma>,
1391 <3 25 3 &pcfg_pull_none_12ma>,
1392 <4 0 3 &pcfg_pull_none>,
1393 <4 5 3 &pcfg_pull_none>,
1394 <4 6 3 &pcfg_pull_none>,
1395 <4 9 3 &pcfg_pull_none_12ma>,
1396 <4 4 3 &pcfg_pull_none_12ma>,
1397 <4 1 3 &pcfg_pull_none>,
1398 <4 3 3 &pcfg_pull_none>;
1401 rmii_pins: rmii-pins {
1402 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1403 <3 31 3 &pcfg_pull_none>,
1404 <3 28 3 &pcfg_pull_none>,
1405 <3 29 3 &pcfg_pull_none>,
1406 <4 0 3 &pcfg_pull_none>,
1407 <4 5 3 &pcfg_pull_none>,
1408 <4 4 3 &pcfg_pull_none>,
1409 <4 1 3 &pcfg_pull_none>,
1410 <4 2 3 &pcfg_pull_none>,
1411 <4 3 3 &pcfg_pull_none>;
1416 power: power-controller {
1417 compatible = "rockchip,rk3288-power-controller";
1418 #power-domain-cells = <1>;
1419 rockchip,pmu = <&pmu>;
1420 #address-cells = <1>;
1424 reg = <RK3288_PD_GPU>;
1425 clocks = <&cru ACLK_GPU>;
1429 reg = <RK3288_PD_HEVC>;
1430 clocks = <&cru ACLK_HEVC>,
1431 <&cru SCLK_HEVC_CABAC>,
1432 <&cru SCLK_HEVC_CORE>,
1437 reg = <RK3288_PD_VIO>;
1438 clocks = <&cru ACLK_IEP>,
1452 <&cru PCLK_EDP_CTRL>,
1453 <&cru PCLK_HDMI_CTRL>,
1454 <&cru PCLK_LVDS_PHY>,
1455 <&cru PCLK_MIPI_CSI>,
1456 <&cru PCLK_MIPI_DSI0>,
1457 <&cru PCLK_MIPI_DSI1>,
1458 <&cru SCLK_EDP_24M>,
1460 <&cru SCLK_HDMI_CEC>,
1461 <&cru SCLK_HDMI_HDCP>,
1462 <&cru SCLK_ISP_JPE>,
1468 reg = <RK3288_PD_VIDEO>;
1469 clocks = <&cru ACLK_VCODEC>,