git.sur5r.net Git - u-boot/blob - arch/arm/dts/rk3288.dtsi

   1 /*
   2  * SPDX-License-Identifier:     GPL-2.0+
   3  */
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/interrupt-controller/irq.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/pinctrl/rockchip.h>
   9 #include <dt-bindings/clock/rk3288-cru.h>
  10 #include <dt-bindings/power-domain/rk3288.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12 #include <dt-bindings/video/rk3288.h>
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         compatible = "rockchip,rk3288";
  17
  18         interrupt-parent = <&gic>;
  19         aliases {
  20                 gpio0 = &gpio0;
  21                 gpio1 = &gpio1;
  22                 gpio2 = &gpio2;
  23                 gpio3 = &gpio3;
  24                 gpio4 = &gpio4;
  25                 gpio5 = &gpio5;
  26                 gpio6 = &gpio6;
  27                 gpio7 = &gpio7;
  28                 gpio8 = &gpio8;
  29                 i2c0 = &i2c0;
  30                 i2c1 = &i2c1;
  31                 i2c2 = &i2c2;
  32                 i2c3 = &i2c3;
  33                 i2c4 = &i2c4;
  34                 i2c5 = &i2c5;
  35                 mmc0 = &emmc;
  36                 mmc1 = &sdmmc;
  37                 mmc2 = &sdio0;
  38                 mmc3 = &sdio1;
  39                 mshc0 = &emmc;
  40                 mshc1 = &sdmmc;
  41                 mshc2 = &sdio0;
  42                 mshc3 = &sdio1;
  43                 serial0 = &uart0;
  44                 serial1 = &uart1;
  45                 serial2 = &uart2;
  46                 serial3 = &uart3;
  47                 serial4 = &uart4;
  48                 spi0 = &spi0;
  49                 spi1 = &spi1;
  50                 spi2 = &spi2;
  51         };
  52
  53         cpus {
  54                 #address-cells = <1>;
  55                 #size-cells = <0>;
  56                 enable-method = "rockchip,rk3066-smp";
  57                 rockchip,pmu = <&pmu>;
  58
  59                 cpu0: cpu@500 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a12";
  62                         reg = <0x500>;
  63                         operating-points = <
  64                                 /* KHz    uV */
  65                                 1800000 1400000
  66                                 1704000 1350000
  67                                 1608000 1300000
  68                                 1512000 1250000
  69                                 1416000 1200000
  70                                 1200000 1100000
  71                                 1008000 1050000
  72                                  816000 1000000
  73                                  696000  950000
  74                                  600000  900000
  75                                  408000  900000
  76                                  216000  900000
  77                                  126000  900000
  78                         >;
  79                         #cooling-cells = <2>; /* min followed by max */
  80                         clock-latency = <40000>;
  81                         clocks = <&cru ARMCLK>;
  82                         resets = <&cru SRST_CORE0>;
  83                 };
  84                 cpu@501 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a12";
  87                         reg = <0x501>;
  88                         resets = <&cru SRST_CORE1>;
  89                 };
  90                 cpu@502 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a12";
  93                         reg = <0x502>;
  94                         resets = <&cru SRST_CORE2>;
  95                 };
  96                 cpu@503 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a12";
  99                         reg = <0x503>;
 100                         resets = <&cru SRST_CORE3>;
 101                 };
 102         };
 103
 104         amba {
 105                 compatible = "arm,amba-bus";
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 ranges;
 109
 110                 dmac_peri: dma-controller@ff250000 {
 111                         compatible = "arm,pl330", "arm,primecell";
 112                         broken-no-flushp;
 113                         reg = <0xff250000 0x4000>;
 114                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 115                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 116                         #dma-cells = <1>;
 117                         clocks = <&cru ACLK_DMAC2>;
 118                         clock-names = "apb_pclk";
 119                 };
 120
 121                 dmac_bus_ns: dma-controller@ff600000 {
 122                         compatible = "arm,pl330", "arm,primecell";
 123                         broken-no-flushp;
 124                         reg = <0xff600000 0x4000>;
 125                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 126                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 127                         #dma-cells = <1>;
 128                         clocks = <&cru ACLK_DMAC1>;
 129                         clock-names = "apb_pclk";
 130                         status = "disabled";
 131                 };
 132
 133                 dmac_bus_s: dma-controller@ffb20000 {
 134                         compatible = "arm,pl330", "arm,primecell";
 135                         broken-no-flushp;
 136                         reg = <0xffb20000 0x4000>;
 137                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 138                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 139                         #dma-cells = <1>;
 140                         clocks = <&cru ACLK_DMAC1>;
 141                         clock-names = "apb_pclk";
 142                 };
 143         };
 144
 145         xin24m: oscillator {
 146                 compatible = "fixed-clock";
 147                 clock-frequency = <24000000>;
 148                 clock-output-names = "xin24m";
 149                 #clock-cells = <0>;
 150         };
 151
 152         timer {
 153                 arm,use-physical-timer;
 154                 compatible = "arm,armv7-timer";
 155                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 156                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 157                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 158                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 159                 clock-frequency = <24000000>;
 160                 always-on;
 161         };
 162
 163         display-subsystem {
 164                 compatible = "rockchip,display-subsystem";
 165                 ports = <&vopl_out>, <&vopb_out>;
 166         };
 167
 168         sdmmc: dwmmc@ff0c0000 {
 169                 compatible = "rockchip,rk3288-dw-mshc";
 170                 clock-freq-min-max = <400000 150000000>;
 171                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 172                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 173                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 174                 fifo-depth = <0x100>;
 175                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 176                 reg = <0xff0c0000 0x4000>;
 177                 status = "disabled";
 178         };
 179
 180         sdio0: dwmmc@ff0d0000 {
 181                 compatible = "rockchip,rk3288-dw-mshc";
 182                 clock-freq-min-max = <400000 150000000>;
 183                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 184                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 185                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 186                 fifo-depth = <0x100>;
 187                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 188                 reg = <0xff0d0000 0x4000>;
 189                 status = "disabled";
 190         };
 191
 192         sdio1: dwmmc@ff0e0000 {
 193                 compatible = "rockchip,rk3288-dw-mshc";
 194                 clock-freq-min-max = <400000 150000000>;
 195                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 196                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 197                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 198                 fifo-depth = <0x100>;
 199                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 200                 reg = <0xff0e0000 0x4000>;
 201                 status = "disabled";
 202         };
 203
 204         emmc: dwmmc@ff0f0000 {
 205                 compatible = "rockchip,rk3288-dw-mshc";
 206                 clock-freq-min-max = <400000 150000000>;
 207                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 208                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 209                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 210                 fifo-depth = <0x100>;
 211                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 212                 reg = <0xff0f0000 0x4000>;
 213                 status = "disabled";
 214         };
 215
 216         saradc: saradc@ff100000 {
 217                 compatible = "rockchip,saradc";
 218                 reg = <0xff100000 0x100>;
 219                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 220                 #io-channel-cells = <1>;
 221                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 222                 clock-names = "saradc", "apb_pclk";
 223                 status = "disabled";
 224         };
 225
 226         spi0: spi@ff110000 {
 227                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 228                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 229                 clock-names = "spiclk", "apb_pclk";
 230                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 231                 dma-names = "tx", "rx";
 232                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 233                 pinctrl-names = "default";
 234                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 235                 reg = <0xff110000 0x1000>;
 236                 #address-cells = <1>;
 237                 #size-cells = <0>;
 238                 status = "disabled";
 239         };
 240
 241         spi1: spi@ff120000 {
 242                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 243                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 244                 clock-names = "spiclk", "apb_pclk";
 245                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 246                 dma-names = "tx", "rx";
 247                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 248                 pinctrl-names = "default";
 249                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 250                 reg = <0xff120000 0x1000>;
 251                 #address-cells = <1>;
 252                 #size-cells = <0>;
 253                 status = "disabled";
 254         };
 255
 256         spi2: spi@ff130000 {
 257                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 258                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 259                 clock-names = "spiclk", "apb_pclk";
 260                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 261                 dma-names = "tx", "rx";
 262                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 263                 pinctrl-names = "default";
 264                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 265                 reg = <0xff130000 0x1000>;
 266                 #address-cells = <1>;
 267                 #size-cells = <0>;
 268                 status = "disabled";
 269         };
 270
 271         i2c1: i2c@ff140000 {
 272                 compatible = "rockchip,rk3288-i2c";
 273                 reg = <0xff140000 0x1000>;
 274                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 275                 #address-cells = <1>;
 276                 #size-cells = <0>;
 277                 clock-names = "i2c";
 278                 clocks = <&cru PCLK_I2C1>;
 279                 pinctrl-names = "default";
 280                 pinctrl-0 = <&i2c1_xfer>;
 281                 status = "disabled";
 282         };
 283
 284         i2c3: i2c@ff150000 {
 285                 compatible = "rockchip,rk3288-i2c";
 286                 reg = <0xff150000 0x1000>;
 287                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 288                 #address-cells = <1>;
 289                 #size-cells = <0>;
 290                 clock-names = "i2c";
 291                 clocks = <&cru PCLK_I2C3>;
 292                 pinctrl-names = "default";
 293                 pinctrl-0 = <&i2c3_xfer>;
 294                 status = "disabled";
 295         };
 296
 297         i2c4: i2c@ff160000 {
 298                 compatible = "rockchip,rk3288-i2c";
 299                 reg = <0xff160000 0x1000>;
 300                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 301                 #address-cells = <1>;
 302                 #size-cells = <0>;
 303                 clock-names = "i2c";
 304                 clocks = <&cru PCLK_I2C4>;
 305                 pinctrl-names = "default";
 306                 pinctrl-0 = <&i2c4_xfer>;
 307                 status = "disabled";
 308         };
 309
 310         i2c5: i2c@ff170000 {
 311                 compatible = "rockchip,rk3288-i2c";
 312                 reg = <0xff170000 0x1000>;
 313                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316                 clock-names = "i2c";
 317                 clocks = <&cru PCLK_I2C5>;
 318                 pinctrl-names = "default";
 319                 pinctrl-0 = <&i2c5_xfer>;
 320                 status = "disabled";
 321         };
 322         uart0: serial@ff180000 {
 323                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 324                 reg = <0xff180000 0x100>;
 325                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 326                 reg-shift = <2>;
 327                 reg-io-width = <4>;
 328                 clock-frequency = <24000000>;
 329                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 330                 clock-names = "baudclk", "apb_pclk";
 331                 pinctrl-names = "default";
 332                 pinctrl-0 = <&uart0_xfer>;
 333                 status = "disabled";
 334         };
 335
 336         uart1: serial@ff190000 {
 337                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 338                 reg = <0xff190000 0x100>;
 339                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 340                 reg-shift = <2>;
 341                 reg-io-width = <4>;
 342                 clock-frequency = <24000000>;
 343                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 344                 clock-names = "baudclk", "apb_pclk";
 345                 pinctrl-names = "default";
 346                 pinctrl-0 = <&uart1_xfer>;
 347                 status = "disabled";
 348         };
 349
 350         uart2: serial@ff690000 {
 351                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 352                 reg = <0xff690000 0x100>;
 353                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 354                 reg-shift = <2>;
 355                 reg-io-width = <4>;
 356                 clock-frequency = <24000000>;
 357                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 358                 clock-names = "baudclk", "apb_pclk";
 359                 pinctrl-names = "default";
 360                 pinctrl-0 = <&uart2_xfer>;
 361                 status = "disabled";
 362         };
 363         uart3: serial@ff1b0000 {
 364                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 365                 reg = <0xff1b0000 0x100>;
 366                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 367                 reg-shift = <2>;
 368                 reg-io-width = <4>;
 369                 clock-frequency = <24000000>;
 370                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 371                 clock-names = "baudclk", "apb_pclk";
 372                 pinctrl-names = "default";
 373                 pinctrl-0 = <&uart3_xfer>;
 374                 status = "disabled";
 375         };
 376
 377         uart4: serial@ff1c0000 {
 378                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 379                 reg = <0xff1c0000 0x100>;
 380                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 381                 reg-shift = <2>;
 382                 reg-io-width = <4>;
 383                 clock-frequency = <24000000>;
 384                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 385                 clock-names = "baudclk", "apb_pclk";
 386                 pinctrl-names = "default";
 387                 pinctrl-0 = <&uart4_xfer>;
 388                 status = "disabled";
 389         };
 390         thermal: thermal-zones {
 391                 #include "rk3288-thermal.dtsi"
 392         };
 393
 394         tsadc: tsadc@ff280000 {
 395                 compatible = "rockchip,rk3288-tsadc";
 396                 reg = <0xff280000 0x100>;
 397                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 398                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 399                 clock-names = "tsadc", "apb_pclk";
 400                 resets = <&cru SRST_TSADC>;
 401                 reset-names = "tsadc-apb";
 402                 pinctrl-names = "otp_out";
 403                 pinctrl-0 = <&otp_out>;
 404                 #thermal-sensor-cells = <1>;
 405                 hw-shut-temp = <125000>;
 406                 status = "disabled";
 407         };
 408
 409         gmac: ethernet@ff290000 {
 410                 compatible = "rockchip,rk3288-gmac";
 411                 reg = <0xff290000 0x10000>;
 412                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 413                 interrupt-names = "macirq";
 414                 rockchip,grf = <&grf>;
 415                 clocks = <&cru SCLK_MAC>,
 416                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 417                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 418                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 419                 clock-names = "stmmaceth",
 420                         "mac_clk_rx", "mac_clk_tx",
 421                         "clk_mac_ref", "clk_mac_refout",
 422                         "aclk_mac", "pclk_mac";
 423         };
 424
 425         usb_host0_ehci: usb@ff500000 {
 426                 compatible = "generic-ehci";
 427                 reg = <0xff500000 0x100>;
 428                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 429                 clocks = <&cru HCLK_USBHOST0>;
 430                 clock-names = "usbhost";
 431                 phys = <&usbphy1>;
 432                 phy-names = "usb";
 433                 status = "disabled";
 434         };
 435
 436         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 437
 438         usb_host1: usb@ff540000 {
 439                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 440                                 "snps,dwc2";
 441                 reg = <0xff540000 0x40000>;
 442                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 443                 clocks = <&cru HCLK_USBHOST1>;
 444                 clock-names = "otg";
 445                 phys = <&usbphy2>;
 446                 phy-names = "usb2-phy";
 447                 status = "disabled";
 448         };
 449
 450         usb_otg: usb@ff580000 {
 451                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 452                                 "snps,dwc2";
 453                 reg = <0xff580000 0x40000>;
 454                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 455                 clocks = <&cru HCLK_OTG0>;
 456                 clock-names = "otg";
 457                 dr_mode = "otg";
 458                 phys = <&usbphy0>;
 459                 phy-names = "usb2-phy";
 460                 status = "disabled";
 461         };
 462
 463         usb_hsic: usb@ff5c0000 {
 464                 compatible = "generic-ehci";
 465                 reg = <0xff5c0000 0x100>;
 466                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 467                 clocks = <&cru HCLK_HSIC>;
 468                 clock-names = "usbhost";
 469                 status = "disabled";
 470         };
 471
 472         dmc: dmc@ff610000 {
 473                 u-boot,dm-pre-reloc;
 474                 compatible = "rockchip,rk3288-dmc", "syscon";
 475                 rockchip,cru = <&cru>;
 476                 rockchip,grf = <&grf>;
 477                 rockchip,pmu = <&pmu>;
 478                 rockchip,sgrf = <&sgrf>;
 479                 rockchip,noc = <&noc>;
 480                 reg = <0xff610000 0x3fc
 481                        0xff620000 0x294
 482                        0xff630000 0x3fc
 483                        0xff640000 0x294>;
 484                 rockchip,sram = <&ddr_sram>;
 485                 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
 486                          <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
 487                          <&cru ARMCLK>;
 488                 clock-names = "pclk_ddrupctl0", "pclk_publ0",
 489                               "pclk_ddrupctl1", "pclk_publ1",
 490                               "arm_clk";
 491         };
 492
 493         i2c0: i2c@ff650000 {
 494                 compatible = "rockchip,rk3288-i2c";
 495                 reg = <0xff650000 0x1000>;
 496                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 497                 #address-cells = <1>;
 498                 #size-cells = <0>;
 499                 clock-names = "i2c";
 500                 clocks = <&cru PCLK_I2C0>;
 501                 pinctrl-names = "default";
 502                 pinctrl-0 = <&i2c0_xfer>;
 503                 status = "disabled";
 504         };
 505
 506         i2c2: i2c@ff660000 {
 507                 compatible = "rockchip,rk3288-i2c";
 508                 reg = <0xff660000 0x1000>;
 509                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 510                 #address-cells = <1>;
 511                 #size-cells = <0>;
 512                 clock-names = "i2c";
 513                 clocks = <&cru PCLK_I2C2>;
 514                 pinctrl-names = "default";
 515                 pinctrl-0 = <&i2c2_xfer>;
 516                 status = "disabled";
 517         };
 518
 519         pwm0: pwm@ff680000 {
 520                 compatible = "rockchip,rk3288-pwm";
 521                 reg = <0xff680000 0x10>;
 522                 #pwm-cells = <3>;
 523                 pinctrl-names = "default";
 524                 pinctrl-0 = <&pwm0_pin>;
 525                 clocks = <&cru PCLK_PWM>;
 526                 clock-names = "pwm";
 527                 rockchip,grf = <&grf>;
 528                 status = "disabled";
 529         };
 530
 531         pwm1: pwm@ff680010 {
 532                 compatible = "rockchip,rk3288-pwm";
 533                 reg = <0xff680010 0x10>;
 534                 #pwm-cells = <3>;
 535                 pinctrl-names = "default";
 536                 pinctrl-0 = <&pwm1_pin>;
 537                 clocks = <&cru PCLK_PWM>;
 538                 clock-names = "pwm";
 539                 rockchip,grf = <&grf>;
 540                 status = "disabled";
 541         };
 542
 543         pwm2: pwm@ff680020 {
 544                 compatible = "rockchip,rk3288-pwm";
 545                 reg = <0xff680020 0x10>;
 546                 #pwm-cells = <3>;
 547                 pinctrl-names = "default";
 548                 pinctrl-0 = <&pwm2_pin>;
 549                 clocks = <&cru PCLK_PWM>;
 550                 clock-names = "pwm";
 551                 rockchip,grf = <&grf>;
 552                 status = "disabled";
 553         };
 554
 555         pwm3: pwm@ff680030 {
 556                 compatible = "rockchip,rk3288-pwm";
 557                 reg = <0xff680030 0x10>;
 558                 #pwm-cells = <2>;
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&pwm3_pin>;
 561                 clocks = <&cru PCLK_PWM>;
 562                 clock-names = "pwm";
 563                 rockchip,grf = <&grf>;
 564                 status = "disabled";
 565         };
 566
 567         bus_intmem@ff700000 {
 568                 compatible = "mmio-sram";
 569                 reg = <0xff700000 0x18000>;
 570                 #address-cells = <1>;
 571                 #size-cells = <1>;
 572                 ranges = <0 0xff700000 0x18000>;
 573                 smp-sram@0 {
 574                         compatible = "rockchip,rk3066-smp-sram";
 575                         reg = <0x00 0x10>;
 576                 };
 577                 ddr_sram: ddr-sram@1000 {
 578                         compatible = "rockchip,rk3288-ddr-sram";
 579                         reg = <0x1000 0x4000>;
 580                 };
 581         };
 582
 583         sram@ff720000 {
 584                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 585                 reg = <0xff720000 0x1000>;
 586         };
 587
 588         pmu: power-management@ff730000 {
 589                 u-boot,dm-pre-reloc;
 590                 compatible = "rockchip,rk3288-pmu", "syscon";
 591                 reg = <0xff730000 0x100>;
 592         };
 593
 594         sgrf: syscon@ff740000 {
 595                 u-boot,dm-pre-reloc;
 596                 compatible = "rockchip,rk3288-sgrf", "syscon";
 597                 reg = <0xff740000 0x1000>;
 598         };
 599
 600         cru: clock-controller@ff760000 {
 601                 compatible = "rockchip,rk3288-cru";
 602                 reg = <0xff760000 0x1000>;
 603                 rockchip,grf = <&grf>;
 604                 u-boot,dm-pre-reloc;
 605                 #clock-cells = <1>;
 606                 #reset-cells = <1>;
 607                 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
 608                                   <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 609                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 610                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 611                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 612                                   <&cru PCLK_PERI>;
 613                 assigned-clock-rates = <0>, <0>,
 614                                        <594000000>, <400000000>,
 615                                        <500000000>, <300000000>,
 616                                        <150000000>, <75000000>,
 617                                        <300000000>, <150000000>,
 618                                        <75000000>;
 619                 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
 620         };
 621
 622         grf: syscon@ff770000 {
 623                 u-boot,dm-pre-reloc;
 624                 compatible = "rockchip,rk3288-grf", "syscon";
 625                 reg = <0xff770000 0x1000>;
 626         };
 627
 628         wdt: watchdog@ff800000 {
 629                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 630                 reg = <0xff800000 0x100>;
 631                 clocks = <&cru PCLK_WDT>;
 632                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 633                 status = "disabled";
 634         };
 635
 636         spdif: sound@ff88b0000 {
 637                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 638                 reg = <0xff8b0000 0x10000>;
 639                 #sound-dai-cells = <0>;
 640                 clock-names = "hclk", "mclk";
 641                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 642                 dmas = <&dmac_bus_s 3>;
 643                 dma-names = "tx";
 644                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 645                 pinctrl-names = "default";
 646                 pinctrl-0 = <&spdif_tx>;
 647                 rockchip,grf = <&grf>;
 648                 status = "disabled";
 649         };
 650
 651         i2s: i2s@ff890000 {
 652                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 653                 reg = <0xff890000 0x10000>;
 654                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 655                 #address-cells = <1>;
 656                 #size-cells = <0>;
 657                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 658                 dma-names = "tx", "rx";
 659                 clock-names = "i2s_hclk", "i2s_clk";
 660                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 661                 pinctrl-names = "default";
 662                 pinctrl-0 = <&i2s0_bus>;
 663                 status = "disabled";
 664         };
 665
 666         vopb: vop@ff930000 {
 667                 compatible = "rockchip,rk3288-vop";
 668                 reg = <0xff930000 0x19c>;
 669                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 670                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 671                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 672                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 673                 reset-names = "axi", "ahb", "dclk";
 674                 iommus = <&vopb_mmu>;
 675                 power-domains = <&power RK3288_PD_VIO>;
 676                 status = "disabled";
 677                 vopb_out: port {
 678                         #address-cells = <1>;
 679                         #size-cells = <0>;
 680                         vopb_out_edp: endpoint@0 {
 681                                 reg = <0>;
 682                                 remote-endpoint = <&edp_in_vopb>;
 683                         };
 684                         vopb_out_hdmi: endpoint@1 {
 685                                 reg = <1>;
 686                                 remote-endpoint = <&hdmi_in_vopb>;
 687                         };
 688                         vopb_out_lvds: endpoint@2 {
 689                                 reg = <2>;
 690                                 remote-endpoint = <&lvds_in_vopb>;
 691                         };
 692                 };
 693         };
 694
 695         vopb_mmu: iommu@ff930300 {
 696                 compatible = "rockchip,iommu";
 697                 reg = <0xff930300 0x100>;
 698                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 699                 interrupt-names = "vopb_mmu";
 700                 power-domains = <&power RK3288_PD_VIO>;
 701                 #iommu-cells = <0>;
 702                 status = "disabled";
 703         };
 704
 705         vopl: vop@ff940000 {
 706                 compatible = "rockchip,rk3288-vop";
 707                 reg = <0xff940000 0x19c>;
 708                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 709                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 710                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 711                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 712                 reset-names = "axi", "ahb", "dclk";
 713                 iommus = <&vopl_mmu>;
 714                 power-domains = <&power RK3288_PD_VIO>;
 715                 status = "disabled";
 716                 u-boot,dm-pre-reloc;
 717                 vopl_out: port {
 718                         #address-cells = <1>;
 719                         #size-cells = <0>;
 720                         vopl_out_edp: endpoint@0 {
 721                                 reg = <0>;
 722                                 remote-endpoint = <&edp_in_vopl>;
 723                         };
 724                         vopl_out_hdmi: endpoint@1 {
 725                                 reg = <1>;
 726                                 remote-endpoint = <&hdmi_in_vopl>;
 727                         };
 728                         vopl_out_lvds: endpoint@2 {
 729                                 reg = <2>;
 730                                 remote-endpoint = <&lvds_in_vopl>;
 731                         };
 732                 };
 733         };
 734
 735         vopl_mmu: iommu@ff940300 {
 736                 compatible = "rockchip,iommu";
 737                 reg = <0xff940300 0x100>;
 738                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 739                 interrupt-names = "vopl_mmu";
 740                 power-domains = <&power RK3288_PD_VIO>;
 741                 #iommu-cells = <0>;
 742                 status = "disabled";
 743         };
 744
 745         edp: edp@ff970000 {
 746                 compatible = "rockchip,rk3288-edp";
 747                 reg = <0xff970000 0x4000>;
 748                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 749                 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
 750                 rockchip,grf = <&grf>;
 751                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 752                 resets = <&cru 111>;
 753                 reset-names = "edp";
 754                 power-domains = <&power RK3288_PD_VIO>;
 755                 status = "disabled";
 756                 ports {
 757                         edp_in: port {
 758                                 #address-cells = <1>;
 759                                 #size-cells = <0>;
 760                                 edp_in_vopb: endpoint@0 {
 761                                         reg = <0>;
 762                                         remote-endpoint = <&vopb_out_edp>;
 763                                 };
 764                                 edp_in_vopl: endpoint@1 {
 765                                         reg = <1>;
 766                                         remote-endpoint = <&vopl_out_edp>;
 767                                 };
 768                         };
 769                 };
 770         };
 771
 772         hdmi: hdmi@ff980000 {
 773                 compatible = "rockchip,rk3288-dw-hdmi";
 774                 reg = <0xff980000 0x20000>;
 775                 reg-io-width = <4>;
 776                 ddc-i2c-bus = <&i2c5>;
 777                 rockchip,grf = <&grf>;
 778                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 779                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
 780                 clock-names = "iahb", "isfr";
 781                 status = "disabled";
 782                 ports {
 783                         hdmi_in: port {
 784                                 #address-cells = <1>;
 785                                 #size-cells = <0>;
 786                                 hdmi_in_vopb: endpoint@0 {
 787                                         reg = <0>;
 788                                         remote-endpoint = <&vopb_out_hdmi>;
 789                                 };
 790                                 hdmi_in_vopl: endpoint@1 {
 791                                         reg = <1>;
 792                                         remote-endpoint = <&vopl_out_hdmi>;
 793                                 };
 794                         };
 795                 };
 796         };
 797
 798         lvds: lvds@ff96c000 {
 799                 compatible = "rockchip,rk3288-lvds";
 800                 reg = <0xff96c000 0x4000>;
 801                 clocks = <&cru PCLK_LVDS_PHY>;
 802                 clock-names = "pclk_lvds";
 803                 pinctrl-names = "default";
 804                 pinctrl-0 = <&lcdc0_ctl>;
 805                 rockchip,grf = <&grf>;
 806                 status = "disabled";
 807                 ports {
 808                         #address-cells = <1>;
 809                         #size-cells = <0>;
 810                         lvds_in: port@0 {
 811                                 reg = <0>;
 812                                 #address-cells = <1>;
 813                                 #size-cells = <0>;
 814                                 lvds_in_vopb: endpoint@0 {
 815                                         reg = <0>;
 816                                         remote-endpoint = <&vopb_out_lvds>;
 817                                 };
 818                                 lvds_in_vopl: endpoint@1 {
 819                                         reg = <1>;
 820                                         remote-endpoint = <&vopl_out_lvds>;
 821                                 };
 822                         };
 823                 };
 824         };
 825
 826         hdmi_audio: hdmi_audio {
 827                 compatible = "rockchip,rk3288-hdmi-audio";
 828                 i2s-controller = <&i2s>;
 829                 status = "disable";
 830         };
 831
 832         vpu: video-codec@ff9a0000 {
 833                 compatible = "rockchip,rk3288-vpu";
 834                 reg = <0xff9a0000 0x800>;
 835                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 836                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 837                 interrupt-names = "vepu", "vdpu";
 838                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 839                 clock-names = "aclk_vcodec", "hclk_vcodec";
 840                 power-domains = <&power RK3288_PD_VIDEO>;
 841                 iommus = <&vpu_mmu>;
 842         };
 843
 844         vpu_mmu: iommu@ff9a0800 {
 845                 compatible = "rockchip,iommu";
 846                 reg = <0xff9a0800 0x100>;
 847                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 848                 interrupt-names = "vpu_mmu";
 849                 power-domains = <&power RK3288_PD_VIDEO>;
 850                 #iommu-cells = <0>;
 851         };
 852
 853         gpu: gpu@ffa30000 {
 854                 compatible = "arm,malit764",
 855                              "arm,malit76x",
 856                              "arm,malit7xx",
 857                              "arm,mali-midgard";
 858                 reg = <0xffa30000 0x10000>;
 859                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 860                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 861                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 862                 interrupt-names = "JOB", "MMU", "GPU";
 863                 clocks = <&cru ACLK_GPU>;
 864                 clock-names = "aclk_gpu";
 865                 operating-points = <
 866                         /* KHz uV */
 867                         100000 950000
 868                         200000 950000
 869                         300000 1000000
 870                         400000 1100000
 871                         /* 500000 1200000 - See crosbug.com/p/33857 */
 872                         600000 1250000
 873                 >;
 874                 power-domains = <&power RK3288_PD_GPU>;
 875                 status = "disabled";
 876         };
 877
 878         noc: syscon@ffac0000 {
 879                 u-boot,dm-pre-reloc;
 880                 compatible = "rockchip,rk3288-noc", "syscon";
 881                 reg = <0xffac0000 0x2000>;
 882         };
 883
 884         efuse: efuse@ffb40000 {
 885                 compatible = "rockchip,rk3288-efuse";
 886                 reg = <0xffb40000 0x10000>;
 887                 status = "disabled";
 888         };
 889
 890         gic: interrupt-controller@ffc01000 {
 891                 compatible = "arm,gic-400";
 892                 interrupt-controller;
 893                 #interrupt-cells = <3>;
 894                 #address-cells = <0>;
 895
 896                 reg = <0xffc01000 0x1000>,
 897                       <0xffc02000 0x1000>,
 898                       <0xffc04000 0x2000>,
 899                       <0xffc06000 0x2000>;
 900                 interrupts = <GIC_PPI 9 0xf04>;
 901         };
 902
 903         cpuidle: cpuidle {
 904                 compatible = "rockchip,rk3288-cpuidle";
 905         };
 906
 907         usbphy: phy {
 908                 compatible = "rockchip,rk3288-usb-phy";
 909                 rockchip,grf = <&grf>;
 910                 #address-cells = <1>;
 911                 #size-cells = <0>;
 912                 status = "disabled";
 913
 914                 usbphy0: usb-phy0 {
 915                         #phy-cells = <0>;
 916                         reg = <0x320>;
 917                         clocks = <&cru SCLK_OTGPHY0>;
 918                         clock-names = "phyclk";
 919                 };
 920
 921                 usbphy1: usb-phy1 {
 922                         #phy-cells = <0>;
 923                         reg = <0x334>;
 924                         clocks = <&cru SCLK_OTGPHY1>;
 925                         clock-names = "phyclk";
 926                 };
 927
 928                 usbphy2: usb-phy2 {
 929                         #phy-cells = <0>;
 930                         reg = <0x348>;
 931                         clocks = <&cru SCLK_OTGPHY2>;
 932                         clock-names = "phyclk";
 933                 };
 934         };
 935
 936         pinctrl: pinctrl {
 937                 compatible = "rockchip,rk3288-pinctrl";
 938                 rockchip,grf = <&grf>;
 939                 rockchip,pmu = <&pmu>;
 940                 #address-cells = <1>;
 941                 #size-cells = <1>;
 942                 ranges;
 943
 944                 gpio0: gpio0@ff750000 {
 945                         compatible = "rockchip,gpio-bank";
 946                         reg =   <0xff750000 0x100>;
 947                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 948                         clocks = <&cru PCLK_GPIO0>;
 949
 950                         gpio-controller;
 951                         #gpio-cells = <2>;
 952
 953                         interrupt-controller;
 954                         #interrupt-cells = <2>;
 955                 };
 956
 957                 gpio1: gpio1@ff780000 {
 958                         compatible = "rockchip,gpio-bank";
 959                         reg = <0xff780000 0x100>;
 960                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 961                         clocks = <&cru PCLK_GPIO1>;
 962
 963                         gpio-controller;
 964                         #gpio-cells = <2>;
 965
 966                         interrupt-controller;
 967                         #interrupt-cells = <2>;
 968                 };
 969
 970                 gpio2: gpio2@ff790000 {
 971                         compatible = "rockchip,gpio-bank";
 972                         reg = <0xff790000 0x100>;
 973                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 974                         clocks = <&cru PCLK_GPIO2>;
 975
 976                         gpio-controller;
 977                         #gpio-cells = <2>;
 978
 979                         interrupt-controller;
 980                         #interrupt-cells = <2>;
 981                 };
 982
 983                 gpio3: gpio3@ff7a0000 {
 984                         compatible = "rockchip,gpio-bank";
 985                         reg = <0xff7a0000 0x100>;
 986                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 987                         clocks = <&cru PCLK_GPIO3>;
 988
 989                         gpio-controller;
 990                         #gpio-cells = <2>;
 991
 992                         interrupt-controller;
 993                         #interrupt-cells = <2>;
 994                 };
 995
 996                 gpio4: gpio4@ff7b0000 {
 997                         compatible = "rockchip,gpio-bank";
 998                         reg = <0xff7b0000 0x100>;
 999                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1000                         clocks = <&cru PCLK_GPIO4>;
1001
1002                         gpio-controller;
1003                         #gpio-cells = <2>;
1004
1005                         interrupt-controller;
1006                         #interrupt-cells = <2>;
1007                 };
1008
1009                 gpio5: gpio5@ff7c0000 {
1010                         compatible = "rockchip,gpio-bank";
1011                         reg = <0xff7c0000 0x100>;
1012                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1013                         clocks = <&cru PCLK_GPIO5>;
1014
1015                         gpio-controller;
1016                         #gpio-cells = <2>;
1017
1018                         interrupt-controller;
1019                         #interrupt-cells = <2>;
1020                 };
1021
1022                 gpio6: gpio6@ff7d0000 {
1023                         compatible = "rockchip,gpio-bank";
1024                         reg = <0xff7d0000 0x100>;
1025                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1026                         clocks = <&cru PCLK_GPIO6>;
1027
1028                         gpio-controller;
1029                         #gpio-cells = <2>;
1030
1031                         interrupt-controller;
1032                         #interrupt-cells = <2>;
1033                 };
1034
1035                 gpio7: gpio7@ff7e0000 {
1036                         compatible = "rockchip,gpio-bank";
1037                         reg = <0xff7e0000 0x100>;
1038                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1039                         clocks = <&cru PCLK_GPIO7>;
1040
1041                         gpio-controller;
1042                         #gpio-cells = <2>;
1043
1044                         interrupt-controller;
1045                         #interrupt-cells = <2>;
1046                 };
1047
1048                 gpio8: gpio8@ff7f0000 {
1049                         compatible = "rockchip,gpio-bank";
1050                         reg = <0xff7f0000 0x100>;
1051                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1052                         clocks = <&cru PCLK_GPIO8>;
1053
1054                         gpio-controller;
1055                         #gpio-cells = <2>;
1056
1057                         interrupt-controller;
1058                         #interrupt-cells = <2>;
1059                 };
1060
1061                 pcfg_pull_up: pcfg-pull-up {
1062                         bias-pull-up;
1063                 };
1064
1065                 pcfg_pull_down: pcfg-pull-down {
1066                         bias-pull-down;
1067                 };
1068
1069                 pcfg_pull_none: pcfg-pull-none {
1070                         bias-disable;
1071                 };
1072
1073                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1074                         bias-disable;
1075                         drive-strength = <12>;
1076                 };
1077
1078                 sleep {
1079                         global_pwroff: global-pwroff {
1080                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1081                         };
1082
1083                         ddrio_pwroff: ddrio-pwroff {
1084                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1085                         };
1086
1087                         ddr0_retention: ddr0-retention {
1088                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1089                         };
1090
1091                         ddr1_retention: ddr1-retention {
1092                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1093                         };
1094                 };
1095
1096                 i2c0 {
1097                         i2c0_xfer: i2c0-xfer {
1098                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1099                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1100                         };
1101                 };
1102
1103                 i2c1 {
1104                         i2c1_xfer: i2c1-xfer {
1105                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1106                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1107                         };
1108                 };
1109
1110                 i2c2 {
1111                         i2c2_xfer: i2c2-xfer {
1112                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1113                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1114                         };
1115                 };
1116
1117                 i2c3 {
1118                         i2c3_xfer: i2c3-xfer {
1119                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1120                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1121                         };
1122                 };
1123
1124                 i2c4 {
1125                         i2c4_xfer: i2c4-xfer {
1126                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1127                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1128                         };
1129                 };
1130
1131                 i2c5 {
1132                         i2c5_xfer: i2c5-xfer {
1133                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1134                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1135                         };
1136                 };
1137
1138                 i2s0 {
1139                         i2s0_bus: i2s0-bus {
1140                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1141                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1142                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1143                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1144                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1145                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1146                         };
1147                 };
1148
1149                 lcdc0 {
1150                         lcdc0_ctl: lcdc0-ctl {
1151                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1152                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1153                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1154                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1155                         };
1156                 };
1157
1158                 sdmmc {
1159                         sdmmc_clk: sdmmc-clk {
1160                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1161                         };
1162
1163                         sdmmc_cmd: sdmmc-cmd {
1164                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1165                         };
1166
1167                         sdmmc_cd: sdmcc-cd {
1168                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1169                         };
1170
1171                         sdmmc_bus1: sdmmc-bus1 {
1172                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1173                         };
1174
1175                         sdmmc_bus4: sdmmc-bus4 {
1176                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1177                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1178                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1179                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1180                         };
1181                 };
1182
1183                 sdio0 {
1184                         sdio0_bus1: sdio0-bus1 {
1185                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1186                         };
1187
1188                         sdio0_bus4: sdio0-bus4 {
1189                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1190                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1191                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1192                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1193                         };
1194
1195                         sdio0_cmd: sdio0-cmd {
1196                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1197                         };
1198
1199                         sdio0_clk: sdio0-clk {
1200                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1201                         };
1202
1203                         sdio0_cd: sdio0-cd {
1204                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1205                         };
1206
1207                         sdio0_wp: sdio0-wp {
1208                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1209                         };
1210
1211                         sdio0_pwr: sdio0-pwr {
1212                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1213                         };
1214
1215                         sdio0_bkpwr: sdio0-bkpwr {
1216                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1217                         };
1218
1219                         sdio0_int: sdio0-int {
1220                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1221                         };
1222                 };
1223
1224                 sdio1 {
1225                         sdio1_bus1: sdio1-bus1 {
1226                                 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
1227                         };
1228
1229                         sdio1_bus4: sdio1-bus4 {
1230                                 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
1231                                                 <3 25 RK_FUNC_4 &pcfg_pull_up>,
1232                                                 <3 26 RK_FUNC_4 &pcfg_pull_up>,
1233                                                 <3 27 RK_FUNC_4 &pcfg_pull_up>;
1234                         };
1235
1236                         sdio1_cd: sdio1-cd {
1237                                 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
1238                         };
1239
1240                         sdio1_wp: sdio1-wp {
1241                                 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
1242                         };
1243
1244                         sdio1_bkpwr: sdio1-bkpwr {
1245                                 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
1246                         };
1247
1248                         sdio1_int: sdio1-int {
1249                                 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
1250                         };
1251
1252                         sdio1_cmd: sdio1-cmd {
1253                                 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
1254                         };
1255
1256                         sdio1_clk: sdio1-clk {
1257                                 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
1258                         };
1259
1260                         sdio1_pwr: sdio1-pwr {
1261                                 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
1262                         };
1263                 };
1264
1265                 emmc {
1266                         emmc_clk: emmc-clk {
1267                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1268                         };
1269
1270                         emmc_cmd: emmc-cmd {
1271                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1272                         };
1273
1274                         emmc_pwr: emmc-pwr {
1275                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1276                         };
1277
1278                         emmc_bus1: emmc-bus1 {
1279                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1280                         };
1281
1282                         emmc_bus4: emmc-bus4 {
1283                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1284                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1285                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1286                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1287                         };
1288
1289                         emmc_bus8: emmc-bus8 {
1290                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1291                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1292                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1293                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1294                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1295                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1296                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1297                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1298                         };
1299                 };
1300
1301                 spi0 {
1302                         spi0_clk: spi0-clk {
1303                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1304                         };
1305                         spi0_cs0: spi0-cs0 {
1306                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1307                         };
1308                         spi0_tx: spi0-tx {
1309                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1310                         };
1311                         spi0_rx: spi0-rx {
1312                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1313                         };
1314                         spi0_cs1: spi0-cs1 {
1315                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1316                         };
1317                 };
1318                 spi1 {
1319                         spi1_clk: spi1-clk {
1320                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1321                         };
1322                         spi1_cs0: spi1-cs0 {
1323                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1324                         };
1325                         spi1_rx: spi1-rx {
1326                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1327                         };
1328                         spi1_tx: spi1-tx {
1329                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1330                         };
1331                 };
1332
1333                 spi2 {
1334                         spi2_cs1: spi2-cs1 {
1335                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1336                         };
1337                         spi2_clk: spi2-clk {
1338                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1339                         };
1340                         spi2_cs0: spi2-cs0 {
1341                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1342                         };
1343                         spi2_rx: spi2-rx {
1344                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1345                         };
1346                         spi2_tx: spi2-tx {
1347                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1348                         };
1349                 };
1350
1351                 uart0 {
1352                         uart0_xfer: uart0-xfer {
1353                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1354                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1355                         };
1356
1357                         uart0_cts: uart0-cts {
1358                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1359                         };
1360
1361                         uart0_rts: uart0-rts {
1362                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1363                         };
1364                 };
1365
1366                 uart1 {
1367                         uart1_xfer: uart1-xfer {
1368                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1369                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1370                         };
1371
1372                         uart1_cts: uart1-cts {
1373                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1374                         };
1375
1376                         uart1_rts: uart1-rts {
1377                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1378                         };
1379                 };
1380
1381                 uart2 {
1382                         uart2_xfer: uart2-xfer {
1383                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1384                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1385                         };
1386                         /* no rts / cts for uart2 */
1387                 };
1388
1389                 uart3 {
1390                         uart3_xfer: uart3-xfer {
1391                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1392                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1393                         };
1394
1395                         uart3_cts: uart3-cts {
1396                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1397                         };
1398
1399                         uart3_rts: uart3-rts {
1400                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1401                         };
1402                 };
1403
1404                 uart4 {
1405                         uart4_xfer: uart4-xfer {
1406                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1407                                                 <5 13 3 &pcfg_pull_none>;
1408                         };
1409
1410                         uart4_cts: uart4-cts {
1411                                 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1412                         };
1413
1414                         uart4_rts: uart4-rts {
1415                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1416                         };
1417                 };
1418
1419                 tsadc {
1420                         otp_out: otp-out {
1421                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1422                         };
1423                 };
1424
1425                 pwm0 {
1426                         pwm0_pin: pwm0-pin {
1427                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1428                         };
1429                 };
1430
1431                 pwm1 {
1432                         pwm1_pin: pwm1-pin {
1433                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1434                         };
1435                 };
1436
1437                 pwm2 {
1438                         pwm2_pin: pwm2-pin {
1439                                 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
1440                         };
1441                 };
1442
1443                 pwm3 {
1444                         pwm3_pin: pwm3-pin {
1445                                 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
1446                         };
1447                 };
1448
1449                 gmac {
1450                         rgmii_pins: rgmii-pins {
1451                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1452                                                 <3 31 3 &pcfg_pull_none>,
1453                                                 <3 26 3 &pcfg_pull_none>,
1454                                                 <3 27 3 &pcfg_pull_none>,
1455                                                 <3 28 3 &pcfg_pull_none_12ma>,
1456                                                 <3 29 3 &pcfg_pull_none_12ma>,
1457                                                 <3 24 3 &pcfg_pull_none_12ma>,
1458                                                 <3 25 3 &pcfg_pull_none_12ma>,
1459                                                 <4 0 3 &pcfg_pull_none>,
1460                                                 <4 5 3 &pcfg_pull_none>,
1461                                                 <4 6 3 &pcfg_pull_none>,
1462                                                 <4 9 3 &pcfg_pull_none_12ma>,
1463                                                 <4 4 3 &pcfg_pull_none_12ma>,
1464                                                 <4 1 3 &pcfg_pull_none>,
1465                                                 <4 3 3 &pcfg_pull_none>;
1466                         };
1467
1468                         rmii_pins: rmii-pins {
1469                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1470                                                 <3 31 3 &pcfg_pull_none>,
1471                                                 <3 28 3 &pcfg_pull_none>,
1472                                                 <3 29 3 &pcfg_pull_none>,
1473                                                 <4 0 3 &pcfg_pull_none>,
1474                                                 <4 5 3 &pcfg_pull_none>,
1475                                                 <4 4 3 &pcfg_pull_none>,
1476                                                 <4 1 3 &pcfg_pull_none>,
1477                                                 <4 2 3 &pcfg_pull_none>,
1478                                                 <4 3 3 &pcfg_pull_none>;
1479                         };
1480                 };
1481
1482                 spdif {
1483                         spdif_tx: spdif-tx {
1484                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1485                         };
1486                 };
1487         };
1488
1489         power: power-controller {
1490                 compatible = "rockchip,rk3288-power-controller";
1491                 #power-domain-cells = <1>;
1492                 rockchip,pmu = <&pmu>;
1493                 #address-cells = <1>;
1494                 #size-cells = <0>;
1495
1496                 pd_gpu {
1497                         reg = <RK3288_PD_GPU>;
1498                         clocks = <&cru ACLK_GPU>;
1499                 };
1500
1501                 pd_hevc {
1502                         reg = <RK3288_PD_HEVC>;
1503                         clocks = <&cru ACLK_HEVC>,
1504                                  <&cru SCLK_HEVC_CABAC>,
1505                                  <&cru SCLK_HEVC_CORE>,
1506                                  <&cru HCLK_HEVC>;
1507                 };
1508
1509                 pd_vio {
1510                         reg = <RK3288_PD_VIO>;
1511                         clocks = <&cru ACLK_IEP>,
1512                                  <&cru ACLK_ISP>,
1513                                  <&cru ACLK_RGA>,
1514                                  <&cru ACLK_VIP>,
1515                                  <&cru ACLK_VOP0>,
1516                                  <&cru ACLK_VOP1>,
1517                                  <&cru DCLK_VOP0>,
1518                                  <&cru DCLK_VOP1>,
1519                                  <&cru HCLK_IEP>,
1520                                  <&cru HCLK_ISP>,
1521                                  <&cru HCLK_RGA>,
1522                                  <&cru HCLK_VIP>,
1523                                  <&cru HCLK_VOP0>,
1524                                  <&cru HCLK_VOP1>,
1525                                  <&cru PCLK_EDP_CTRL>,
1526                                  <&cru PCLK_HDMI_CTRL>,
1527                                  <&cru PCLK_LVDS_PHY>,
1528                                  <&cru PCLK_MIPI_CSI>,
1529                                  <&cru PCLK_MIPI_DSI0>,
1530                                  <&cru PCLK_MIPI_DSI1>,
1531                                  <&cru SCLK_EDP_24M>,
1532                                  <&cru SCLK_EDP>,
1533                                  <&cru SCLK_HDMI_CEC>,
1534                                  <&cru SCLK_HDMI_HDCP>,
1535                                  <&cru SCLK_ISP_JPE>,
1536                                  <&cru SCLK_ISP>,
1537                                  <&cru SCLK_RGA>;
1538                 };
1539
1540                 pd_video {
1541                         reg = <RK3288_PD_VIDEO>;
1542                         clocks = <&cru ACLK_VCODEC>,
1543                                  <&cru HCLK_VCODEC>;
1544                 };
1545         };
1546 };