1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
13 compatible = "rockchip,rk3328";
15 interrupt-parent = <&gic>;
38 compatible = "arm,cortex-a53", "arm,armv8";
40 enable-method = "psci";
41 // clocks = <&cru ARMCLK>;
42 operating-points-v2 = <&cpu0_opp_table>;
46 compatible = "arm,cortex-a53", "arm,armv8";
48 enable-method = "psci";
52 compatible = "arm,cortex-a53", "arm,armv8";
54 enable-method = "psci";
58 compatible = "arm,cortex-a53", "arm,armv8";
60 enable-method = "psci";
64 cpu0_opp_table: opp_table0 {
65 compatible = "operating-points-v2";
69 opp-hz = /bits/ 64 <408000000>;
70 opp-microvolt = <950000>;
71 clock-latency-ns = <40000>;
75 opp-hz = /bits/ 64 <600000000>;
76 opp-microvolt = <950000>;
77 clock-latency-ns = <40000>;
80 opp-hz = /bits/ 64 <816000000>;
81 opp-microvolt = <1000000>;
82 clock-latency-ns = <40000>;
85 opp-hz = /bits/ 64 <1008000000>;
86 opp-microvolt = <1100000>;
87 clock-latency-ns = <40000>;
90 opp-hz = /bits/ 64 <1200000000>;
91 opp-microvolt = <1225000>;
92 clock-latency-ns = <40000>;
95 opp-hz = /bits/ 64 <1296000000>;
96 opp-microvolt = <1300000>;
97 clock-latency-ns = <40000>;
102 compatible = "arm,cortex-a53-pmu";
103 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
107 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
111 compatible = "arm,psci-1.0";
116 compatible = "arm,armv8-timer";
117 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
118 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
119 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
120 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
124 compatible = "fixed-clock";
126 clock-frequency = <24000000>;
127 clock-output-names = "xin24m";
131 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
132 reg = <0x0 0xff000000 0x0 0x1000>;
133 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
135 clock-names = "i2s_clk", "i2s_hclk";
136 dmas = <&dmac 11>, <&dmac 12>;
138 dma-names = "tx", "rx";
143 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
144 reg = <0x0 0xff010000 0x0 0x1000>;
145 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
147 clock-names = "i2s_clk", "i2s_hclk";
148 dmas = <&dmac 14>, <&dmac 15>;
150 dma-names = "tx", "rx";
155 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
156 reg = <0x0 0xff020000 0x0 0x1000>;
157 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
159 clock-names = "i2s_clk", "i2s_hclk";
160 dmas = <&dmac 0>, <&dmac 1>;
162 dma-names = "tx", "rx";
163 pinctrl-names = "default", "sleep";
164 pinctrl-0 = <&i2s2m0_mclk
170 pinctrl-1 = <&i2s2m0_sleep>;
174 spdif: spdif@ff030000 {
175 compatible = "rockchip,rk3328-spdif";
176 reg = <0x0 0xff030000 0x0 0x1000>;
177 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
179 clock-names = "mclk", "hclk";
183 pinctrl-names = "default";
184 pinctrl-0 = <&spdifm2_tx>;
188 grf: syscon@ff100000 {
190 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
191 reg = <0x0 0xff100000 0x0 0x1000>;
192 #address-cells = <1>;
195 io_domains: io-domains {
196 compatible = "rockchip,rk3328-io-voltage-domain";
201 uart0: serial@ff110000 {
202 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
203 reg = <0x0 0xff110000 0x0 0x100>;
204 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
206 clock-names = "baudclk", "apb_pclk";
209 dmas = <&dmac 2>, <&dmac 3>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
216 uart1: serial@ff120000 {
217 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
218 reg = <0x0 0xff120000 0x0 0x100>;
219 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
221 clock-names = "sclk_uart", "pclk_uart";
224 dmas = <&dmac 4>, <&dmac 5>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
231 uart2: serial@ff130000 {
232 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
233 reg = <0x0 0xff130000 0x0 0x100>;
234 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
236 clock-names = "baudclk", "apb_pclk";
237 clock-frequency = <24000000>;
240 dmas = <&dmac 6>, <&dmac 7>;
242 pinctrl-names = "default";
243 pinctrl-0 = <&uart2m1_xfer>;
247 pmu: power-management@ff140000 {
248 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
249 reg = <0x0 0xff140000 0x0 0x1000>;
253 compatible = "rockchip,rk3328-i2c";
254 reg = <0x0 0xff150000 0x0 0x1000>;
255 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
256 #address-cells = <1>;
258 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
259 clock-names = "i2c", "pclk";
260 pinctrl-names = "default";
261 pinctrl-0 = <&i2c0_xfer>;
266 compatible = "rockchip,rk3328-i2c";
267 reg = <0x0 0xff160000 0x0 0x1000>;
268 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
269 #address-cells = <1>;
271 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
272 clock-names = "i2c", "pclk";
273 pinctrl-names = "default";
274 pinctrl-0 = <&i2c1_xfer>;
279 compatible = "rockchip,rk3328-i2c";
280 reg = <0x0 0xff170000 0x0 0x1000>;
281 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
282 #address-cells = <1>;
284 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
285 clock-names = "i2c", "pclk";
286 pinctrl-names = "default";
287 pinctrl-0 = <&i2c2_xfer>;
292 compatible = "rockchip,rk3328-i2c";
293 reg = <0x0 0xff180000 0x0 0x1000>;
294 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
295 #address-cells = <1>;
297 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
298 clock-names = "i2c", "pclk";
299 pinctrl-names = "default";
300 pinctrl-0 = <&i2c3_xfer>;
305 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
306 reg = <0x0 0xff190000 0x0 0x1000>;
307 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
308 #address-cells = <1>;
310 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
311 clock-names = "spiclk", "apb_pclk";
312 dmas = <&dmac 8>, <&dmac 9>;
314 dma-names = "tx", "rx";
315 pinctrl-names = "default";
316 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
320 wdt: watchdog@ff1a0000 {
321 compatible = "snps,dw-wdt";
322 reg = <0x0 0xff1a0000 0x0 0x100>;
323 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
328 compatible = "simple-bus";
329 #address-cells = <2>;
333 dmac: dmac@ff1f0000 {
334 compatible = "arm,pl330", "arm,primecell";
335 reg = <0x0 0xff1f0000 0x0 0x4000>;
336 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&cru ACLK_DMAC>;
339 clock-names = "apb_pclk";
344 saradc: saradc@ff280000 {
345 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
346 reg = <0x0 0xff280000 0x0 0x100>;
347 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
348 #io-channel-cells = <1>;
349 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
350 clock-names = "saradc", "apb_pclk";
351 resets = <&cru SRST_SARADC_P>;
352 reset-names = "saradc-apb";
358 compatible = "rockchip,rk3328-dmc", "syscon";
359 reg = <0x0 0xff400000 0x0 0x1000>;
362 cru: clock-controller@ff440000 {
363 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
364 reg = <0x0 0xff440000 0x0 0x1000>;
365 rockchip,grf = <&grf>;
369 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
370 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
371 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
372 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
373 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
374 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
375 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
376 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
377 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
378 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
379 <&cru SCLK_WIFI>, <&cru ARMCLK>,
380 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
381 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
382 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
383 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
384 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
385 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
386 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
387 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
388 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
389 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
390 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
391 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
392 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
393 assigned-clock-parents =
394 <&cru HDMIPHY>, <&cru PLL_APLL>,
395 <&cru PLL_GPLL>, <&xin24m>,
396 <&xin24m>, <&xin24m>;
397 assigned-clock-rates =
400 <24000000>, <24000000>,
401 <15000000>, <15000000>,
402 <100000000>, <100000000>,
403 <100000000>, <100000000>,
404 <50000000>, <100000000>,
405 <100000000>, <100000000>,
406 <50000000>, <50000000>,
407 <50000000>, <50000000>,
408 <24000000>, <600000000>,
409 <491520000>, <1200000000>,
410 <150000000>, <75000000>,
411 <75000000>, <150000000>,
412 <75000000>, <75000000>,
413 <300000000>, <100000000>,
414 <300000000>, <200000000>,
415 <400000000>, <500000000>,
416 <200000000>, <300000000>,
417 <300000000>, <250000000>,
418 <200000000>, <100000000>,
419 <24000000>, <100000000>,
420 <150000000>, <50000000>,
424 sdmmc: rksdmmc@ff500000 {
425 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
426 reg = <0x0 0xff500000 0x0 0x4000>;
427 max-frequency = <150000000>;
428 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
429 clock-names = "biu", "ciu";
430 fifo-depth = <0x100>;
431 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
435 sdio: dwmmc@ff510000 {
436 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
437 reg = <0x0 0xff510000 0x0 0x4000>;
438 max-frequency = <150000000>;
439 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
440 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
441 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
442 fifo-depth = <0x100>;
443 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
447 emmc: rksdmmc@ff520000 {
448 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
449 reg = <0x0 0xff520000 0x0 0x4000>;
450 max-frequency = <150000000>;
451 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
452 clock-names = "biu", "ciu";
453 fifo-depth = <0x100>;
454 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
458 gmac2io: ethernet@ff540000 {
459 compatible = "rockchip,rk3328-gmac";
460 reg = <0x0 0xff540000 0x0 0x10000>;
461 rockchip,grf = <&grf>;
462 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
463 interrupt-names = "macirq";
464 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
465 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
466 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
468 clock-names = "stmmaceth", "mac_clk_rx",
469 "mac_clk_tx", "clk_mac_ref",
470 "clk_mac_refout", "aclk_mac",
472 resets = <&cru SRST_GMAC2IO_A>;
473 reset-names = "stmmaceth";
477 usb_host0_ehci: usb@ff5c0000 {
478 compatible = "generic-ehci";
479 reg = <0x0 0xff5c0000 0x0 0x10000>;
480 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
484 usb_host0_ohci: usb@ff5d0000 {
485 compatible = "generic-ohci";
486 reg = <0x0 0xff5d0000 0x0 0x10000>;
487 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
491 usb20_otg: usb@ff580000 {
492 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
494 reg = <0x0 0xff580000 0x0 0x40000>;
495 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
501 sdmmc_ext: rksdmmc@ff5f0000 {
502 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
503 reg = <0x0 0xff5f0000 0x0 0x4000>;
504 max-frequency = <150000000>;
505 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
506 clock-names = "biu", "ciu";
507 fifo-depth = <0x100>;
508 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
512 usb_host0_xhci: usb@ff600000 {
513 compatible = "rockchip,rk3328-xhci";
514 reg = <0x0 0xff600000 0x0 0x100000>;
515 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
516 snps,dis-enblslpm-quirk;
517 snps,phyif-utmi-bits = <16>;
518 snps,dis-u2-freeclk-exists-quirk;
519 snps,dis-u2-susphy-quirk;
523 gic: interrupt-controller@ffb70000 {
524 compatible = "arm,gic-400";
525 #interrupt-cells = <3>;
526 #address-cells = <0>;
527 interrupt-controller;
528 reg = <0x0 0xff811000 0 0x1000>,
529 <0x0 0xff812000 0 0x2000>,
530 <0x0 0xff814000 0 0x2000>,
531 <0x0 0xff816000 0 0x2000>;
532 interrupts = <GIC_PPI 9
533 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
537 compatible = "rockchip,rk3328-pinctrl";
538 rockchip,grf = <&grf>;
539 #address-cells = <2>;
543 gpio0: gpio0@ff210000 {
544 compatible = "rockchip,gpio-bank";
545 reg = <0x0 0xff210000 0x0 0x100>;
546 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&cru PCLK_GPIO0>;
552 interrupt-controller;
553 #interrupt-cells = <2>;
556 gpio1: gpio1@ff220000 {
557 compatible = "rockchip,gpio-bank";
558 reg = <0x0 0xff220000 0x0 0x100>;
559 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&cru PCLK_GPIO1>;
565 interrupt-controller;
566 #interrupt-cells = <2>;
569 gpio2: gpio2@ff230000 {
570 compatible = "rockchip,gpio-bank";
571 reg = <0x0 0xff230000 0x0 0x100>;
572 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&cru PCLK_GPIO2>;
578 interrupt-controller;
579 #interrupt-cells = <2>;
582 gpio3: gpio3@ff240000 {
583 compatible = "rockchip,gpio-bank";
584 reg = <0x0 0xff240000 0x0 0x100>;
585 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&cru PCLK_GPIO3>;
591 interrupt-controller;
592 #interrupt-cells = <2>;
595 pcfg_pull_up: pcfg-pull-up {
599 pcfg_pull_down: pcfg-pull-down {
603 pcfg_pull_none: pcfg-pull-none {
607 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
609 drive-strength = <2>;
612 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
614 drive-strength = <2>;
617 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
619 drive-strength = <4>;
622 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
624 drive-strength = <4>;
627 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
629 drive-strength = <4>;
632 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
634 drive-strength = <8>;
637 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
639 drive-strength = <8>;
642 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
644 drive-strength = <12>;
647 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
649 drive-strength = <12>;
652 pcfg_output_high: pcfg-output-high {
656 pcfg_output_low: pcfg-output-low {
660 pcfg_input_high: pcfg-input-high {
665 pcfg_input: pcfg-input {
670 i2c0_xfer: i2c0-xfer {
672 <2 24 RK_FUNC_1 &pcfg_pull_none>,
673 <2 25 RK_FUNC_1 &pcfg_pull_none>;
678 i2c1_xfer: i2c1-xfer {
680 <2 4 RK_FUNC_2 &pcfg_pull_none>,
681 <2 5 RK_FUNC_2 &pcfg_pull_none>;
686 i2c2_xfer: i2c2-xfer {
688 <2 13 RK_FUNC_1 &pcfg_pull_none>,
689 <2 14 RK_FUNC_1 &pcfg_pull_none>;
694 i2c3_xfer: i2c3-xfer {
696 <0 5 RK_FUNC_2 &pcfg_pull_none>,
697 <0 6 RK_FUNC_2 &pcfg_pull_none>;
699 i2c3_gpio: i2c3-gpio {
701 <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
702 <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
707 hdmii2c_xfer: hdmii2c-xfer {
709 <0 5 RK_FUNC_1 &pcfg_pull_none>,
710 <0 6 RK_FUNC_1 &pcfg_pull_none>;
715 uart0_xfer: uart0-xfer {
717 <1 9 RK_FUNC_1 &pcfg_pull_up>,
718 <1 8 RK_FUNC_1 &pcfg_pull_none>;
721 uart0_cts: uart0-cts {
723 <1 11 RK_FUNC_1 &pcfg_pull_none>;
726 uart0_rts: uart0-rts {
728 <1 10 RK_FUNC_1 &pcfg_pull_none>;
731 uart0_rts_gpio: uart0-rts-gpio {
733 <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
738 uart1_xfer: uart1-xfer {
740 <3 4 RK_FUNC_4 &pcfg_pull_up>,
741 <3 6 RK_FUNC_4 &pcfg_pull_none>;
744 uart1_cts: uart1-cts {
746 <3 7 RK_FUNC_4 &pcfg_pull_none>;
749 uart1_rts: uart1-rts {
751 <3 5 RK_FUNC_4 &pcfg_pull_none>;
754 uart1_rts_gpio: uart1-rts-gpio {
756 <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
761 uart2m0_xfer: uart2m0-xfer {
763 <1 0 RK_FUNC_2 &pcfg_pull_up>,
764 <1 1 RK_FUNC_2 &pcfg_pull_none>;
769 uart2m1_xfer: uart2m1-xfer {
771 <2 0 RK_FUNC_1 &pcfg_pull_up>,
772 <2 1 RK_FUNC_1 &pcfg_pull_none>;
777 spi0m0_clk: spi0m0-clk {
779 <2 8 RK_FUNC_1 &pcfg_pull_up>;
782 spi0m0_cs0: spi0m0-cs0 {
784 <2 11 RK_FUNC_1 &pcfg_pull_up>;
787 spi0m0_tx: spi0m0-tx {
789 <2 9 RK_FUNC_1 &pcfg_pull_up>;
792 spi0m0_rx: spi0m0-rx {
794 <2 10 RK_FUNC_1 &pcfg_pull_up>;
797 spi0m0_cs1: spi0m0-cs1 {
799 <2 12 RK_FUNC_1 &pcfg_pull_up>;
804 spi0m1_clk: spi0m1-clk {
806 <3 23 RK_FUNC_2 &pcfg_pull_up>;
809 spi0m1_cs0: spi0m1-cs0 {
811 <3 26 RK_FUNC_2 &pcfg_pull_up>;
814 spi0m1_tx: spi0m1-tx {
816 <3 25 RK_FUNC_2 &pcfg_pull_up>;
819 spi0m1_rx: spi0m1-rx {
821 <3 24 RK_FUNC_2 &pcfg_pull_up>;
824 spi0m1_cs1: spi0m1-cs1 {
826 <3 27 RK_FUNC_2 &pcfg_pull_up>;
831 spi0m2_clk: spi0m2-clk {
833 <3 0 RK_FUNC_4 &pcfg_pull_up>;
836 spi0m2_cs0: spi0m2-cs0 {
838 <3 8 RK_FUNC_3 &pcfg_pull_up>;
841 spi0m2_tx: spi0m2-tx {
843 <3 1 RK_FUNC_4 &pcfg_pull_up>;
846 spi0m2_rx: spi0m2-rx {
848 <3 2 RK_FUNC_4 &pcfg_pull_up>;
853 i2s1_mclk: i2s1-mclk {
855 <2 15 RK_FUNC_1 &pcfg_pull_none>;
858 i2s1_sclk: i2s1-sclk {
860 <2 18 RK_FUNC_1 &pcfg_pull_none>;
863 i2s1_lrckrx: i2s1-lrckrx {
865 <2 16 RK_FUNC_1 &pcfg_pull_none>;
868 i2s1_lrcktx: i2s1-lrcktx {
870 <2 17 RK_FUNC_1 &pcfg_pull_none>;
875 <2 19 RK_FUNC_1 &pcfg_pull_none>;
880 <2 23 RK_FUNC_1 &pcfg_pull_none>;
883 i2s1_sdio1: i2s1-sdio1 {
885 <2 20 RK_FUNC_1 &pcfg_pull_none>;
888 i2s1_sdio2: i2s1-sdio2 {
890 <2 21 RK_FUNC_1 &pcfg_pull_none>;
893 i2s1_sdio3: i2s1-sdio3 {
895 <2 22 RK_FUNC_1 &pcfg_pull_none>;
898 i2s1_sleep: i2s1-sleep {
900 <2 15 RK_FUNC_GPIO &pcfg_input_high>,
901 <2 16 RK_FUNC_GPIO &pcfg_input_high>,
902 <2 17 RK_FUNC_GPIO &pcfg_input_high>,
903 <2 18 RK_FUNC_GPIO &pcfg_input_high>,
904 <2 19 RK_FUNC_GPIO &pcfg_input_high>,
905 <2 20 RK_FUNC_GPIO &pcfg_input_high>,
906 <2 21 RK_FUNC_GPIO &pcfg_input_high>,
907 <2 22 RK_FUNC_GPIO &pcfg_input_high>,
908 <2 23 RK_FUNC_GPIO &pcfg_input_high>;
913 i2s2m0_mclk: i2s2m0-mclk {
915 <1 21 RK_FUNC_1 &pcfg_pull_none>;
918 i2s2m0_sclk: i2s2m0-sclk {
920 <1 22 RK_FUNC_1 &pcfg_pull_none>;
923 i2s2m0_lrckrx: i2s2m0-lrckrx {
925 <1 26 RK_FUNC_1 &pcfg_pull_none>;
928 i2s2m0_lrcktx: i2s2m0-lrcktx {
930 <1 23 RK_FUNC_1 &pcfg_pull_none>;
933 i2s2m0_sdi: i2s2m0-sdi {
935 <1 24 RK_FUNC_1 &pcfg_pull_none>;
938 i2s2m0_sdo: i2s2m0-sdo {
940 <1 25 RK_FUNC_1 &pcfg_pull_none>;
943 i2s2m0_sleep: i2s2m0-sleep {
945 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
946 <1 22 RK_FUNC_GPIO &pcfg_input_high>,
947 <1 26 RK_FUNC_GPIO &pcfg_input_high>,
948 <1 23 RK_FUNC_GPIO &pcfg_input_high>,
949 <1 24 RK_FUNC_GPIO &pcfg_input_high>,
950 <1 25 RK_FUNC_GPIO &pcfg_input_high>;
955 i2s2m1_mclk: i2s2m1-mclk {
957 <1 21 RK_FUNC_1 &pcfg_pull_none>;
960 i2s2m1_sclk: i2s2m1-sclk {
962 <3 0 RK_FUNC_6 &pcfg_pull_none>;
965 i2s2m1_lrckrx: i2sm1-lrckrx {
967 <3 8 RK_FUNC_6 &pcfg_pull_none>;
970 i2s2m1_lrcktx: i2s2m1-lrcktx {
972 <3 8 RK_FUNC_4 &pcfg_pull_none>;
975 i2s2m1_sdi: i2s2m1-sdi {
977 <3 2 RK_FUNC_6 &pcfg_pull_none>;
980 i2s2m1_sdo: i2s2m1-sdo {
982 <3 1 RK_FUNC_6 &pcfg_pull_none>;
985 i2s2m1_sleep: i2s2m1-sleep {
987 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
988 <3 0 RK_FUNC_GPIO &pcfg_input_high>,
989 <3 8 RK_FUNC_GPIO &pcfg_input_high>,
990 <3 2 RK_FUNC_GPIO &pcfg_input_high>,
991 <3 1 RK_FUNC_GPIO &pcfg_input_high>;
996 spdifm0_tx: spdifm0-tx {
998 <0 27 RK_FUNC_1 &pcfg_pull_none>;
1003 spdifm1_tx: spdifm1-tx {
1005 <2 17 RK_FUNC_2 &pcfg_pull_none>;
1010 spdifm2_tx: spdifm2-tx {
1012 <0 2 RK_FUNC_2 &pcfg_pull_none>;
1017 sdmmc0m0_pwren: sdmmc0m0-pwren {
1019 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1022 sdmmc0m0_gpio: sdmmc0m0-gpio {
1024 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1029 sdmmc0m1_pwren: sdmmc0m1-pwren {
1031 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1034 sdmmc0m1_gpio: sdmmc0m1-gpio {
1036 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1041 sdmmc0_clk: sdmmc0-clk {
1043 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1046 sdmmc0_cmd: sdmmc0-cmd {
1048 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1051 sdmmc0_dectn: sdmmc0-dectn {
1053 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1056 sdmmc0_wrprt: sdmmc0-wrprt {
1058 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1061 sdmmc0_bus1: sdmmc0-bus1 {
1063 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1066 sdmmc0_bus4: sdmmc0-bus4 {
1068 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1069 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1070 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1071 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1074 sdmmc0_gpio: sdmmc0-gpio {
1076 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1077 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1078 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1079 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1080 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1081 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1082 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1083 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1088 sdmmc0ext_clk: sdmmc0ext-clk {
1090 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1093 sdmmc0ext_cmd: sdmmc0ext-cmd {
1095 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1098 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1100 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1103 sdmmc0ext_dectn: sdmmc0ext-dectn {
1105 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1108 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1110 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1113 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1115 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1116 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1117 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1118 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1121 sdmmc0ext_gpio: sdmmc0ext-gpio {
1123 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1124 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1125 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1126 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1127 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1128 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1129 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1130 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1135 sdmmc1_clk: sdmmc1-clk {
1137 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1140 sdmmc1_cmd: sdmmc1-cmd {
1142 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1145 sdmmc1_pwren: sdmmc1-pwren {
1147 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1150 sdmmc1_wrprt: sdmmc1-wrprt {
1152 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1155 sdmmc1_dectn: sdmmc1-dectn {
1157 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1160 sdmmc1_bus1: sdmmc1-bus1 {
1162 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1165 sdmmc1_bus4: sdmmc1-bus4 {
1167 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1168 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1169 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1170 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1173 sdmmc1_gpio: sdmmc1-gpio {
1175 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1176 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1177 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1178 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1179 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1180 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1181 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1182 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1183 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1188 emmc_clk: emmc-clk {
1190 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1193 emmc_cmd: emmc-cmd {
1195 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1198 emmc_pwren: emmc-pwren {
1200 <3 22 RK_FUNC_2 &pcfg_pull_none>;
1203 emmc_rstnout: emmc-rstnout {
1205 <3 20 RK_FUNC_2 &pcfg_pull_none>;
1208 emmc_bus1: emmc-bus1 {
1210 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1213 emmc_bus4: emmc-bus4 {
1215 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1216 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1217 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1218 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1221 emmc_bus8: emmc-bus8 {
1223 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1224 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1225 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1226 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1227 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1228 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1229 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1230 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1235 pwm0_pin: pwm0-pin {
1237 <2 4 RK_FUNC_1 &pcfg_pull_none>;
1242 pwm1_pin: pwm1-pin {
1244 <2 5 RK_FUNC_1 &pcfg_pull_none>;
1249 pwm2_pin: pwm2-pin {
1251 <2 6 RK_FUNC_1 &pcfg_pull_none>;
1256 pwmir_pin: pwmir-pin {
1258 <2 2 RK_FUNC_1 &pcfg_pull_none>;
1263 rgmiim0_pins: rgmiim0-pins {
1266 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1268 <0 10 RK_FUNC_1 &pcfg_pull_none>,
1270 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1272 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1274 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1276 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1278 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1280 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1282 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1284 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1286 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1288 <0 20 RK_FUNC_1 &pcfg_pull_none>,
1290 <0 21 RK_FUNC_1 &pcfg_pull_none>,
1292 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1294 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1297 rmiim0_pins: rmiim0-pins {
1300 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1302 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1304 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1306 <0 13 RK_FUNC_1 &pcfg_pull_none>,
1308 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1310 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1312 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1314 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1316 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1318 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1323 rgmiim1_pins: rgmiim1-pins {
1326 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1328 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1330 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1332 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1334 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1336 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1338 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1340 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1342 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1344 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1346 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1348 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1350 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1352 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1354 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1357 <0 8 RK_FUNC_1 &pcfg_pull_none>,
1359 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1361 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1363 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1365 <0 17 RK_FUNC_1 &pcfg_pull_none>,
1367 <0 23 RK_FUNC_1 &pcfg_pull_none>,
1369 <0 22 RK_FUNC_1 &pcfg_pull_none>;
1372 rmiim1_pins: rmiim1-pins {
1375 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1377 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1379 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1381 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1383 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1385 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1387 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1389 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1391 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1393 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1396 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1398 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1400 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1402 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1404 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1406 <0 17 RK_FUNC_1 &pcfg_pull_none>;
1411 fephyled_speed100: fephyled-speed100 {
1413 <0 31 RK_FUNC_1 &pcfg_pull_none>;
1416 fephyled_speed10: fephyled-speed10 {
1418 <0 30 RK_FUNC_1 &pcfg_pull_none>;
1421 fephyled_duplex: fephyled-duplex {
1423 <0 30 RK_FUNC_2 &pcfg_pull_none>;
1426 fephyled_rxm0: fephyled-rxm0 {
1428 <0 29 RK_FUNC_1 &pcfg_pull_none>;
1431 fephyled_txm0: fephyled-txm0 {
1433 <0 29 RK_FUNC_2 &pcfg_pull_none>;
1436 fephyled_linkm0: fephyled-linkm0 {
1438 <0 28 RK_FUNC_1 &pcfg_pull_none>;
1441 fephyled_rxm1: fephyled-rxm1 {
1443 <2 25 RK_FUNC_2 &pcfg_pull_none>;
1446 fephyled_txm1: fephyled-txm1 {
1448 <2 25 RK_FUNC_3 &pcfg_pull_none>;
1451 fephyled_linkm1: fephyled-linkm1 {
1453 <2 24 RK_FUNC_2 &pcfg_pull_none>;
1458 tsadc_int: tsadc-int {
1460 <2 13 RK_FUNC_2 &pcfg_pull_none>;
1462 tsadc_gpio: tsadc-gpio {
1464 <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1469 hdmi_cec: hdmi-cec {
1471 <0 3 RK_FUNC_1 &pcfg_pull_none>;
1474 hdmi_hpd: hdmi-hpd {
1476 <0 4 RK_FUNC_1 &pcfg_pull_down>;
1481 dvp_d2d9_m0:dvp-d2d9-m0 {
1484 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1486 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1488 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1490 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1492 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1494 <3 9 RK_FUNC_2 &pcfg_pull_none>,
1496 <3 10 RK_FUNC_2 &pcfg_pull_none>,
1498 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1500 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1502 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1504 <3 3 RK_FUNC_2 &pcfg_pull_none>,
1506 <3 2 RK_FUNC_2 &pcfg_pull_none>;
1511 dvp_d2d9_m1:dvp-d2d9-m1 {
1514 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1516 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1518 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1520 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1522 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1524 <2 16 RK_FUNC_4 &pcfg_pull_none>,
1526 <2 17 RK_FUNC_4 &pcfg_pull_none>,
1528 <2 18 RK_FUNC_4 &pcfg_pull_none>,
1530 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1532 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1534 <2 15 RK_FUNC_4 &pcfg_pull_none>,
1536 <3 2 RK_FUNC_2 &pcfg_pull_none>;