2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/clock/rk3328-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
14 compatible = "rockchip,rk3328";
16 interrupt-parent = <&gic>;
36 compatible = "arm,cortex-a53", "arm,armv8";
38 enable-method = "psci";
39 // clocks = <&cru ARMCLK>;
40 operating-points-v2 = <&cpu0_opp_table>;
44 compatible = "arm,cortex-a53", "arm,armv8";
46 enable-method = "psci";
50 compatible = "arm,cortex-a53", "arm,armv8";
52 enable-method = "psci";
56 compatible = "arm,cortex-a53", "arm,armv8";
58 enable-method = "psci";
62 cpu0_opp_table: opp_table0 {
63 compatible = "operating-points-v2";
67 opp-hz = /bits/ 64 <408000000>;
68 opp-microvolt = <950000>;
69 clock-latency-ns = <40000>;
73 opp-hz = /bits/ 64 <600000000>;
74 opp-microvolt = <950000>;
75 clock-latency-ns = <40000>;
78 opp-hz = /bits/ 64 <816000000>;
79 opp-microvolt = <1000000>;
80 clock-latency-ns = <40000>;
83 opp-hz = /bits/ 64 <1008000000>;
84 opp-microvolt = <1100000>;
85 clock-latency-ns = <40000>;
88 opp-hz = /bits/ 64 <1200000000>;
89 opp-microvolt = <1225000>;
90 clock-latency-ns = <40000>;
93 opp-hz = /bits/ 64 <1296000000>;
94 opp-microvolt = <1300000>;
95 clock-latency-ns = <40000>;
100 compatible = "arm,cortex-a53-pmu";
101 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
105 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
109 compatible = "arm,psci-1.0";
114 compatible = "arm,armv8-timer";
115 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
116 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
117 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
118 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
122 compatible = "fixed-clock";
124 clock-frequency = <24000000>;
125 clock-output-names = "xin24m";
129 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
130 reg = <0x0 0xff000000 0x0 0x1000>;
131 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
132 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
133 clock-names = "i2s_clk", "i2s_hclk";
134 dmas = <&dmac 11>, <&dmac 12>;
136 dma-names = "tx", "rx";
141 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
142 reg = <0x0 0xff010000 0x0 0x1000>;
143 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
145 clock-names = "i2s_clk", "i2s_hclk";
146 dmas = <&dmac 14>, <&dmac 15>;
148 dma-names = "tx", "rx";
153 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
154 reg = <0x0 0xff020000 0x0 0x1000>;
155 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
157 clock-names = "i2s_clk", "i2s_hclk";
158 dmas = <&dmac 0>, <&dmac 1>;
160 dma-names = "tx", "rx";
161 pinctrl-names = "default", "sleep";
162 pinctrl-0 = <&i2s2m0_mclk
168 pinctrl-1 = <&i2s2m0_sleep>;
172 spdif: spdif@ff030000 {
173 compatible = "rockchip,rk3328-spdif";
174 reg = <0x0 0xff030000 0x0 0x1000>;
175 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
177 clock-names = "mclk", "hclk";
181 pinctrl-names = "default";
182 pinctrl-0 = <&spdifm2_tx>;
186 grf: syscon@ff100000 {
187 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
188 reg = <0x0 0xff100000 0x0 0x1000>;
189 #address-cells = <1>;
192 io_domains: io-domains {
193 compatible = "rockchip,rk3328-io-voltage-domain";
198 uart0: serial@ff110000 {
199 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
200 reg = <0x0 0xff110000 0x0 0x100>;
201 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
203 clock-names = "baudclk", "apb_pclk";
206 dmas = <&dmac 2>, <&dmac 3>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
213 uart1: serial@ff120000 {
214 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
215 reg = <0x0 0xff120000 0x0 0x100>;
216 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
218 clock-names = "sclk_uart", "pclk_uart";
221 dmas = <&dmac 4>, <&dmac 5>;
223 pinctrl-names = "default";
224 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
228 uart2: serial@ff130000 {
229 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
230 reg = <0x0 0xff130000 0x0 0x100>;
231 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
233 clock-names = "baudclk", "apb_pclk";
234 clock-frequency = <24000000>;
237 dmas = <&dmac 6>, <&dmac 7>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&uart2m1_xfer>;
244 pmu: power-management@ff140000 {
245 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
246 reg = <0x0 0xff140000 0x0 0x1000>;
250 compatible = "rockchip,rk3328-i2c";
251 reg = <0x0 0xff150000 0x0 0x1000>;
252 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
253 #address-cells = <1>;
255 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
256 clock-names = "i2c", "pclk";
257 pinctrl-names = "default";
258 pinctrl-0 = <&i2c0_xfer>;
263 compatible = "rockchip,rk3328-i2c";
264 reg = <0x0 0xff160000 0x0 0x1000>;
265 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
266 #address-cells = <1>;
268 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
269 clock-names = "i2c", "pclk";
270 pinctrl-names = "default";
271 pinctrl-0 = <&i2c1_xfer>;
276 compatible = "rockchip,rk3328-i2c";
277 reg = <0x0 0xff170000 0x0 0x1000>;
278 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
279 #address-cells = <1>;
281 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
282 clock-names = "i2c", "pclk";
283 pinctrl-names = "default";
284 pinctrl-0 = <&i2c2_xfer>;
289 compatible = "rockchip,rk3328-i2c";
290 reg = <0x0 0xff180000 0x0 0x1000>;
291 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
292 #address-cells = <1>;
294 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
295 clock-names = "i2c", "pclk";
296 pinctrl-names = "default";
297 pinctrl-0 = <&i2c3_xfer>;
302 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
303 reg = <0x0 0xff190000 0x0 0x1000>;
304 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
305 #address-cells = <1>;
307 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
308 clock-names = "spiclk", "apb_pclk";
309 dmas = <&dmac 8>, <&dmac 9>;
311 dma-names = "tx", "rx";
312 pinctrl-names = "default";
313 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
317 wdt: watchdog@ff1a0000 {
318 compatible = "snps,dw-wdt";
319 reg = <0x0 0xff1a0000 0x0 0x100>;
320 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
325 compatible = "simple-bus";
326 #address-cells = <2>;
330 dmac: dmac@ff1f0000 {
331 compatible = "arm,pl330", "arm,primecell";
332 reg = <0x0 0xff1f0000 0x0 0x4000>;
333 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&cru ACLK_DMAC>;
336 clock-names = "apb_pclk";
341 saradc: saradc@ff280000 {
342 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
343 reg = <0x0 0xff280000 0x0 0x100>;
344 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
345 #io-channel-cells = <1>;
346 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
347 clock-names = "saradc", "apb_pclk";
348 resets = <&cru SRST_SARADC_P>;
349 reset-names = "saradc-apb";
353 cru: clock-controller@ff440000 {
354 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
355 reg = <0x0 0xff440000 0x0 0x1000>;
356 rockchip,grf = <&grf>;
360 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
361 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
362 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
363 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
364 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
365 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
366 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
367 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
368 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
369 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
370 <&cru SCLK_WIFI>, <&cru ARMCLK>,
371 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
372 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
373 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
374 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
375 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
376 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
377 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
378 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
379 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
380 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
381 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
382 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
383 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
384 assigned-clock-parents =
385 <&cru HDMIPHY>, <&cru PLL_APLL>,
386 <&cru PLL_GPLL>, <&xin24m>,
387 <&xin24m>, <&xin24m>;
388 assigned-clock-rates =
391 <24000000>, <24000000>,
392 <15000000>, <15000000>,
393 <100000000>, <100000000>,
394 <100000000>, <100000000>,
395 <50000000>, <100000000>,
396 <100000000>, <100000000>,
397 <50000000>, <50000000>,
398 <50000000>, <50000000>,
399 <24000000>, <600000000>,
400 <491520000>, <1200000000>,
401 <150000000>, <75000000>,
402 <75000000>, <150000000>,
403 <75000000>, <75000000>,
404 <300000000>, <100000000>,
405 <300000000>, <200000000>,
406 <400000000>, <500000000>,
407 <200000000>, <300000000>,
408 <300000000>, <250000000>,
409 <200000000>, <100000000>,
410 <24000000>, <100000000>,
411 <150000000>, <50000000>,
415 sdmmc: rksdmmc@ff500000 {
416 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
417 reg = <0x0 0xff500000 0x0 0x4000>;
418 clock-freq-min-max = <400000 150000000>;
419 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
420 clock-names = "biu", "ciu";
421 fifo-depth = <0x100>;
422 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
426 sdio: dwmmc@ff510000 {
427 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
428 reg = <0x0 0xff510000 0x0 0x4000>;
429 clock-freq-min-max = <400000 150000000>;
430 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
431 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
432 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
433 fifo-depth = <0x100>;
434 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
438 emmc: rksdmmc@ff520000 {
439 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
440 reg = <0x0 0xff520000 0x0 0x4000>;
441 clock-freq-min-max = <400000 150000000>;
442 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
443 clock-names = "biu", "ciu";
444 fifo-depth = <0x100>;
445 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
449 sdmmc_ext: rksdmmc@ff5f0000 {
450 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
451 reg = <0x0 0xff5f0000 0x0 0x4000>;
452 clock-freq-min-max = <400000 150000000>;
453 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
454 clock-names = "biu", "ciu";
455 fifo-depth = <0x100>;
456 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
460 gic: interrupt-controller@ffb70000 {
461 compatible = "arm,gic-400";
462 #interrupt-cells = <3>;
463 #address-cells = <0>;
464 interrupt-controller;
465 reg = <0x0 0xff811000 0 0x1000>,
466 <0x0 0xff812000 0 0x2000>,
467 <0x0 0xff814000 0 0x2000>,
468 <0x0 0xff816000 0 0x2000>;
469 interrupts = <GIC_PPI 9
470 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
474 compatible = "rockchip,rk3328-pinctrl";
475 rockchip,grf = <&grf>;
476 #address-cells = <2>;
480 gpio0: gpio0@ff210000 {
481 compatible = "rockchip,gpio-bank";
482 reg = <0x0 0xff210000 0x0 0x100>;
483 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&cru PCLK_GPIO0>;
489 interrupt-controller;
490 #interrupt-cells = <2>;
493 gpio1: gpio1@ff220000 {
494 compatible = "rockchip,gpio-bank";
495 reg = <0x0 0xff220000 0x0 0x100>;
496 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&cru PCLK_GPIO1>;
502 interrupt-controller;
503 #interrupt-cells = <2>;
506 gpio2: gpio2@ff230000 {
507 compatible = "rockchip,gpio-bank";
508 reg = <0x0 0xff230000 0x0 0x100>;
509 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&cru PCLK_GPIO2>;
515 interrupt-controller;
516 #interrupt-cells = <2>;
519 gpio3: gpio3@ff240000 {
520 compatible = "rockchip,gpio-bank";
521 reg = <0x0 0xff240000 0x0 0x100>;
522 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&cru PCLK_GPIO3>;
528 interrupt-controller;
529 #interrupt-cells = <2>;
532 pcfg_pull_up: pcfg-pull-up {
536 pcfg_pull_down: pcfg-pull-down {
540 pcfg_pull_none: pcfg-pull-none {
544 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
546 drive-strength = <2>;
549 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
551 drive-strength = <2>;
554 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
556 drive-strength = <4>;
559 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
561 drive-strength = <4>;
564 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
566 drive-strength = <4>;
569 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
571 drive-strength = <8>;
574 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
576 drive-strength = <8>;
579 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
581 drive-strength = <12>;
584 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
586 drive-strength = <12>;
589 pcfg_output_high: pcfg-output-high {
593 pcfg_output_low: pcfg-output-low {
597 pcfg_input_high: pcfg-input-high {
602 pcfg_input: pcfg-input {
607 i2c0_xfer: i2c0-xfer {
609 <2 24 RK_FUNC_1 &pcfg_pull_none>,
610 <2 25 RK_FUNC_1 &pcfg_pull_none>;
615 i2c1_xfer: i2c1-xfer {
617 <2 4 RK_FUNC_2 &pcfg_pull_none>,
618 <2 5 RK_FUNC_2 &pcfg_pull_none>;
623 i2c2_xfer: i2c2-xfer {
625 <2 13 RK_FUNC_1 &pcfg_pull_none>,
626 <2 14 RK_FUNC_1 &pcfg_pull_none>;
631 i2c3_xfer: i2c3-xfer {
633 <0 5 RK_FUNC_2 &pcfg_pull_none>,
634 <0 6 RK_FUNC_2 &pcfg_pull_none>;
636 i2c3_gpio: i2c3-gpio {
638 <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
639 <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
644 hdmii2c_xfer: hdmii2c-xfer {
646 <0 5 RK_FUNC_1 &pcfg_pull_none>,
647 <0 6 RK_FUNC_1 &pcfg_pull_none>;
652 uart0_xfer: uart0-xfer {
654 <1 9 RK_FUNC_1 &pcfg_pull_up>,
655 <1 8 RK_FUNC_1 &pcfg_pull_none>;
658 uart0_cts: uart0-cts {
660 <1 11 RK_FUNC_1 &pcfg_pull_none>;
663 uart0_rts: uart0-rts {
665 <1 10 RK_FUNC_1 &pcfg_pull_none>;
668 uart0_rts_gpio: uart0-rts-gpio {
670 <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
675 uart1_xfer: uart1-xfer {
677 <3 4 RK_FUNC_4 &pcfg_pull_up>,
678 <3 6 RK_FUNC_4 &pcfg_pull_none>;
681 uart1_cts: uart1-cts {
683 <3 7 RK_FUNC_4 &pcfg_pull_none>;
686 uart1_rts: uart1-rts {
688 <3 5 RK_FUNC_4 &pcfg_pull_none>;
691 uart1_rts_gpio: uart1-rts-gpio {
693 <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
698 uart2m0_xfer: uart2m0-xfer {
700 <1 0 RK_FUNC_2 &pcfg_pull_up>,
701 <1 1 RK_FUNC_2 &pcfg_pull_none>;
706 uart2m1_xfer: uart2m1-xfer {
708 <2 0 RK_FUNC_1 &pcfg_pull_up>,
709 <2 1 RK_FUNC_1 &pcfg_pull_none>;
714 spi0m0_clk: spi0m0-clk {
716 <2 8 RK_FUNC_1 &pcfg_pull_up>;
719 spi0m0_cs0: spi0m0-cs0 {
721 <2 11 RK_FUNC_1 &pcfg_pull_up>;
724 spi0m0_tx: spi0m0-tx {
726 <2 9 RK_FUNC_1 &pcfg_pull_up>;
729 spi0m0_rx: spi0m0-rx {
731 <2 10 RK_FUNC_1 &pcfg_pull_up>;
734 spi0m0_cs1: spi0m0-cs1 {
736 <2 12 RK_FUNC_1 &pcfg_pull_up>;
741 spi0m1_clk: spi0m1-clk {
743 <3 23 RK_FUNC_2 &pcfg_pull_up>;
746 spi0m1_cs0: spi0m1-cs0 {
748 <3 26 RK_FUNC_2 &pcfg_pull_up>;
751 spi0m1_tx: spi0m1-tx {
753 <3 25 RK_FUNC_2 &pcfg_pull_up>;
756 spi0m1_rx: spi0m1-rx {
758 <3 24 RK_FUNC_2 &pcfg_pull_up>;
761 spi0m1_cs1: spi0m1-cs1 {
763 <3 27 RK_FUNC_2 &pcfg_pull_up>;
768 spi0m2_clk: spi0m2-clk {
770 <3 0 RK_FUNC_4 &pcfg_pull_up>;
773 spi0m2_cs0: spi0m2-cs0 {
775 <3 8 RK_FUNC_3 &pcfg_pull_up>;
778 spi0m2_tx: spi0m2-tx {
780 <3 1 RK_FUNC_4 &pcfg_pull_up>;
783 spi0m2_rx: spi0m2-rx {
785 <3 2 RK_FUNC_4 &pcfg_pull_up>;
790 i2s1_mclk: i2s1-mclk {
792 <2 15 RK_FUNC_1 &pcfg_pull_none>;
795 i2s1_sclk: i2s1-sclk {
797 <2 18 RK_FUNC_1 &pcfg_pull_none>;
800 i2s1_lrckrx: i2s1-lrckrx {
802 <2 16 RK_FUNC_1 &pcfg_pull_none>;
805 i2s1_lrcktx: i2s1-lrcktx {
807 <2 17 RK_FUNC_1 &pcfg_pull_none>;
812 <2 19 RK_FUNC_1 &pcfg_pull_none>;
817 <2 23 RK_FUNC_1 &pcfg_pull_none>;
820 i2s1_sdio1: i2s1-sdio1 {
822 <2 20 RK_FUNC_1 &pcfg_pull_none>;
825 i2s1_sdio2: i2s1-sdio2 {
827 <2 21 RK_FUNC_1 &pcfg_pull_none>;
830 i2s1_sdio3: i2s1-sdio3 {
832 <2 22 RK_FUNC_1 &pcfg_pull_none>;
835 i2s1_sleep: i2s1-sleep {
837 <2 15 RK_FUNC_GPIO &pcfg_input_high>,
838 <2 16 RK_FUNC_GPIO &pcfg_input_high>,
839 <2 17 RK_FUNC_GPIO &pcfg_input_high>,
840 <2 18 RK_FUNC_GPIO &pcfg_input_high>,
841 <2 19 RK_FUNC_GPIO &pcfg_input_high>,
842 <2 20 RK_FUNC_GPIO &pcfg_input_high>,
843 <2 21 RK_FUNC_GPIO &pcfg_input_high>,
844 <2 22 RK_FUNC_GPIO &pcfg_input_high>,
845 <2 23 RK_FUNC_GPIO &pcfg_input_high>;
850 i2s2m0_mclk: i2s2m0-mclk {
852 <1 21 RK_FUNC_1 &pcfg_pull_none>;
855 i2s2m0_sclk: i2s2m0-sclk {
857 <1 22 RK_FUNC_1 &pcfg_pull_none>;
860 i2s2m0_lrckrx: i2s2m0-lrckrx {
862 <1 26 RK_FUNC_1 &pcfg_pull_none>;
865 i2s2m0_lrcktx: i2s2m0-lrcktx {
867 <1 23 RK_FUNC_1 &pcfg_pull_none>;
870 i2s2m0_sdi: i2s2m0-sdi {
872 <1 24 RK_FUNC_1 &pcfg_pull_none>;
875 i2s2m0_sdo: i2s2m0-sdo {
877 <1 25 RK_FUNC_1 &pcfg_pull_none>;
880 i2s2m0_sleep: i2s2m0-sleep {
882 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
883 <1 22 RK_FUNC_GPIO &pcfg_input_high>,
884 <1 26 RK_FUNC_GPIO &pcfg_input_high>,
885 <1 23 RK_FUNC_GPIO &pcfg_input_high>,
886 <1 24 RK_FUNC_GPIO &pcfg_input_high>,
887 <1 25 RK_FUNC_GPIO &pcfg_input_high>;
892 i2s2m1_mclk: i2s2m1-mclk {
894 <1 21 RK_FUNC_1 &pcfg_pull_none>;
897 i2s2m1_sclk: i2s2m1-sclk {
899 <3 0 RK_FUNC_6 &pcfg_pull_none>;
902 i2s2m1_lrckrx: i2sm1-lrckrx {
904 <3 8 RK_FUNC_6 &pcfg_pull_none>;
907 i2s2m1_lrcktx: i2s2m1-lrcktx {
909 <3 8 RK_FUNC_4 &pcfg_pull_none>;
912 i2s2m1_sdi: i2s2m1-sdi {
914 <3 2 RK_FUNC_6 &pcfg_pull_none>;
917 i2s2m1_sdo: i2s2m1-sdo {
919 <3 1 RK_FUNC_6 &pcfg_pull_none>;
922 i2s2m1_sleep: i2s2m1-sleep {
924 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
925 <3 0 RK_FUNC_GPIO &pcfg_input_high>,
926 <3 8 RK_FUNC_GPIO &pcfg_input_high>,
927 <3 2 RK_FUNC_GPIO &pcfg_input_high>,
928 <3 1 RK_FUNC_GPIO &pcfg_input_high>;
933 spdifm0_tx: spdifm0-tx {
935 <0 27 RK_FUNC_1 &pcfg_pull_none>;
940 spdifm1_tx: spdifm1-tx {
942 <2 17 RK_FUNC_2 &pcfg_pull_none>;
947 spdifm2_tx: spdifm2-tx {
949 <0 2 RK_FUNC_2 &pcfg_pull_none>;
954 sdmmc0m0_pwren: sdmmc0m0-pwren {
956 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
959 sdmmc0m0_gpio: sdmmc0m0-gpio {
961 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
966 sdmmc0m1_pwren: sdmmc0m1-pwren {
968 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
971 sdmmc0m1_gpio: sdmmc0m1-gpio {
973 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
978 sdmmc0_clk: sdmmc0-clk {
980 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
983 sdmmc0_cmd: sdmmc0-cmd {
985 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
988 sdmmc0_dectn: sdmmc0-dectn {
990 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
993 sdmmc0_wrprt: sdmmc0-wrprt {
995 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
998 sdmmc0_bus1: sdmmc0-bus1 {
1000 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1003 sdmmc0_bus4: sdmmc0-bus4 {
1005 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1006 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1007 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1008 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1011 sdmmc0_gpio: sdmmc0-gpio {
1013 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1014 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1015 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1016 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1017 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1018 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1019 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1020 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1025 sdmmc0ext_clk: sdmmc0ext-clk {
1027 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1030 sdmmc0ext_cmd: sdmmc0ext-cmd {
1032 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1035 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1037 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1040 sdmmc0ext_dectn: sdmmc0ext-dectn {
1042 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1045 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1047 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1050 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1052 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1053 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1054 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1055 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1058 sdmmc0ext_gpio: sdmmc0ext-gpio {
1060 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1061 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1062 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1063 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1064 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1065 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1066 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1067 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1072 sdmmc1_clk: sdmmc1-clk {
1074 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1077 sdmmc1_cmd: sdmmc1-cmd {
1079 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1082 sdmmc1_pwren: sdmmc1-pwren {
1084 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1087 sdmmc1_wrprt: sdmmc1-wrprt {
1089 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1092 sdmmc1_dectn: sdmmc1-dectn {
1094 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1097 sdmmc1_bus1: sdmmc1-bus1 {
1099 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1102 sdmmc1_bus4: sdmmc1-bus4 {
1104 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1105 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1106 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1107 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1110 sdmmc1_gpio: sdmmc1-gpio {
1112 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1113 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1114 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1115 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1116 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1117 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1118 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1119 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1120 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1125 emmc_clk: emmc-clk {
1127 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1130 emmc_cmd: emmc-cmd {
1132 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1135 emmc_pwren: emmc-pwren {
1137 <3 22 RK_FUNC_2 &pcfg_pull_none>;
1140 emmc_rstnout: emmc-rstnout {
1142 <3 20 RK_FUNC_2 &pcfg_pull_none>;
1145 emmc_bus1: emmc-bus1 {
1147 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1150 emmc_bus4: emmc-bus4 {
1152 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1153 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1154 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1155 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1158 emmc_bus8: emmc-bus8 {
1160 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1161 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1162 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1163 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1164 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1165 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1166 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1167 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1172 pwm0_pin: pwm0-pin {
1174 <2 4 RK_FUNC_1 &pcfg_pull_none>;
1179 pwm1_pin: pwm1-pin {
1181 <2 5 RK_FUNC_1 &pcfg_pull_none>;
1186 pwm2_pin: pwm2-pin {
1188 <2 6 RK_FUNC_1 &pcfg_pull_none>;
1193 pwmir_pin: pwmir-pin {
1195 <2 2 RK_FUNC_1 &pcfg_pull_none>;
1200 rgmiim0_pins: rgmiim0-pins {
1203 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1205 <0 10 RK_FUNC_1 &pcfg_pull_none>,
1207 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1209 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1211 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1213 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1215 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1217 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1219 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1221 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1223 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1225 <0 20 RK_FUNC_1 &pcfg_pull_none>,
1227 <0 21 RK_FUNC_1 &pcfg_pull_none>,
1229 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1231 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1234 rmiim0_pins: rmiim0-pins {
1237 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1239 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1241 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1243 <0 13 RK_FUNC_1 &pcfg_pull_none>,
1245 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1247 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1249 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1251 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1253 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1255 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1260 rgmiim1_pins: rgmiim1-pins {
1263 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1265 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1267 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1269 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1271 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1273 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1275 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1277 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1279 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1281 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1283 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1285 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1287 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1289 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1291 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1294 <0 8 RK_FUNC_1 &pcfg_pull_none>,
1296 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1298 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1300 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1302 <0 17 RK_FUNC_1 &pcfg_pull_none>,
1304 <0 23 RK_FUNC_1 &pcfg_pull_none>,
1306 <0 22 RK_FUNC_1 &pcfg_pull_none>;
1309 rmiim1_pins: rmiim1-pins {
1312 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1314 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1316 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1318 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1320 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1322 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1324 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1326 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1328 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1330 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1333 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1335 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1337 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1339 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1341 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1343 <0 17 RK_FUNC_1 &pcfg_pull_none>;
1348 fephyled_speed100: fephyled-speed100 {
1350 <0 31 RK_FUNC_1 &pcfg_pull_none>;
1353 fephyled_speed10: fephyled-speed10 {
1355 <0 30 RK_FUNC_1 &pcfg_pull_none>;
1358 fephyled_duplex: fephyled-duplex {
1360 <0 30 RK_FUNC_2 &pcfg_pull_none>;
1363 fephyled_rxm0: fephyled-rxm0 {
1365 <0 29 RK_FUNC_1 &pcfg_pull_none>;
1368 fephyled_txm0: fephyled-txm0 {
1370 <0 29 RK_FUNC_2 &pcfg_pull_none>;
1373 fephyled_linkm0: fephyled-linkm0 {
1375 <0 28 RK_FUNC_1 &pcfg_pull_none>;
1378 fephyled_rxm1: fephyled-rxm1 {
1380 <2 25 RK_FUNC_2 &pcfg_pull_none>;
1383 fephyled_txm1: fephyled-txm1 {
1385 <2 25 RK_FUNC_3 &pcfg_pull_none>;
1388 fephyled_linkm1: fephyled-linkm1 {
1390 <2 24 RK_FUNC_2 &pcfg_pull_none>;
1395 tsadc_int: tsadc-int {
1397 <2 13 RK_FUNC_2 &pcfg_pull_none>;
1399 tsadc_gpio: tsadc-gpio {
1401 <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1406 hdmi_cec: hdmi-cec {
1408 <0 3 RK_FUNC_1 &pcfg_pull_none>;
1411 hdmi_hpd: hdmi-hpd {
1413 <0 4 RK_FUNC_1 &pcfg_pull_down>;
1418 dvp_d2d9_m0:dvp-d2d9-m0 {
1421 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1423 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1425 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1427 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1429 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1431 <3 9 RK_FUNC_2 &pcfg_pull_none>,
1433 <3 10 RK_FUNC_2 &pcfg_pull_none>,
1435 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1437 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1439 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1441 <3 3 RK_FUNC_2 &pcfg_pull_none>,
1443 <3 2 RK_FUNC_2 &pcfg_pull_none>;
1448 dvp_d2d9_m1:dvp-d2d9-m1 {
1451 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1453 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1455 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1457 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1459 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1461 <2 16 RK_FUNC_4 &pcfg_pull_none>,
1463 <2 17 RK_FUNC_4 &pcfg_pull_none>,
1465 <2 18 RK_FUNC_4 &pcfg_pull_none>,
1467 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1469 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1471 <2 15 RK_FUNC_4 &pcfg_pull_none>,
1473 <3 2 RK_FUNC_2 &pcfg_pull_none>;