2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/clock/rk3328-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
14 compatible = "rockchip,rk3328";
16 interrupt-parent = <&gic>;
36 compatible = "arm,cortex-a53", "arm,armv8";
38 enable-method = "psci";
39 // clocks = <&cru ARMCLK>;
40 operating-points-v2 = <&cpu0_opp_table>;
44 compatible = "arm,cortex-a53", "arm,armv8";
46 enable-method = "psci";
50 compatible = "arm,cortex-a53", "arm,armv8";
52 enable-method = "psci";
56 compatible = "arm,cortex-a53", "arm,armv8";
58 enable-method = "psci";
62 cpu0_opp_table: opp_table0 {
63 compatible = "operating-points-v2";
67 opp-hz = /bits/ 64 <408000000>;
68 opp-microvolt = <950000>;
69 clock-latency-ns = <40000>;
73 opp-hz = /bits/ 64 <600000000>;
74 opp-microvolt = <950000>;
75 clock-latency-ns = <40000>;
78 opp-hz = /bits/ 64 <816000000>;
79 opp-microvolt = <1000000>;
80 clock-latency-ns = <40000>;
83 opp-hz = /bits/ 64 <1008000000>;
84 opp-microvolt = <1100000>;
85 clock-latency-ns = <40000>;
88 opp-hz = /bits/ 64 <1200000000>;
89 opp-microvolt = <1225000>;
90 clock-latency-ns = <40000>;
93 opp-hz = /bits/ 64 <1296000000>;
94 opp-microvolt = <1300000>;
95 clock-latency-ns = <40000>;
100 compatible = "arm,cortex-a53-pmu";
101 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
105 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
109 compatible = "arm,psci-1.0";
114 compatible = "arm,armv8-timer";
115 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
116 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
117 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
118 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
122 compatible = "fixed-clock";
124 clock-frequency = <24000000>;
125 clock-output-names = "xin24m";
129 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
130 reg = <0x0 0xff000000 0x0 0x1000>;
131 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
132 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
133 clock-names = "i2s_clk", "i2s_hclk";
134 dmas = <&dmac 11>, <&dmac 12>;
136 dma-names = "tx", "rx";
141 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
142 reg = <0x0 0xff010000 0x0 0x1000>;
143 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
145 clock-names = "i2s_clk", "i2s_hclk";
146 dmas = <&dmac 14>, <&dmac 15>;
148 dma-names = "tx", "rx";
153 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
154 reg = <0x0 0xff020000 0x0 0x1000>;
155 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
157 clock-names = "i2s_clk", "i2s_hclk";
158 dmas = <&dmac 0>, <&dmac 1>;
160 dma-names = "tx", "rx";
161 pinctrl-names = "default", "sleep";
162 pinctrl-0 = <&i2s2m0_mclk
168 pinctrl-1 = <&i2s2m0_sleep>;
172 spdif: spdif@ff030000 {
173 compatible = "rockchip,rk3328-spdif";
174 reg = <0x0 0xff030000 0x0 0x1000>;
175 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
177 clock-names = "mclk", "hclk";
181 pinctrl-names = "default";
182 pinctrl-0 = <&spdifm2_tx>;
186 grf: syscon@ff100000 {
187 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
188 reg = <0x0 0xff100000 0x0 0x1000>;
189 #address-cells = <1>;
192 io_domains: io-domains {
193 compatible = "rockchip,rk3328-io-voltage-domain";
198 uart0: serial@ff110000 {
199 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
200 reg = <0x0 0xff110000 0x0 0x100>;
201 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
203 clock-names = "baudclk", "apb_pclk";
206 dmas = <&dmac 2>, <&dmac 3>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
213 uart1: serial@ff120000 {
214 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
215 reg = <0x0 0xff120000 0x0 0x100>;
216 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
218 clock-names = "sclk_uart", "pclk_uart";
221 dmas = <&dmac 4>, <&dmac 5>;
223 pinctrl-names = "default";
224 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
228 uart2: serial@ff130000 {
229 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
230 reg = <0x0 0xff130000 0x0 0x100>;
231 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
233 clock-names = "baudclk", "apb_pclk";
234 clock-frequency = <24000000>;
237 dmas = <&dmac 6>, <&dmac 7>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&uart2m1_xfer>;
244 pmu: power-management@ff140000 {
245 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
246 reg = <0x0 0xff140000 0x0 0x1000>;
250 compatible = "rockchip,rk3328-i2c";
251 reg = <0x0 0xff150000 0x0 0x1000>;
252 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
253 #address-cells = <1>;
255 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
256 clock-names = "i2c", "pclk";
257 pinctrl-names = "default";
258 pinctrl-0 = <&i2c0_xfer>;
263 compatible = "rockchip,rk3328-i2c";
264 reg = <0x0 0xff160000 0x0 0x1000>;
265 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
266 #address-cells = <1>;
268 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
269 clock-names = "i2c", "pclk";
270 pinctrl-names = "default";
271 pinctrl-0 = <&i2c1_xfer>;
276 compatible = "rockchip,rk3328-i2c";
277 reg = <0x0 0xff170000 0x0 0x1000>;
278 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
279 #address-cells = <1>;
281 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
282 clock-names = "i2c", "pclk";
283 pinctrl-names = "default";
284 pinctrl-0 = <&i2c2_xfer>;
289 compatible = "rockchip,rk3328-i2c";
290 reg = <0x0 0xff180000 0x0 0x1000>;
291 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
292 #address-cells = <1>;
294 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
295 clock-names = "i2c", "pclk";
296 pinctrl-names = "default";
297 pinctrl-0 = <&i2c3_xfer>;
302 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
303 reg = <0x0 0xff190000 0x0 0x1000>;
304 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
305 #address-cells = <1>;
307 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
308 clock-names = "spiclk", "apb_pclk";
309 dmas = <&dmac 8>, <&dmac 9>;
311 dma-names = "tx", "rx";
312 pinctrl-names = "default";
313 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
317 wdt: watchdog@ff1a0000 {
318 compatible = "snps,dw-wdt";
319 reg = <0x0 0xff1a0000 0x0 0x100>;
320 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
325 compatible = "simple-bus";
326 #address-cells = <2>;
330 dmac: dmac@ff1f0000 {
331 compatible = "arm,pl330", "arm,primecell";
332 reg = <0x0 0xff1f0000 0x0 0x4000>;
333 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&cru ACLK_DMAC>;
336 clock-names = "apb_pclk";
341 saradc: saradc@ff280000 {
342 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
343 reg = <0x0 0xff280000 0x0 0x100>;
344 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
345 #io-channel-cells = <1>;
346 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
347 clock-names = "saradc", "apb_pclk";
348 resets = <&cru SRST_SARADC_P>;
349 reset-names = "saradc-apb";
353 cru: clock-controller@ff440000 {
354 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
355 reg = <0x0 0xff440000 0x0 0x1000>;
356 rockchip,grf = <&grf>;
360 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
361 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
362 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
363 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
364 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
365 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
366 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
367 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
368 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
369 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
370 <&cru SCLK_WIFI>, <&cru ARMCLK>,
371 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
372 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
373 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
374 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
375 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
376 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
377 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
378 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
379 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
380 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
381 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
382 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
383 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
384 assigned-clock-parents =
385 <&cru HDMIPHY>, <&cru PLL_APLL>,
386 <&cru PLL_GPLL>, <&xin24m>,
387 <&xin24m>, <&xin24m>;
388 assigned-clock-rates =
391 <24000000>, <24000000>,
392 <15000000>, <15000000>,
393 <100000000>, <100000000>,
394 <100000000>, <100000000>,
395 <50000000>, <100000000>,
396 <100000000>, <100000000>,
397 <50000000>, <50000000>,
398 <50000000>, <50000000>,
399 <24000000>, <600000000>,
400 <491520000>, <1200000000>,
401 <150000000>, <75000000>,
402 <75000000>, <150000000>,
403 <75000000>, <75000000>,
404 <300000000>, <100000000>,
405 <300000000>, <200000000>,
406 <400000000>, <500000000>,
407 <200000000>, <300000000>,
408 <300000000>, <250000000>,
409 <200000000>, <100000000>,
410 <24000000>, <100000000>,
411 <150000000>, <50000000>,
415 sdmmc: rksdmmc@ff500000 {
416 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
417 reg = <0x0 0xff500000 0x0 0x4000>;
418 clock-freq-min-max = <400000 150000000>;
419 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
420 clock-names = "biu", "ciu";
421 fifo-depth = <0x100>;
422 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
426 sdio: dwmmc@ff510000 {
427 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
428 reg = <0x0 0xff510000 0x0 0x4000>;
429 clock-freq-min-max = <400000 150000000>;
430 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
431 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
432 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
433 fifo-depth = <0x100>;
434 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
438 emmc: rksdmmc@ff520000 {
439 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
440 reg = <0x0 0xff520000 0x0 0x4000>;
441 clock-freq-min-max = <400000 150000000>;
442 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
443 clock-names = "biu", "ciu";
444 fifo-depth = <0x100>;
445 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
449 usb_host0_ehci: usb@ff5c0000 {
450 compatible = "generic-ehci";
451 reg = <0x0 0xff5c0000 0x0 0x10000>;
452 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
456 usb_host0_ohci: usb@ff5d0000 {
457 compatible = "generic-ohci";
458 reg = <0x0 0xff5d0000 0x0 0x10000>;
459 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
463 sdmmc_ext: rksdmmc@ff5f0000 {
464 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
465 reg = <0x0 0xff5f0000 0x0 0x4000>;
466 clock-freq-min-max = <400000 150000000>;
467 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
468 clock-names = "biu", "ciu";
469 fifo-depth = <0x100>;
470 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
474 usb_host0_xhci: usb@ff600000 {
475 compatible = "rockchip,rk3328-xhci";
476 reg = <0x0 0xff600000 0x0 0x100000>;
477 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
478 snps,dis-enblslpm-quirk;
479 snps,phyif-utmi-bits = <16>;
480 snps,dis-u2-freeclk-exists-quirk;
481 snps,dis-u2-susphy-quirk;
485 gic: interrupt-controller@ffb70000 {
486 compatible = "arm,gic-400";
487 #interrupt-cells = <3>;
488 #address-cells = <0>;
489 interrupt-controller;
490 reg = <0x0 0xff811000 0 0x1000>,
491 <0x0 0xff812000 0 0x2000>,
492 <0x0 0xff814000 0 0x2000>,
493 <0x0 0xff816000 0 0x2000>;
494 interrupts = <GIC_PPI 9
495 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
499 compatible = "rockchip,rk3328-pinctrl";
500 rockchip,grf = <&grf>;
501 #address-cells = <2>;
505 gpio0: gpio0@ff210000 {
506 compatible = "rockchip,gpio-bank";
507 reg = <0x0 0xff210000 0x0 0x100>;
508 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&cru PCLK_GPIO0>;
514 interrupt-controller;
515 #interrupt-cells = <2>;
518 gpio1: gpio1@ff220000 {
519 compatible = "rockchip,gpio-bank";
520 reg = <0x0 0xff220000 0x0 0x100>;
521 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&cru PCLK_GPIO1>;
527 interrupt-controller;
528 #interrupt-cells = <2>;
531 gpio2: gpio2@ff230000 {
532 compatible = "rockchip,gpio-bank";
533 reg = <0x0 0xff230000 0x0 0x100>;
534 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&cru PCLK_GPIO2>;
540 interrupt-controller;
541 #interrupt-cells = <2>;
544 gpio3: gpio3@ff240000 {
545 compatible = "rockchip,gpio-bank";
546 reg = <0x0 0xff240000 0x0 0x100>;
547 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&cru PCLK_GPIO3>;
553 interrupt-controller;
554 #interrupt-cells = <2>;
557 pcfg_pull_up: pcfg-pull-up {
561 pcfg_pull_down: pcfg-pull-down {
565 pcfg_pull_none: pcfg-pull-none {
569 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
571 drive-strength = <2>;
574 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
576 drive-strength = <2>;
579 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
581 drive-strength = <4>;
584 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
586 drive-strength = <4>;
589 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
591 drive-strength = <4>;
594 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
596 drive-strength = <8>;
599 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
601 drive-strength = <8>;
604 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
606 drive-strength = <12>;
609 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
611 drive-strength = <12>;
614 pcfg_output_high: pcfg-output-high {
618 pcfg_output_low: pcfg-output-low {
622 pcfg_input_high: pcfg-input-high {
627 pcfg_input: pcfg-input {
632 i2c0_xfer: i2c0-xfer {
634 <2 24 RK_FUNC_1 &pcfg_pull_none>,
635 <2 25 RK_FUNC_1 &pcfg_pull_none>;
640 i2c1_xfer: i2c1-xfer {
642 <2 4 RK_FUNC_2 &pcfg_pull_none>,
643 <2 5 RK_FUNC_2 &pcfg_pull_none>;
648 i2c2_xfer: i2c2-xfer {
650 <2 13 RK_FUNC_1 &pcfg_pull_none>,
651 <2 14 RK_FUNC_1 &pcfg_pull_none>;
656 i2c3_xfer: i2c3-xfer {
658 <0 5 RK_FUNC_2 &pcfg_pull_none>,
659 <0 6 RK_FUNC_2 &pcfg_pull_none>;
661 i2c3_gpio: i2c3-gpio {
663 <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
664 <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
669 hdmii2c_xfer: hdmii2c-xfer {
671 <0 5 RK_FUNC_1 &pcfg_pull_none>,
672 <0 6 RK_FUNC_1 &pcfg_pull_none>;
677 uart0_xfer: uart0-xfer {
679 <1 9 RK_FUNC_1 &pcfg_pull_up>,
680 <1 8 RK_FUNC_1 &pcfg_pull_none>;
683 uart0_cts: uart0-cts {
685 <1 11 RK_FUNC_1 &pcfg_pull_none>;
688 uart0_rts: uart0-rts {
690 <1 10 RK_FUNC_1 &pcfg_pull_none>;
693 uart0_rts_gpio: uart0-rts-gpio {
695 <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
700 uart1_xfer: uart1-xfer {
702 <3 4 RK_FUNC_4 &pcfg_pull_up>,
703 <3 6 RK_FUNC_4 &pcfg_pull_none>;
706 uart1_cts: uart1-cts {
708 <3 7 RK_FUNC_4 &pcfg_pull_none>;
711 uart1_rts: uart1-rts {
713 <3 5 RK_FUNC_4 &pcfg_pull_none>;
716 uart1_rts_gpio: uart1-rts-gpio {
718 <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
723 uart2m0_xfer: uart2m0-xfer {
725 <1 0 RK_FUNC_2 &pcfg_pull_up>,
726 <1 1 RK_FUNC_2 &pcfg_pull_none>;
731 uart2m1_xfer: uart2m1-xfer {
733 <2 0 RK_FUNC_1 &pcfg_pull_up>,
734 <2 1 RK_FUNC_1 &pcfg_pull_none>;
739 spi0m0_clk: spi0m0-clk {
741 <2 8 RK_FUNC_1 &pcfg_pull_up>;
744 spi0m0_cs0: spi0m0-cs0 {
746 <2 11 RK_FUNC_1 &pcfg_pull_up>;
749 spi0m0_tx: spi0m0-tx {
751 <2 9 RK_FUNC_1 &pcfg_pull_up>;
754 spi0m0_rx: spi0m0-rx {
756 <2 10 RK_FUNC_1 &pcfg_pull_up>;
759 spi0m0_cs1: spi0m0-cs1 {
761 <2 12 RK_FUNC_1 &pcfg_pull_up>;
766 spi0m1_clk: spi0m1-clk {
768 <3 23 RK_FUNC_2 &pcfg_pull_up>;
771 spi0m1_cs0: spi0m1-cs0 {
773 <3 26 RK_FUNC_2 &pcfg_pull_up>;
776 spi0m1_tx: spi0m1-tx {
778 <3 25 RK_FUNC_2 &pcfg_pull_up>;
781 spi0m1_rx: spi0m1-rx {
783 <3 24 RK_FUNC_2 &pcfg_pull_up>;
786 spi0m1_cs1: spi0m1-cs1 {
788 <3 27 RK_FUNC_2 &pcfg_pull_up>;
793 spi0m2_clk: spi0m2-clk {
795 <3 0 RK_FUNC_4 &pcfg_pull_up>;
798 spi0m2_cs0: spi0m2-cs0 {
800 <3 8 RK_FUNC_3 &pcfg_pull_up>;
803 spi0m2_tx: spi0m2-tx {
805 <3 1 RK_FUNC_4 &pcfg_pull_up>;
808 spi0m2_rx: spi0m2-rx {
810 <3 2 RK_FUNC_4 &pcfg_pull_up>;
815 i2s1_mclk: i2s1-mclk {
817 <2 15 RK_FUNC_1 &pcfg_pull_none>;
820 i2s1_sclk: i2s1-sclk {
822 <2 18 RK_FUNC_1 &pcfg_pull_none>;
825 i2s1_lrckrx: i2s1-lrckrx {
827 <2 16 RK_FUNC_1 &pcfg_pull_none>;
830 i2s1_lrcktx: i2s1-lrcktx {
832 <2 17 RK_FUNC_1 &pcfg_pull_none>;
837 <2 19 RK_FUNC_1 &pcfg_pull_none>;
842 <2 23 RK_FUNC_1 &pcfg_pull_none>;
845 i2s1_sdio1: i2s1-sdio1 {
847 <2 20 RK_FUNC_1 &pcfg_pull_none>;
850 i2s1_sdio2: i2s1-sdio2 {
852 <2 21 RK_FUNC_1 &pcfg_pull_none>;
855 i2s1_sdio3: i2s1-sdio3 {
857 <2 22 RK_FUNC_1 &pcfg_pull_none>;
860 i2s1_sleep: i2s1-sleep {
862 <2 15 RK_FUNC_GPIO &pcfg_input_high>,
863 <2 16 RK_FUNC_GPIO &pcfg_input_high>,
864 <2 17 RK_FUNC_GPIO &pcfg_input_high>,
865 <2 18 RK_FUNC_GPIO &pcfg_input_high>,
866 <2 19 RK_FUNC_GPIO &pcfg_input_high>,
867 <2 20 RK_FUNC_GPIO &pcfg_input_high>,
868 <2 21 RK_FUNC_GPIO &pcfg_input_high>,
869 <2 22 RK_FUNC_GPIO &pcfg_input_high>,
870 <2 23 RK_FUNC_GPIO &pcfg_input_high>;
875 i2s2m0_mclk: i2s2m0-mclk {
877 <1 21 RK_FUNC_1 &pcfg_pull_none>;
880 i2s2m0_sclk: i2s2m0-sclk {
882 <1 22 RK_FUNC_1 &pcfg_pull_none>;
885 i2s2m0_lrckrx: i2s2m0-lrckrx {
887 <1 26 RK_FUNC_1 &pcfg_pull_none>;
890 i2s2m0_lrcktx: i2s2m0-lrcktx {
892 <1 23 RK_FUNC_1 &pcfg_pull_none>;
895 i2s2m0_sdi: i2s2m0-sdi {
897 <1 24 RK_FUNC_1 &pcfg_pull_none>;
900 i2s2m0_sdo: i2s2m0-sdo {
902 <1 25 RK_FUNC_1 &pcfg_pull_none>;
905 i2s2m0_sleep: i2s2m0-sleep {
907 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
908 <1 22 RK_FUNC_GPIO &pcfg_input_high>,
909 <1 26 RK_FUNC_GPIO &pcfg_input_high>,
910 <1 23 RK_FUNC_GPIO &pcfg_input_high>,
911 <1 24 RK_FUNC_GPIO &pcfg_input_high>,
912 <1 25 RK_FUNC_GPIO &pcfg_input_high>;
917 i2s2m1_mclk: i2s2m1-mclk {
919 <1 21 RK_FUNC_1 &pcfg_pull_none>;
922 i2s2m1_sclk: i2s2m1-sclk {
924 <3 0 RK_FUNC_6 &pcfg_pull_none>;
927 i2s2m1_lrckrx: i2sm1-lrckrx {
929 <3 8 RK_FUNC_6 &pcfg_pull_none>;
932 i2s2m1_lrcktx: i2s2m1-lrcktx {
934 <3 8 RK_FUNC_4 &pcfg_pull_none>;
937 i2s2m1_sdi: i2s2m1-sdi {
939 <3 2 RK_FUNC_6 &pcfg_pull_none>;
942 i2s2m1_sdo: i2s2m1-sdo {
944 <3 1 RK_FUNC_6 &pcfg_pull_none>;
947 i2s2m1_sleep: i2s2m1-sleep {
949 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
950 <3 0 RK_FUNC_GPIO &pcfg_input_high>,
951 <3 8 RK_FUNC_GPIO &pcfg_input_high>,
952 <3 2 RK_FUNC_GPIO &pcfg_input_high>,
953 <3 1 RK_FUNC_GPIO &pcfg_input_high>;
958 spdifm0_tx: spdifm0-tx {
960 <0 27 RK_FUNC_1 &pcfg_pull_none>;
965 spdifm1_tx: spdifm1-tx {
967 <2 17 RK_FUNC_2 &pcfg_pull_none>;
972 spdifm2_tx: spdifm2-tx {
974 <0 2 RK_FUNC_2 &pcfg_pull_none>;
979 sdmmc0m0_pwren: sdmmc0m0-pwren {
981 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
984 sdmmc0m0_gpio: sdmmc0m0-gpio {
986 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
991 sdmmc0m1_pwren: sdmmc0m1-pwren {
993 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
996 sdmmc0m1_gpio: sdmmc0m1-gpio {
998 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1003 sdmmc0_clk: sdmmc0-clk {
1005 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1008 sdmmc0_cmd: sdmmc0-cmd {
1010 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1013 sdmmc0_dectn: sdmmc0-dectn {
1015 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1018 sdmmc0_wrprt: sdmmc0-wrprt {
1020 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1023 sdmmc0_bus1: sdmmc0-bus1 {
1025 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1028 sdmmc0_bus4: sdmmc0-bus4 {
1030 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1031 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1032 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1033 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1036 sdmmc0_gpio: sdmmc0-gpio {
1038 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1039 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1040 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1041 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1042 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1043 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1044 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1045 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1050 sdmmc0ext_clk: sdmmc0ext-clk {
1052 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1055 sdmmc0ext_cmd: sdmmc0ext-cmd {
1057 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1060 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1062 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1065 sdmmc0ext_dectn: sdmmc0ext-dectn {
1067 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1070 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1072 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1075 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1077 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1078 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1079 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1080 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1083 sdmmc0ext_gpio: sdmmc0ext-gpio {
1085 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1086 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1087 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1088 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1089 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1090 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1091 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1092 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1097 sdmmc1_clk: sdmmc1-clk {
1099 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1102 sdmmc1_cmd: sdmmc1-cmd {
1104 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1107 sdmmc1_pwren: sdmmc1-pwren {
1109 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1112 sdmmc1_wrprt: sdmmc1-wrprt {
1114 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1117 sdmmc1_dectn: sdmmc1-dectn {
1119 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1122 sdmmc1_bus1: sdmmc1-bus1 {
1124 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1127 sdmmc1_bus4: sdmmc1-bus4 {
1129 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1130 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1131 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1132 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1135 sdmmc1_gpio: sdmmc1-gpio {
1137 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1138 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1139 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1140 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1141 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1142 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1143 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1144 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1145 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1150 emmc_clk: emmc-clk {
1152 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1155 emmc_cmd: emmc-cmd {
1157 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1160 emmc_pwren: emmc-pwren {
1162 <3 22 RK_FUNC_2 &pcfg_pull_none>;
1165 emmc_rstnout: emmc-rstnout {
1167 <3 20 RK_FUNC_2 &pcfg_pull_none>;
1170 emmc_bus1: emmc-bus1 {
1172 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1175 emmc_bus4: emmc-bus4 {
1177 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1178 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1179 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1180 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1183 emmc_bus8: emmc-bus8 {
1185 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1186 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1187 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1188 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1189 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1190 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1191 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1192 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1197 pwm0_pin: pwm0-pin {
1199 <2 4 RK_FUNC_1 &pcfg_pull_none>;
1204 pwm1_pin: pwm1-pin {
1206 <2 5 RK_FUNC_1 &pcfg_pull_none>;
1211 pwm2_pin: pwm2-pin {
1213 <2 6 RK_FUNC_1 &pcfg_pull_none>;
1218 pwmir_pin: pwmir-pin {
1220 <2 2 RK_FUNC_1 &pcfg_pull_none>;
1225 rgmiim0_pins: rgmiim0-pins {
1228 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1230 <0 10 RK_FUNC_1 &pcfg_pull_none>,
1232 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1234 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1236 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1238 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1240 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1242 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1244 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1246 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1248 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1250 <0 20 RK_FUNC_1 &pcfg_pull_none>,
1252 <0 21 RK_FUNC_1 &pcfg_pull_none>,
1254 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1256 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1259 rmiim0_pins: rmiim0-pins {
1262 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1264 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1266 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1268 <0 13 RK_FUNC_1 &pcfg_pull_none>,
1270 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1272 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1274 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1276 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1278 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1280 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1285 rgmiim1_pins: rgmiim1-pins {
1288 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1290 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1292 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1294 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1296 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1298 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1300 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1302 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1304 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1306 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1308 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1310 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1312 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1314 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1316 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1319 <0 8 RK_FUNC_1 &pcfg_pull_none>,
1321 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1323 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1325 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1327 <0 17 RK_FUNC_1 &pcfg_pull_none>,
1329 <0 23 RK_FUNC_1 &pcfg_pull_none>,
1331 <0 22 RK_FUNC_1 &pcfg_pull_none>;
1334 rmiim1_pins: rmiim1-pins {
1337 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1339 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1341 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1343 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1345 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1347 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1349 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1351 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1353 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1355 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1358 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1360 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1362 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1364 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1366 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1368 <0 17 RK_FUNC_1 &pcfg_pull_none>;
1373 fephyled_speed100: fephyled-speed100 {
1375 <0 31 RK_FUNC_1 &pcfg_pull_none>;
1378 fephyled_speed10: fephyled-speed10 {
1380 <0 30 RK_FUNC_1 &pcfg_pull_none>;
1383 fephyled_duplex: fephyled-duplex {
1385 <0 30 RK_FUNC_2 &pcfg_pull_none>;
1388 fephyled_rxm0: fephyled-rxm0 {
1390 <0 29 RK_FUNC_1 &pcfg_pull_none>;
1393 fephyled_txm0: fephyled-txm0 {
1395 <0 29 RK_FUNC_2 &pcfg_pull_none>;
1398 fephyled_linkm0: fephyled-linkm0 {
1400 <0 28 RK_FUNC_1 &pcfg_pull_none>;
1403 fephyled_rxm1: fephyled-rxm1 {
1405 <2 25 RK_FUNC_2 &pcfg_pull_none>;
1408 fephyled_txm1: fephyled-txm1 {
1410 <2 25 RK_FUNC_3 &pcfg_pull_none>;
1413 fephyled_linkm1: fephyled-linkm1 {
1415 <2 24 RK_FUNC_2 &pcfg_pull_none>;
1420 tsadc_int: tsadc-int {
1422 <2 13 RK_FUNC_2 &pcfg_pull_none>;
1424 tsadc_gpio: tsadc-gpio {
1426 <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1431 hdmi_cec: hdmi-cec {
1433 <0 3 RK_FUNC_1 &pcfg_pull_none>;
1436 hdmi_hpd: hdmi-hpd {
1438 <0 4 RK_FUNC_1 &pcfg_pull_down>;
1443 dvp_d2d9_m0:dvp-d2d9-m0 {
1446 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1448 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1450 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1452 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1454 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1456 <3 9 RK_FUNC_2 &pcfg_pull_none>,
1458 <3 10 RK_FUNC_2 &pcfg_pull_none>,
1460 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1462 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1464 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1466 <3 3 RK_FUNC_2 &pcfg_pull_none>,
1468 <3 2 RK_FUNC_2 &pcfg_pull_none>;
1473 dvp_d2d9_m1:dvp-d2d9-m1 {
1476 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1478 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1480 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1482 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1484 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1486 <2 16 RK_FUNC_4 &pcfg_pull_none>,
1488 <2 17 RK_FUNC_4 &pcfg_pull_none>,
1490 <2 18 RK_FUNC_4 &pcfg_pull_none>,
1492 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1494 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1496 <2 15 RK_FUNC_4 &pcfg_pull_none>,
1498 <3 2 RK_FUNC_2 &pcfg_pull_none>;