2 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
4 * SPDX-License-Identifier: GPL-2.0+ X11
9 u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
10 u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
14 stdout-path = "serial0:115200n8";
15 u-boot,spl-boot-order = &emmc, &sdmmc;
16 tick-timer = "/timer@ff810000";
33 * Validation of throughput using SPEC2000 shows the following
34 * relative performance for the different memory schedules:
38 * Note that the best performance for any given application workload
39 * may vary from the default configured here (e.g. 164.gzip is fastest
40 * with CBRD, whereas 252.eon and 186.crafty are fastest with CRBD).
42 * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
43 * details on the 'rockchip,memory-schedule' property and how it
44 * affects the physical-address to device-address mapping.
46 rockchip,memory-schedule = <DMC_MSCH_CBDR>;
47 rockchip,ddr-frequency = <800000000>;
48 rockchip,ddr-speed-bin = <DDR3_1600K>;
84 spiflash: w25q32dw@0 {
91 clock-frequency = <24000000>;