git.sur5r.net Git - u-boot/blob - arch/arm/dts/rk3399.dtsi

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <dt-bindings/clock/rk3399-cru.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/pinctrl/rockchip.h>
  12 #define USB_CLASS_HUB                   9
  13
  14 / {
  15         compatible = "rockchip,rk3399";
  16
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 serial0 = &uart0;
  23                 serial1 = &uart1;
  24                 serial2 = &uart2;
  25                 serial3 = &uart3;
  26                 serial4 = &uart4;
  27         };
  28
  29         cpus {
  30                 #address-cells = <2>;
  31                 #size-cells = <0>;
  32
  33                 cpu-map {
  34                         cluster0 {
  35                                 core0 {
  36                                         cpu = <&cpu_l0>;
  37                                 };
  38                                 core1 {
  39                                         cpu = <&cpu_l1>;
  40                                 };
  41                                 core2 {
  42                                         cpu = <&cpu_l2>;
  43                                 };
  44                                 core3 {
  45                                         cpu = <&cpu_l3>;
  46                                 };
  47                         };
  48
  49                         cluster1 {
  50                                 core0 {
  51                                         cpu = <&cpu_b0>;
  52                                 };
  53                                 core1 {
  54                                         cpu = <&cpu_b1>;
  55                                 };
  56                         };
  57                 };
  58
  59                 cpu_l0: cpu@0 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a53", "arm,armv8";
  62                         reg = <0x0 0x0>;
  63                         enable-method = "psci";
  64                         #cooling-cells = <2>; /* min followed by max */
  65                         clocks = <&cru ARMCLKL>;
  66                 };
  67
  68                 cpu_l1: cpu@1 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a53", "arm,armv8";
  71                         reg = <0x0 0x1>;
  72                         enable-method = "psci";
  73                         clocks = <&cru ARMCLKL>;
  74                 };
  75
  76                 cpu_l2: cpu@2 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a53", "arm,armv8";
  79                         reg = <0x0 0x2>;
  80                         enable-method = "psci";
  81                         clocks = <&cru ARMCLKL>;
  82                 };
  83
  84                 cpu_l3: cpu@3 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a53", "arm,armv8";
  87                         reg = <0x0 0x3>;
  88                         enable-method = "psci";
  89                         clocks = <&cru ARMCLKL>;
  90                 };
  91
  92                 cpu_b0: cpu@100 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a72", "arm,armv8";
  95                         reg = <0x0 0x100>;
  96                         enable-method = "psci";
  97                         #cooling-cells = <2>; /* min followed by max */
  98                         clocks = <&cru ARMCLKB>;
  99                 };
 100
 101                 cpu_b1: cpu@101 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a72", "arm,armv8";
 104                         reg = <0x0 0x101>;
 105                         enable-method = "psci";
 106                         clocks = <&cru ARMCLKB>;
 107                 };
 108         };
 109
 110         psci {
 111                 compatible = "arm,psci-1.0";
 112                 method = "smc";
 113         };
 114
 115         timer {
 116                 compatible = "arm,armv8-timer";
 117                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 118                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 119                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 120                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 121         };
 122
 123         xin24m: xin24m {
 124                 compatible = "fixed-clock";
 125                 clock-frequency = <24000000>;
 126                 clock-output-names = "xin24m";
 127                 #clock-cells = <0>;
 128         };
 129
 130         amba {
 131                 compatible = "simple-bus";
 132                 #address-cells = <2>;
 133                 #size-cells = <2>;
 134                 ranges;
 135
 136                 dmac_bus: dma-controller@ff6d0000 {
 137                         compatible = "arm,pl330", "arm,primecell";
 138                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 139                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 140                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 141                         #dma-cells = <1>;
 142                         clocks = <&cru ACLK_DMAC0_PERILP>;
 143                         clock-names = "apb_pclk";
 144                 };
 145
 146                 dmac_peri: dma-controller@ff6e0000 {
 147                         compatible = "arm,pl330", "arm,primecell";
 148                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 149                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 150                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 151                         #dma-cells = <1>;
 152                         clocks = <&cru ACLK_DMAC1_PERILP>;
 153                         clock-names = "apb_pclk";
 154                 };
 155         };
 156
 157         sdio0: dwmmc@fe310000 {
 158                 compatible = "rockchip,rk3399-dw-mshc",
 159                              "rockchip,rk3288-dw-mshc";
 160                 reg = <0x0 0xfe310000 0x0 0x4000>;
 161                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 162                 clock-freq-min-max = <400000 150000000>;
 163                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 164                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 165                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 166                 fifo-depth = <0x100>;
 167                 status = "disabled";
 168         };
 169
 170         sdmmc: dwmmc@fe320000 {
 171                 compatible = "rockchip,rk3399-dw-mshc",
 172                              "rockchip,rk3288-dw-mshc";
 173                 reg = <0x0 0xfe320000 0x0 0x4000>;
 174                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 175                 clock-freq-min-max = <400000 150000000>;
 176                 clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>,
 177                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 178                 clock-names = "ciu", "biu", "ciu-drive", "ciu-sample";
 179                 pinctrl-names = "default";
 180                 pinctrl-0 = <&sdmmc_clk>;
 181                 fifo-depth = <0x100>;
 182                 status = "disabled";
 183         };
 184
 185         sdhci: sdhci@fe330000 {
 186                 u-boot,dm-pre-reloc;
 187                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 188                 reg = <0x0 0xfe330000 0x0 0x10000>;
 189                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 190                 assigned-clocks = <&cru SCLK_EMMC>;
 191                 assigned-clock-rates = <200000000>;
 192                 max-frequency = <200000000>;
 193                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 194                 clock-names = "clk_xin", "clk_ahb";
 195                 phys = <&emmc_phy>;
 196                 phy-names = "phy_arasan";
 197                 status = "disabled";
 198         };
 199
 200         usb_host0_ehci: usb@fe380000 {
 201                 compatible = "generic-ehci";
 202                 reg = <0x0 0xfe380000 0x0 0x20000>;
 203                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 204                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 205                 clock-names = "hclk_host0", "hclk_host0_arb";
 206                 status = "disabled";
 207         };
 208
 209         usb_host0_ohci: usb@fe3a0000 {
 210                 compatible = "generic-ohci";
 211                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 212                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 213                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 214                 clock-names = "hclk_host0", "hclk_host0_arb";
 215                 status = "disabled";
 216         };
 217
 218         usb_host1_ehci: usb@fe3c0000 {
 219                 compatible = "generic-ehci";
 220                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 221                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 222                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 223                 clock-names = "hclk_host1", "hclk_host1_arb";
 224                 status = "disabled";
 225         };
 226
 227         usb_host1_ohci: usb@fe3e0000 {
 228                 compatible = "generic-ohci";
 229                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 230                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 231                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 232                 clock-names = "hclk_host1", "hclk_host1_arb";
 233                 status = "disabled";
 234         };
 235
 236         dwc3_typec0: usb@fe800000 {
 237                 compatible = "rockchip,rk3399-xhci";
 238                 reg = <0x0 0xfe800000 0x0 0x100000>;
 239                 status = "disabled";
 240                 rockchip,vbus-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
 241                 snps,dis-enblslpm-quirk;
 242                 snps,phyif-utmi-bits = <16>;
 243                 snps,dis-u2-freeclk-exists-quirk;
 244                 snps,dis-u2-susphy-quirk;
 245
 246                 #address-cells = <2>;
 247                 #size-cells = <2>;
 248                 hub {
 249                         compatible = "usb-hub";
 250                         usb,device-class = <USB_CLASS_HUB>;
 251                 };
 252                 typec_phy0 {
 253                         compatible = "rockchip,rk3399-usb3-phy";
 254                         reg = <0x0 0xff7c0000 0x0 0x40000>;
 255                 };
 256         };
 257
 258         dwc3_typec1: usb@fe900000 {
 259                 compatible = "rockchip,rk3399-xhci";
 260                 reg = <0x0 0xfe900000 0x0 0x100000>;
 261                 status = "disabled";
 262                 rockchip,vbus-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 263                 snps,dis-enblslpm-quirk;
 264                 snps,phyif-utmi-bits = <16>;
 265                 snps,dis-u2-freeclk-exists-quirk;
 266                 snps,dis-u2-susphy-quirk;
 267
 268                 #address-cells = <2>;
 269                 #size-cells = <2>;
 270                 hub {
 271                         compatible = "usb-hub";
 272                         usb,device-class = <USB_CLASS_HUB>;
 273                 };
 274                 typec_phy1 {
 275                         compatible = "rockchip,rk3399-usb3-phy";
 276                         reg = <0x0 0xff800000 0x0 0x40000>;
 277                 };
 278         };
 279
 280         gic: interrupt-controller@fee00000 {
 281                 compatible = "arm,gic-v3";
 282                 #interrupt-cells = <3>;
 283                 #address-cells = <2>;
 284                 #size-cells = <2>;
 285                 ranges;
 286                 interrupt-controller;
 287
 288                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 289                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 290                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 291                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 292                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 293                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 294                 its: interrupt-controller@fee20000 {
 295                         compatible = "arm,gic-v3-its";
 296                         msi-controller;
 297                         reg = <0x0 0xfee20000 0x0 0x20000>;
 298                 };
 299         };
 300
 301         uart0: serial@ff180000 {
 302                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 303                 reg = <0x0 0xff180000 0x0 0x100>;
 304                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 305                 clock-names = "baudclk", "apb_pclk";
 306                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 307                 reg-shift = <2>;
 308                 reg-io-width = <4>;
 309                 pinctrl-names = "default";
 310                 pinctrl-0 = <&uart0_xfer>;
 311                 status = "disabled";
 312         };
 313
 314         uart1: serial@ff190000 {
 315                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 316                 reg = <0x0 0xff190000 0x0 0x100>;
 317                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 318                 clock-names = "baudclk", "apb_pclk";
 319                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 320                 reg-shift = <2>;
 321                 reg-io-width = <4>;
 322                 pinctrl-names = "default";
 323                 pinctrl-0 = <&uart1_xfer>;
 324                 status = "disabled";
 325         };
 326
 327         uart2: serial@ff1a0000 {
 328                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 329                 reg = <0x0 0xff1a0000 0x0 0x100>;
 330                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 331                 clock-names = "baudclk", "apb_pclk";
 332                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 333                 clock-frequency = <24000000>;
 334                 reg-shift = <2>;
 335                 reg-io-width = <4>;
 336                 pinctrl-names = "default";
 337                 pinctrl-0 = <&uart2c_xfer>;
 338                 status = "disabled";
 339         };
 340
 341         uart3: serial@ff1b0000 {
 342                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 343                 reg = <0x0 0xff1b0000 0x0 0x100>;
 344                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 345                 clock-names = "baudclk", "apb_pclk";
 346                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 347                 reg-shift = <2>;
 348                 reg-io-width = <4>;
 349                 pinctrl-names = "default";
 350                 pinctrl-0 = <&uart3_xfer>;
 351                 status = "disabled";
 352         };
 353
 354         spi0: spi@ff1c0000 {
 355                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 356                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 357                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 358                 clock-names = "spiclk", "apb_pclk";
 359                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 360                 pinctrl-names = "default";
 361                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 362                 #address-cells = <1>;
 363                 #size-cells = <0>;
 364                 status = "disabled";
 365         };
 366
 367         spi1: spi@ff1d0000 {
 368                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 369                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 370                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 371                 clock-names = "spiclk", "apb_pclk";
 372                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 373                 pinctrl-names = "default";
 374                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377                 status = "disabled";
 378         };
 379
 380         spi2: spi@ff1e0000 {
 381                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 382                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 383                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 384                 clock-names = "spiclk", "apb_pclk";
 385                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 386                 pinctrl-names = "default";
 387                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 388                 #address-cells = <1>;
 389                 #size-cells = <0>;
 390                 status = "disabled";
 391         };
 392
 393         spi4: spi@ff1f0000 {
 394                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 395                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 396                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 397                 clock-names = "spiclk", "apb_pclk";
 398                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 399                 pinctrl-names = "default";
 400                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 401                 #address-cells = <1>;
 402                 #size-cells = <0>;
 403                 status = "disabled";
 404         };
 405
 406         spi5: spi@ff200000 {
 407                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 408                 reg = <0x0 0xff200000 0x0 0x1000>;
 409                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 410                 clock-names = "spiclk", "apb_pclk";
 411                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 412                 pinctrl-names = "default";
 413                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 414                 #address-cells = <1>;
 415                 #size-cells = <0>;
 416                 status = "disabled";
 417         };
 418
 419         pmugrf: syscon@ff320000 {
 420                 u-boot,dm-pre-reloc;
 421                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 422                 reg = <0x0 0xff320000 0x0 0x1000>;
 423                 #address-cells = <1>;
 424                 #size-cells = <1>;
 425
 426                 pmu_io_domains: io-domains {
 427                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
 428                         status = "disabled";
 429                 };
 430         };
 431
 432         pmusgrf: syscon@ff330000 {
 433                 u-boot,dm-pre-reloc;
 434                 compatible = "rockchip,rk3399-pmusgrf", "syscon";
 435                 reg = <0x0 0xff330000 0x0 0xe3d4>;
 436         };
 437
 438         spi3: spi@ff350000 {
 439                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 440                 reg = <0x0 0xff350000 0x0 0x1000>;
 441                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 442                 clock-names = "spiclk", "apb_pclk";
 443                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 444                 pinctrl-names = "default";
 445                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 446                 #address-cells = <1>;
 447                 #size-cells = <0>;
 448                 status = "disabled";
 449         };
 450
 451         uart4: serial@ff370000 {
 452                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 453                 reg = <0x0 0xff370000 0x0 0x100>;
 454                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 455                 clock-names = "baudclk", "apb_pclk";
 456                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 457                 reg-shift = <2>;
 458                 reg-io-width = <4>;
 459                 pinctrl-names = "default";
 460                 pinctrl-0 = <&uart4_xfer>;
 461                 status = "disabled";
 462         };
 463
 464         pwm0: pwm@ff420000 {
 465                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 466                 reg = <0x0 0xff420000 0x0 0x10>;
 467                 #pwm-cells = <3>;
 468                 pinctrl-names = "default";
 469                 pinctrl-0 = <&pwm0_pin>;
 470                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 471                 clock-names = "pwm";
 472                 status = "disabled";
 473         };
 474
 475         pwm1: pwm@ff420010 {
 476                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 477                 reg = <0x0 0xff420010 0x0 0x10>;
 478                 #pwm-cells = <3>;
 479                 pinctrl-names = "default";
 480                 pinctrl-0 = <&pwm1_pin>;
 481                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 482                 clock-names = "pwm";
 483                 status = "disabled";
 484         };
 485
 486         pwm2: pwm@ff420020 {
 487                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 488                 reg = <0x0 0xff420020 0x0 0x10>;
 489                 #pwm-cells = <3>;
 490                 pinctrl-names = "default";
 491                 pinctrl-0 = <&pwm2_pin>;
 492                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 493                 clock-names = "pwm";
 494                 status = "disabled";
 495         };
 496
 497         pwm3: pwm@ff420030 {
 498                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 499                 reg = <0x0 0xff420030 0x0 0x10>;
 500                 #pwm-cells = <3>;
 501                 pinctrl-names = "default";
 502                 pinctrl-0 = <&pwm3a_pin>;
 503                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 504                 clock-names = "pwm";
 505                 status = "disabled";
 506         };
 507
 508         cic: syscon@ff620000 {
 509                 u-boot,dm-pre-reloc;
 510                 compatible = "rockchip,rk3399-cic", "syscon";
 511                 reg = <0x0 0xff620000 0x0 0x100>;
 512         };
 513
 514         dfi: dfi@ff630000 {
 515                 reg = <0x00 0xff630000 0x00 0x4000>;
 516                 compatible = "rockchip,rk3399-dfi";
 517                 rockchip,pmu = <&pmugrf>;
 518                 clocks = <&cru PCLK_DDR_MON>;
 519                 clock-names = "pclk_ddr_mon";
 520                 status = "disabled";
 521         };
 522
 523         dmc: dmc {
 524                 u-boot,dm-pre-reloc;
 525                 compatible = "rockchip,rk3399-dmc";
 526                 devfreq-events = <&dfi>;
 527                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
 528                 clocks = <&cru SCLK_DDRCLK>;
 529                 clock-names = "dmc_clk";
 530                 reg = <0x0 0xffa80000 0x0 0x0800
 531                        0x0 0xffa80800 0x0 0x1800
 532                        0x0 0xffa82000 0x0 0x2000
 533                        0x0 0xffa84000 0x0 0x1000
 534                        0x0 0xffa88000 0x0 0x0800
 535                        0x0 0xffa88800 0x0 0x1800
 536                        0x0 0xffa8a000 0x0 0x2000
 537                        0x0 0xffa8c000 0x0 0x1000>;
 538         };
 539
 540         pmucru: pmu-clock-controller@ff750000 {
 541                 u-boot,dm-pre-reloc;
 542                 compatible = "rockchip,rk3399-pmucru";
 543                 reg = <0x0 0xff750000 0x0 0x1000>;
 544                 #clock-cells = <1>;
 545                 #reset-cells = <1>;
 546                 assigned-clocks = <&pmucru PLL_PPLL>;
 547                 assigned-clock-rates = <676000000>;
 548         };
 549
 550         cru: clock-controller@ff760000 {
 551                 u-boot,dm-pre-reloc;
 552                 compatible = "rockchip,rk3399-cru";
 553                 reg = <0x0 0xff760000 0x0 0x1000>;
 554                 #clock-cells = <1>;
 555                 #reset-cells = <1>;
 556                 assigned-clocks =
 557                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 558                         <&cru PLL_NPLL>,
 559                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 560                         <&cru PCLK_PERIHP>,
 561                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 562                         <&cru PCLK_PERILP0>,
 563                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 564                 assigned-clock-rates =
 565                          <594000000>,  <800000000>,
 566                         <1000000000>,
 567                          <150000000>,   <75000000>,
 568                           <37500000>,
 569                          <100000000>,  <100000000>,
 570                           <50000000>,
 571                          <100000000>,   <50000000>;
 572         };
 573
 574         grf: syscon@ff770000 {
 575                 u-boot,dm-pre-reloc;
 576                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
 577                 reg = <0x0 0xff770000 0x0 0x10000>;
 578                 #address-cells = <1>;
 579                 #size-cells = <1>;
 580
 581                 io_domains: io-domains {
 582                         compatible = "rockchip,rk3399-io-voltage-domain";
 583                         status = "disabled";
 584                 };
 585
 586                 emmc_phy: phy@f780 {
 587                         compatible = "rockchip,rk3399-emmc-phy";
 588                         reg = <0xf780 0x24>;
 589                         #phy-cells = <0>;
 590                         status = "disabled";
 591                 };
 592         };
 593
 594         watchdog@ff840000 {
 595                 compatible = "snps,dw-wdt";
 596                 reg = <0x0 0xff840000 0x0 0x100>;
 597                 clocks = <&cru PCLK_WDT>;
 598                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 599         };
 600
 601         spdif: spdif@ff870000 {
 602                 compatible = "rockchip,rk3399-spdif";
 603                 reg = <0x0 0xff870000 0x0 0x1000>;
 604                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 605                 dmas = <&dmac_bus 7>;
 606                 dma-names = "tx";
 607                 clock-names = "mclk", "hclk";
 608                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 609                 pinctrl-names = "default";
 610                 pinctrl-0 = <&spdif_bus>;
 611                 status = "disabled";
 612         };
 613
 614         i2s0: i2s@ff880000 {
 615                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 616                 reg = <0x0 0xff880000 0x0 0x1000>;
 617                 rockchip,grf = <&grf>;
 618                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 619                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 620                 dma-names = "tx", "rx";
 621                 clock-names = "i2s_clk", "i2s_hclk";
 622                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
 623                 pinctrl-names = "default";
 624                 pinctrl-0 = <&i2s0_8ch_bus>;
 625                 status = "disabled";
 626         };
 627
 628         i2s1: i2s@ff890000 {
 629                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 630                 reg = <0x0 0xff890000 0x0 0x1000>;
 631                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 632                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 633                 dma-names = "tx", "rx";
 634                 clock-names = "i2s_clk", "i2s_hclk";
 635                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
 636                 pinctrl-names = "default";
 637                 pinctrl-0 = <&i2s1_2ch_bus>;
 638                 status = "disabled";
 639         };
 640
 641         i2s2: i2s@ff8a0000 {
 642                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 643                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 644                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 645                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 646                 dma-names = "tx", "rx";
 647                 clock-names = "i2s_clk", "i2s_hclk";
 648                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
 649                 status = "disabled";
 650         };
 651
 652         pinctrl: pinctrl {
 653                 u-boot,dm-pre-reloc;
 654                 compatible = "rockchip,rk3399-pinctrl";
 655                 rockchip,grf = <&grf>;
 656                 rockchip,pmu = <&pmugrf>;
 657                 #address-cells = <2>;
 658                 #size-cells = <2>;
 659                 ranges;
 660
 661                 gpio0: gpio0@ff720000 {
 662                         compatible = "rockchip,gpio-bank";
 663                         reg = <0x0 0xff720000 0x0 0x100>;
 664                         clocks = <&pmucru PCLK_GPIO0_PMU>;
 665                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 666
 667                         gpio-controller;
 668                         #gpio-cells = <0x2>;
 669
 670                         interrupt-controller;
 671                         #interrupt-cells = <0x2>;
 672                 };
 673
 674                 gpio1: gpio1@ff730000 {
 675                         compatible = "rockchip,gpio-bank";
 676                         reg = <0x0 0xff730000 0x0 0x100>;
 677                         clocks = <&pmucru PCLK_GPIO1_PMU>;
 678                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 679
 680                         gpio-controller;
 681                         #gpio-cells = <0x2>;
 682
 683                         interrupt-controller;
 684                         #interrupt-cells = <0x2>;
 685                 };
 686
 687                 gpio2: gpio2@ff780000 {
 688                         compatible = "rockchip,gpio-bank";
 689                         reg = <0x0 0xff780000 0x0 0x100>;
 690                         clocks = <&cru PCLK_GPIO2>;
 691                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 692
 693                         gpio-controller;
 694                         #gpio-cells = <0x2>;
 695
 696                         interrupt-controller;
 697                         #interrupt-cells = <0x2>;
 698                 };
 699
 700                 gpio3: gpio3@ff788000 {
 701                         compatible = "rockchip,gpio-bank";
 702                         reg = <0x0 0xff788000 0x0 0x100>;
 703                         clocks = <&cru PCLK_GPIO3>;
 704                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 705
 706                         gpio-controller;
 707                         #gpio-cells = <0x2>;
 708
 709                         interrupt-controller;
 710                         #interrupt-cells = <0x2>;
 711                 };
 712
 713                 gpio4: gpio4@ff790000 {
 714                         compatible = "rockchip,gpio-bank";
 715                         reg = <0x0 0xff790000 0x0 0x100>;
 716                         clocks = <&cru PCLK_GPIO4>;
 717                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 718
 719                         gpio-controller;
 720                         #gpio-cells = <0x2>;
 721
 722                         interrupt-controller;
 723                         #interrupt-cells = <0x2>;
 724                 };
 725
 726                 pcfg_pull_up: pcfg-pull-up {
 727                         bias-pull-up;
 728                 };
 729
 730                 pcfg_pull_down: pcfg-pull-down {
 731                         bias-pull-down;
 732                 };
 733
 734                 pcfg_pull_none: pcfg-pull-none {
 735                         bias-disable;
 736                 };
 737
 738                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 739                         bias-disable;
 740                         drive-strength = <12>;
 741                 };
 742
 743                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 744                         bias-pull-up;
 745                         drive-strength = <8>;
 746                 };
 747
 748                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 749                         bias-pull-down;
 750                         drive-strength = <4>;
 751                 };
 752
 753                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 754                         bias-pull-up;
 755                         drive-strength = <2>;
 756                 };
 757
 758                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
 759                         bias-pull-down;
 760                         drive-strength = <12>;
 761                 };
 762
 763                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
 764                         bias-disable;
 765                         drive-strength = <13>;
 766                 };
 767
 768                 i2c0 {
 769                         i2c0_xfer: i2c0-xfer {
 770                                 rockchip,pins =
 771                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
 772                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
 773                         };
 774                 };
 775
 776                 i2c1 {
 777                         i2c1_xfer: i2c1-xfer {
 778                                 rockchip,pins =
 779                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
 780                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
 781                         };
 782                 };
 783
 784                 i2c2 {
 785                         i2c2_xfer: i2c2-xfer {
 786                                 rockchip,pins =
 787                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
 788                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
 789                         };
 790                 };
 791
 792                 i2c3 {
 793                         i2c3_xfer: i2c3-xfer {
 794                                 rockchip,pins =
 795                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
 796                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
 797                         };
 798                 };
 799
 800                 i2c4 {
 801                         i2c4_xfer: i2c4-xfer {
 802                                 rockchip,pins =
 803                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
 804                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 805                         };
 806                 };
 807
 808                 i2c5 {
 809                         i2c5_xfer: i2c5-xfer {
 810                                 rockchip,pins =
 811                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
 812                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
 813                         };
 814                 };
 815
 816                 i2c6 {
 817                         i2c6_xfer: i2c6-xfer {
 818                                 rockchip,pins =
 819                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
 820                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
 821                         };
 822                 };
 823
 824                 i2c7 {
 825                         i2c7_xfer: i2c7-xfer {
 826                                 rockchip,pins =
 827                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
 828                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
 829                         };
 830                 };
 831
 832                 i2c8 {
 833                         i2c8_xfer: i2c8-xfer {
 834                                 rockchip,pins =
 835                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
 836                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
 837                         };
 838                 };
 839
 840                 i2s0 {
 841                         i2s0_8ch_bus: i2s0-8ch-bus {
 842                                 rockchip,pins =
 843                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
 844                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
 845                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
 846                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
 847                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
 848                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
 849                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
 850                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
 851                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
 852                         };
 853                 };
 854
 855                 i2s1 {
 856                         i2s1_2ch_bus: i2s1-2ch-bus {
 857                                 rockchip,pins =
 858                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
 859                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
 860                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
 861                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
 862                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
 863                         };
 864                 };
 865
 866                 sdmmc {
 867                         sdmmc_bus1: sdmmc-bus1 {
 868                                 rockchip,pins =
 869                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
 870                         };
 871
 872                         sdmmc_bus4: sdmmc-bus4 {
 873                                 rockchip,pins =
 874                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
 875                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
 876                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
 877                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
 878                         };
 879
 880                         sdmmc_clk: sdmmc-clk {
 881                                 rockchip,pins =
 882                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
 883                         };
 884
 885                         sdmmc_cmd: sdmmc-cmd {
 886                                 rockchip,pins =
 887                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
 888                         };
 889
 890                         sdmmc_cd: sdmcc-cd {
 891                                 rockchip,pins =
 892                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
 893                         };
 894
 895                         sdmmc_wp: sdmmc-wp {
 896                                 rockchip,pins =
 897                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
 898                         };
 899                 };
 900
 901                 spdif {
 902                         spdif_bus: spdif-bus {
 903                                 rockchip,pins =
 904                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
 905                         };
 906                 };
 907
 908                 spi0 {
 909                         spi0_clk: spi0-clk {
 910                                 rockchip,pins =
 911                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
 912                         };
 913                         spi0_cs0: spi0-cs0 {
 914                                 rockchip,pins =
 915                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
 916                         };
 917                         spi0_cs1: spi0-cs1 {
 918                                 rockchip,pins =
 919                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
 920                         };
 921                         spi0_tx: spi0-tx {
 922                                 rockchip,pins =
 923                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
 924                         };
 925                         spi0_rx: spi0-rx {
 926                                 rockchip,pins =
 927                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
 928                         };
 929                 };
 930
 931                 spi1 {
 932                         spi1_clk: spi1-clk {
 933                                 rockchip,pins =
 934                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
 935                         };
 936                         spi1_cs0: spi1-cs0 {
 937                                 rockchip,pins =
 938                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
 939                         };
 940                         spi1_rx: spi1-rx {
 941                                 rockchip,pins =
 942                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
 943                         };
 944                         spi1_tx: spi1-tx {
 945                                 rockchip,pins =
 946                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
 947                         };
 948                 };
 949
 950                 spi2 {
 951                         spi2_clk: spi2-clk {
 952                                 rockchip,pins =
 953                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
 954                         };
 955                         spi2_cs0: spi2-cs0 {
 956                                 rockchip,pins =
 957                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
 958                         };
 959                         spi2_rx: spi2-rx {
 960                                 rockchip,pins =
 961                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
 962                         };
 963                         spi2_tx: spi2-tx {
 964                                 rockchip,pins =
 965                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
 966                         };
 967                 };
 968
 969                 spi3 {
 970                         spi3_clk: spi3-clk {
 971                                 rockchip,pins =
 972                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
 973                         };
 974                         spi3_cs0: spi3-cs0 {
 975                                 rockchip,pins =
 976                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
 977                         };
 978                         spi3_rx: spi3-rx {
 979                                 rockchip,pins =
 980                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
 981                         };
 982                         spi3_tx: spi3-tx {
 983                                 rockchip,pins =
 984                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
 985                         };
 986                 };
 987
 988                 spi4 {
 989                         spi4_clk: spi4-clk {
 990                                 rockchip,pins =
 991                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
 992                         };
 993                         spi4_cs0: spi4-cs0 {
 994                                 rockchip,pins =
 995                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
 996                         };
 997                         spi4_rx: spi4-rx {
 998                                 rockchip,pins =
 999                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1000                         };
1001                         spi4_tx: spi4-tx {
1002                                 rockchip,pins =
1003                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1004                         };
1005                 };
1006
1007                 spi5 {
1008                         spi5_clk: spi5-clk {
1009                                 rockchip,pins =
1010                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1011                         };
1012                         spi5_cs0: spi5-cs0 {
1013                                 rockchip,pins =
1014                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1015                         };
1016                         spi5_rx: spi5-rx {
1017                                 rockchip,pins =
1018                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1019                         };
1020                         spi5_tx: spi5-tx {
1021                                 rockchip,pins =
1022                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1023                         };
1024                 };
1025
1026                 uart0 {
1027                         uart0_xfer: uart0-xfer {
1028                                 rockchip,pins =
1029                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1030                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1031                         };
1032
1033                         uart0_cts: uart0-cts {
1034                                 rockchip,pins =
1035                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1036                         };
1037
1038                         uart0_rts: uart0-rts {
1039                                 rockchip,pins =
1040                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1041                         };
1042                 };
1043
1044                 uart1 {
1045                         uart1_xfer: uart1-xfer {
1046                                 rockchip,pins =
1047                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1048                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1049                         };
1050                 };
1051
1052                 uart2a {
1053                         uart2a_xfer: uart2a-xfer {
1054                                 rockchip,pins =
1055                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1056                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1057                         };
1058                 };
1059
1060                 uart2b {
1061                         uart2b_xfer: uart2b-xfer {
1062                                 rockchip,pins =
1063                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1064                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1065                         };
1066                 };
1067
1068                 uart2c {
1069                         uart2c_xfer: uart2c-xfer {
1070                                 rockchip,pins =
1071                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1072                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1073                         };
1074                 };
1075
1076                 uart3 {
1077                         uart3_xfer: uart3-xfer {
1078                                 rockchip,pins =
1079                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1080                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1081                         };
1082
1083                         uart3_cts: uart3-cts {
1084                                 rockchip,pins =
1085                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1086                         };
1087
1088                         uart3_rts: uart3-rts {
1089                                 rockchip,pins =
1090                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1091                         };
1092                 };
1093
1094                 uart4 {
1095                         uart4_xfer: uart4-xfer {
1096                                 rockchip,pins =
1097                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1098                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1099                         };
1100                 };
1101
1102                 uarthdcp {
1103                         uarthdcp_xfer: uarthdcp-xfer {
1104                                 rockchip,pins =
1105                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1106                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1107                         };
1108                 };
1109
1110                 pwm0 {
1111                         pwm0_pin: pwm0-pin {
1112                                 rockchip,pins =
1113                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1114                         };
1115
1116                         vop0_pwm_pin: vop0-pwm-pin {
1117                                 rockchip,pins =
1118                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1119                         };
1120                 };
1121
1122                 pwm1 {
1123                         pwm1_pin: pwm1-pin {
1124                                 rockchip,pins =
1125                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1126                         };
1127
1128                         vop1_pwm_pin: vop1-pwm-pin {
1129                                 rockchip,pins =
1130                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1131                         };
1132                 };
1133
1134                 pwm2 {
1135                         pwm2_pin: pwm2-pin {
1136                                 rockchip,pins =
1137                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1138                         };
1139                 };
1140
1141                 pwm3a {
1142                         pwm3a_pin: pwm3a-pin {
1143                                 rockchip,pins =
1144                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1145                         };
1146                 };
1147
1148                 pwm3b {
1149                         pwm3b_pin: pwm3b-pin {
1150                                 rockchip,pins =
1151                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1152                         };
1153                 };
1154         };
1155 };