git.sur5r.net Git - u-boot/blob - arch/arm/dts/rk3399.dtsi

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <dt-bindings/clock/rk3399-cru.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/pinctrl/rockchip.h>
  12 #define USB_CLASS_HUB                   9
  13
  14 / {
  15         compatible = "rockchip,rk3399";
  16
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 serial0 = &uart0;
  23                 serial1 = &uart1;
  24                 serial2 = &uart2;
  25                 serial3 = &uart3;
  26                 serial4 = &uart4;
  27                 mmc0 = &sdhci;
  28                 mmc1 = &sdmmc;
  29         };
  30
  31         cpus {
  32                 #address-cells = <2>;
  33                 #size-cells = <0>;
  34
  35                 cpu-map {
  36                         cluster0 {
  37                                 core0 {
  38                                         cpu = <&cpu_l0>;
  39                                 };
  40                                 core1 {
  41                                         cpu = <&cpu_l1>;
  42                                 };
  43                                 core2 {
  44                                         cpu = <&cpu_l2>;
  45                                 };
  46                                 core3 {
  47                                         cpu = <&cpu_l3>;
  48                                 };
  49                         };
  50
  51                         cluster1 {
  52                                 core0 {
  53                                         cpu = <&cpu_b0>;
  54                                 };
  55                                 core1 {
  56                                         cpu = <&cpu_b1>;
  57                                 };
  58                         };
  59                 };
  60
  61                 cpu_l0: cpu@0 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a53", "arm,armv8";
  64                         reg = <0x0 0x0>;
  65                         enable-method = "psci";
  66                         #cooling-cells = <2>; /* min followed by max */
  67                         clocks = <&cru ARMCLKL>;
  68                 };
  69
  70                 cpu_l1: cpu@1 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a53", "arm,armv8";
  73                         reg = <0x0 0x1>;
  74                         enable-method = "psci";
  75                         clocks = <&cru ARMCLKL>;
  76                 };
  77
  78                 cpu_l2: cpu@2 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a53", "arm,armv8";
  81                         reg = <0x0 0x2>;
  82                         enable-method = "psci";
  83                         clocks = <&cru ARMCLKL>;
  84                 };
  85
  86                 cpu_l3: cpu@3 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53", "arm,armv8";
  89                         reg = <0x0 0x3>;
  90                         enable-method = "psci";
  91                         clocks = <&cru ARMCLKL>;
  92                 };
  93
  94                 cpu_b0: cpu@100 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a72", "arm,armv8";
  97                         reg = <0x0 0x100>;
  98                         enable-method = "psci";
  99                         #cooling-cells = <2>; /* min followed by max */
 100                         clocks = <&cru ARMCLKB>;
 101                 };
 102
 103                 cpu_b1: cpu@101 {
 104                         device_type = "cpu";
 105                         compatible = "arm,cortex-a72", "arm,armv8";
 106                         reg = <0x0 0x101>;
 107                         enable-method = "psci";
 108                         clocks = <&cru ARMCLKB>;
 109                 };
 110         };
 111
 112         psci {
 113                 compatible = "arm,psci-1.0";
 114                 method = "smc";
 115         };
 116
 117         timer {
 118                 compatible = "arm,armv8-timer";
 119                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 120                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 121                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 122                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 123         };
 124
 125         xin24m: xin24m {
 126                 compatible = "fixed-clock";
 127                 clock-frequency = <24000000>;
 128                 clock-output-names = "xin24m";
 129                 #clock-cells = <0>;
 130         };
 131
 132         amba {
 133                 compatible = "simple-bus";
 134                 #address-cells = <2>;
 135                 #size-cells = <2>;
 136                 ranges;
 137
 138                 dmac_bus: dma-controller@ff6d0000 {
 139                         compatible = "arm,pl330", "arm,primecell";
 140                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 141                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 142                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 143                         #dma-cells = <1>;
 144                         clocks = <&cru ACLK_DMAC0_PERILP>;
 145                         clock-names = "apb_pclk";
 146                 };
 147
 148                 dmac_peri: dma-controller@ff6e0000 {
 149                         compatible = "arm,pl330", "arm,primecell";
 150                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 151                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 152                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 153                         #dma-cells = <1>;
 154                         clocks = <&cru ACLK_DMAC1_PERILP>;
 155                         clock-names = "apb_pclk";
 156                 };
 157         };
 158
 159         sdio0: dwmmc@fe310000 {
 160                 compatible = "rockchip,rk3399-dw-mshc",
 161                              "rockchip,rk3288-dw-mshc";
 162                 reg = <0x0 0xfe310000 0x0 0x4000>;
 163                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 164                 clock-freq-min-max = <400000 150000000>;
 165                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 166                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 167                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 168                 fifo-depth = <0x100>;
 169                 status = "disabled";
 170         };
 171
 172         sdmmc: dwmmc@fe320000 {
 173                 compatible = "rockchip,rk3399-dw-mshc",
 174                              "rockchip,rk3288-dw-mshc";
 175                 reg = <0x0 0xfe320000 0x0 0x4000>;
 176                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 177                 clock-freq-min-max = <400000 150000000>;
 178                 clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>,
 179                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 180                 clock-names = "ciu", "biu", "ciu-drive", "ciu-sample";
 181                 pinctrl-names = "default";
 182                 pinctrl-0 = <&sdmmc_clk>;
 183                 fifo-depth = <0x100>;
 184                 status = "disabled";
 185         };
 186
 187         sdhci: sdhci@fe330000 {
 188                 u-boot,dm-pre-reloc;
 189                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 190                 reg = <0x0 0xfe330000 0x0 0x10000>;
 191                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 192                 assigned-clocks = <&cru SCLK_EMMC>;
 193                 assigned-clock-rates = <200000000>;
 194                 max-frequency = <200000000>;
 195                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 196                 clock-names = "clk_xin", "clk_ahb";
 197                 phys = <&emmc_phy>;
 198                 phy-names = "phy_arasan";
 199                 status = "disabled";
 200         };
 201
 202         usb_host0_ehci: usb@fe380000 {
 203                 compatible = "generic-ehci";
 204                 reg = <0x0 0xfe380000 0x0 0x20000>;
 205                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 206                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 207                 clock-names = "hclk_host0", "hclk_host0_arb";
 208                 status = "disabled";
 209         };
 210
 211         usb_host0_ohci: usb@fe3a0000 {
 212                 compatible = "generic-ohci";
 213                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 214                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 215                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 216                 clock-names = "hclk_host0", "hclk_host0_arb";
 217                 status = "disabled";
 218         };
 219
 220         usb_host1_ehci: usb@fe3c0000 {
 221                 compatible = "generic-ehci";
 222                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 223                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 224                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 225                 clock-names = "hclk_host1", "hclk_host1_arb";
 226                 status = "disabled";
 227         };
 228
 229         usb_host1_ohci: usb@fe3e0000 {
 230                 compatible = "generic-ohci";
 231                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 232                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 233                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 234                 clock-names = "hclk_host1", "hclk_host1_arb";
 235                 status = "disabled";
 236         };
 237
 238         dwc3_typec0: usb@fe800000 {
 239                 compatible = "rockchip,rk3399-xhci";
 240                 reg = <0x0 0xfe800000 0x0 0x100000>;
 241                 status = "disabled";
 242                 rockchip,vbus-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
 243                 snps,dis-enblslpm-quirk;
 244                 snps,phyif-utmi-bits = <16>;
 245                 snps,dis-u2-freeclk-exists-quirk;
 246                 snps,dis-u2-susphy-quirk;
 247
 248                 #address-cells = <2>;
 249                 #size-cells = <2>;
 250                 hub {
 251                         compatible = "usb-hub";
 252                         usb,device-class = <USB_CLASS_HUB>;
 253                 };
 254                 typec_phy0 {
 255                         compatible = "rockchip,rk3399-usb3-phy";
 256                         reg = <0x0 0xff7c0000 0x0 0x40000>;
 257                 };
 258         };
 259
 260         dwc3_typec1: usb@fe900000 {
 261                 compatible = "rockchip,rk3399-xhci";
 262                 reg = <0x0 0xfe900000 0x0 0x100000>;
 263                 status = "disabled";
 264                 rockchip,vbus-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 265                 snps,dis-enblslpm-quirk;
 266                 snps,phyif-utmi-bits = <16>;
 267                 snps,dis-u2-freeclk-exists-quirk;
 268                 snps,dis-u2-susphy-quirk;
 269
 270                 #address-cells = <2>;
 271                 #size-cells = <2>;
 272                 hub {
 273                         compatible = "usb-hub";
 274                         usb,device-class = <USB_CLASS_HUB>;
 275                 };
 276                 typec_phy1 {
 277                         compatible = "rockchip,rk3399-usb3-phy";
 278                         reg = <0x0 0xff800000 0x0 0x40000>;
 279                 };
 280         };
 281
 282         gic: interrupt-controller@fee00000 {
 283                 compatible = "arm,gic-v3";
 284                 #interrupt-cells = <3>;
 285                 #address-cells = <2>;
 286                 #size-cells = <2>;
 287                 ranges;
 288                 interrupt-controller;
 289
 290                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 291                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 292                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 293                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 294                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 295                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 296                 its: interrupt-controller@fee20000 {
 297                         compatible = "arm,gic-v3-its";
 298                         msi-controller;
 299                         reg = <0x0 0xfee20000 0x0 0x20000>;
 300                 };
 301         };
 302
 303         uart0: serial@ff180000 {
 304                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 305                 reg = <0x0 0xff180000 0x0 0x100>;
 306                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 307                 clock-names = "baudclk", "apb_pclk";
 308                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 309                 reg-shift = <2>;
 310                 reg-io-width = <4>;
 311                 pinctrl-names = "default";
 312                 pinctrl-0 = <&uart0_xfer>;
 313                 status = "disabled";
 314         };
 315
 316         uart1: serial@ff190000 {
 317                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 318                 reg = <0x0 0xff190000 0x0 0x100>;
 319                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 320                 clock-names = "baudclk", "apb_pclk";
 321                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 322                 reg-shift = <2>;
 323                 reg-io-width = <4>;
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&uart1_xfer>;
 326                 status = "disabled";
 327         };
 328
 329         uart2: serial@ff1a0000 {
 330                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 331                 reg = <0x0 0xff1a0000 0x0 0x100>;
 332                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 333                 clock-names = "baudclk", "apb_pclk";
 334                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 335                 clock-frequency = <24000000>;
 336                 reg-shift = <2>;
 337                 reg-io-width = <4>;
 338                 pinctrl-names = "default";
 339                 pinctrl-0 = <&uart2c_xfer>;
 340                 status = "disabled";
 341         };
 342
 343         uart3: serial@ff1b0000 {
 344                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 345                 reg = <0x0 0xff1b0000 0x0 0x100>;
 346                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 347                 clock-names = "baudclk", "apb_pclk";
 348                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 349                 reg-shift = <2>;
 350                 reg-io-width = <4>;
 351                 pinctrl-names = "default";
 352                 pinctrl-0 = <&uart3_xfer>;
 353                 status = "disabled";
 354         };
 355
 356         spi0: spi@ff1c0000 {
 357                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 358                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 359                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 360                 clock-names = "spiclk", "apb_pclk";
 361                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 362                 pinctrl-names = "default";
 363                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366                 status = "disabled";
 367         };
 368
 369         spi1: spi@ff1d0000 {
 370                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 371                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 372                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 373                 clock-names = "spiclk", "apb_pclk";
 374                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 375                 pinctrl-names = "default";
 376                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 377                 #address-cells = <1>;
 378                 #size-cells = <0>;
 379                 status = "disabled";
 380         };
 381
 382         spi2: spi@ff1e0000 {
 383                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 384                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 385                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 386                 clock-names = "spiclk", "apb_pclk";
 387                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 388                 pinctrl-names = "default";
 389                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 390                 #address-cells = <1>;
 391                 #size-cells = <0>;
 392                 status = "disabled";
 393         };
 394
 395         spi4: spi@ff1f0000 {
 396                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 397                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 398                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 399                 clock-names = "spiclk", "apb_pclk";
 400                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 401                 pinctrl-names = "default";
 402                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 status = "disabled";
 406         };
 407
 408         spi5: spi@ff200000 {
 409                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 410                 reg = <0x0 0xff200000 0x0 0x1000>;
 411                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 412                 clock-names = "spiclk", "apb_pclk";
 413                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 414                 pinctrl-names = "default";
 415                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 416                 #address-cells = <1>;
 417                 #size-cells = <0>;
 418                 status = "disabled";
 419         };
 420
 421         pmugrf: syscon@ff320000 {
 422                 u-boot,dm-pre-reloc;
 423                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 424                 reg = <0x0 0xff320000 0x0 0x1000>;
 425                 #address-cells = <1>;
 426                 #size-cells = <1>;
 427
 428                 pmu_io_domains: io-domains {
 429                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
 430                         status = "disabled";
 431                 };
 432         };
 433
 434         pmusgrf: syscon@ff330000 {
 435                 u-boot,dm-pre-reloc;
 436                 compatible = "rockchip,rk3399-pmusgrf", "syscon";
 437                 reg = <0x0 0xff330000 0x0 0xe3d4>;
 438         };
 439
 440         spi3: spi@ff350000 {
 441                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 442                 reg = <0x0 0xff350000 0x0 0x1000>;
 443                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 444                 clock-names = "spiclk", "apb_pclk";
 445                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 446                 pinctrl-names = "default";
 447                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 448                 #address-cells = <1>;
 449                 #size-cells = <0>;
 450                 status = "disabled";
 451         };
 452
 453         uart4: serial@ff370000 {
 454                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 455                 reg = <0x0 0xff370000 0x0 0x100>;
 456                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 457                 clock-names = "baudclk", "apb_pclk";
 458                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 459                 reg-shift = <2>;
 460                 reg-io-width = <4>;
 461                 pinctrl-names = "default";
 462                 pinctrl-0 = <&uart4_xfer>;
 463                 status = "disabled";
 464         };
 465
 466         pwm0: pwm@ff420000 {
 467                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 468                 reg = <0x0 0xff420000 0x0 0x10>;
 469                 #pwm-cells = <3>;
 470                 pinctrl-names = "default";
 471                 pinctrl-0 = <&pwm0_pin>;
 472                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 473                 clock-names = "pwm";
 474                 status = "disabled";
 475         };
 476
 477         pwm1: pwm@ff420010 {
 478                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 479                 reg = <0x0 0xff420010 0x0 0x10>;
 480                 #pwm-cells = <3>;
 481                 pinctrl-names = "default";
 482                 pinctrl-0 = <&pwm1_pin>;
 483                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 484                 clock-names = "pwm";
 485                 status = "disabled";
 486         };
 487
 488         pwm2: pwm@ff420020 {
 489                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 490                 reg = <0x0 0xff420020 0x0 0x10>;
 491                 #pwm-cells = <3>;
 492                 pinctrl-names = "default";
 493                 pinctrl-0 = <&pwm2_pin>;
 494                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 495                 clock-names = "pwm";
 496                 status = "disabled";
 497         };
 498
 499         pwm3: pwm@ff420030 {
 500                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 501                 reg = <0x0 0xff420030 0x0 0x10>;
 502                 #pwm-cells = <3>;
 503                 pinctrl-names = "default";
 504                 pinctrl-0 = <&pwm3a_pin>;
 505                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 506                 clock-names = "pwm";
 507                 status = "disabled";
 508         };
 509
 510         cic: syscon@ff620000 {
 511                 u-boot,dm-pre-reloc;
 512                 compatible = "rockchip,rk3399-cic", "syscon";
 513                 reg = <0x0 0xff620000 0x0 0x100>;
 514         };
 515
 516         dfi: dfi@ff630000 {
 517                 reg = <0x00 0xff630000 0x00 0x4000>;
 518                 compatible = "rockchip,rk3399-dfi";
 519                 rockchip,pmu = <&pmugrf>;
 520                 clocks = <&cru PCLK_DDR_MON>;
 521                 clock-names = "pclk_ddr_mon";
 522                 status = "disabled";
 523         };
 524
 525         dmc: dmc {
 526                 u-boot,dm-pre-reloc;
 527                 compatible = "rockchip,rk3399-dmc";
 528                 devfreq-events = <&dfi>;
 529                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
 530                 clocks = <&cru SCLK_DDRCLK>;
 531                 clock-names = "dmc_clk";
 532                 reg = <0x0 0xffa80000 0x0 0x0800
 533                        0x0 0xffa80800 0x0 0x1800
 534                        0x0 0xffa82000 0x0 0x2000
 535                        0x0 0xffa84000 0x0 0x1000
 536                        0x0 0xffa88000 0x0 0x0800
 537                        0x0 0xffa88800 0x0 0x1800
 538                        0x0 0xffa8a000 0x0 0x2000
 539                        0x0 0xffa8c000 0x0 0x1000>;
 540         };
 541
 542         pmucru: pmu-clock-controller@ff750000 {
 543                 u-boot,dm-pre-reloc;
 544                 compatible = "rockchip,rk3399-pmucru";
 545                 reg = <0x0 0xff750000 0x0 0x1000>;
 546                 #clock-cells = <1>;
 547                 #reset-cells = <1>;
 548                 assigned-clocks = <&pmucru PLL_PPLL>;
 549                 assigned-clock-rates = <676000000>;
 550         };
 551
 552         cru: clock-controller@ff760000 {
 553                 u-boot,dm-pre-reloc;
 554                 compatible = "rockchip,rk3399-cru";
 555                 reg = <0x0 0xff760000 0x0 0x1000>;
 556                 #clock-cells = <1>;
 557                 #reset-cells = <1>;
 558                 assigned-clocks =
 559                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 560                         <&cru PLL_NPLL>,
 561                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 562                         <&cru PCLK_PERIHP>,
 563                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 564                         <&cru PCLK_PERILP0>,
 565                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 566                 assigned-clock-rates =
 567                          <594000000>,  <800000000>,
 568                         <1000000000>,
 569                          <150000000>,   <75000000>,
 570                           <37500000>,
 571                          <100000000>,  <100000000>,
 572                           <50000000>,
 573                          <100000000>,   <50000000>;
 574         };
 575
 576         grf: syscon@ff770000 {
 577                 u-boot,dm-pre-reloc;
 578                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
 579                 reg = <0x0 0xff770000 0x0 0x10000>;
 580                 #address-cells = <1>;
 581                 #size-cells = <1>;
 582
 583                 io_domains: io-domains {
 584                         compatible = "rockchip,rk3399-io-voltage-domain";
 585                         status = "disabled";
 586                 };
 587
 588                 emmc_phy: phy@f780 {
 589                         compatible = "rockchip,rk3399-emmc-phy";
 590                         reg = <0xf780 0x24>;
 591                         #phy-cells = <0>;
 592                         status = "disabled";
 593                 };
 594         };
 595
 596         watchdog@ff840000 {
 597                 compatible = "snps,dw-wdt";
 598                 reg = <0x0 0xff840000 0x0 0x100>;
 599                 clocks = <&cru PCLK_WDT>;
 600                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 601         };
 602
 603         spdif: spdif@ff870000 {
 604                 compatible = "rockchip,rk3399-spdif";
 605                 reg = <0x0 0xff870000 0x0 0x1000>;
 606                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 607                 dmas = <&dmac_bus 7>;
 608                 dma-names = "tx";
 609                 clock-names = "mclk", "hclk";
 610                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 611                 pinctrl-names = "default";
 612                 pinctrl-0 = <&spdif_bus>;
 613                 status = "disabled";
 614         };
 615
 616         i2s0: i2s@ff880000 {
 617                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 618                 reg = <0x0 0xff880000 0x0 0x1000>;
 619                 rockchip,grf = <&grf>;
 620                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 621                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 622                 dma-names = "tx", "rx";
 623                 clock-names = "i2s_clk", "i2s_hclk";
 624                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
 625                 pinctrl-names = "default";
 626                 pinctrl-0 = <&i2s0_8ch_bus>;
 627                 status = "disabled";
 628         };
 629
 630         i2s1: i2s@ff890000 {
 631                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 632                 reg = <0x0 0xff890000 0x0 0x1000>;
 633                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 634                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 635                 dma-names = "tx", "rx";
 636                 clock-names = "i2s_clk", "i2s_hclk";
 637                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
 638                 pinctrl-names = "default";
 639                 pinctrl-0 = <&i2s1_2ch_bus>;
 640                 status = "disabled";
 641         };
 642
 643         i2s2: i2s@ff8a0000 {
 644                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 645                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 646                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 647                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 648                 dma-names = "tx", "rx";
 649                 clock-names = "i2s_clk", "i2s_hclk";
 650                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
 651                 status = "disabled";
 652         };
 653
 654         pinctrl: pinctrl {
 655                 u-boot,dm-pre-reloc;
 656                 compatible = "rockchip,rk3399-pinctrl";
 657                 rockchip,grf = <&grf>;
 658                 rockchip,pmu = <&pmugrf>;
 659                 #address-cells = <2>;
 660                 #size-cells = <2>;
 661                 ranges;
 662
 663                 gpio0: gpio0@ff720000 {
 664                         compatible = "rockchip,gpio-bank";
 665                         reg = <0x0 0xff720000 0x0 0x100>;
 666                         clocks = <&pmucru PCLK_GPIO0_PMU>;
 667                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 668
 669                         gpio-controller;
 670                         #gpio-cells = <0x2>;
 671
 672                         interrupt-controller;
 673                         #interrupt-cells = <0x2>;
 674                 };
 675
 676                 gpio1: gpio1@ff730000 {
 677                         compatible = "rockchip,gpio-bank";
 678                         reg = <0x0 0xff730000 0x0 0x100>;
 679                         clocks = <&pmucru PCLK_GPIO1_PMU>;
 680                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 681
 682                         gpio-controller;
 683                         #gpio-cells = <0x2>;
 684
 685                         interrupt-controller;
 686                         #interrupt-cells = <0x2>;
 687                 };
 688
 689                 gpio2: gpio2@ff780000 {
 690                         compatible = "rockchip,gpio-bank";
 691                         reg = <0x0 0xff780000 0x0 0x100>;
 692                         clocks = <&cru PCLK_GPIO2>;
 693                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 694
 695                         gpio-controller;
 696                         #gpio-cells = <0x2>;
 697
 698                         interrupt-controller;
 699                         #interrupt-cells = <0x2>;
 700                 };
 701
 702                 gpio3: gpio3@ff788000 {
 703                         compatible = "rockchip,gpio-bank";
 704                         reg = <0x0 0xff788000 0x0 0x100>;
 705                         clocks = <&cru PCLK_GPIO3>;
 706                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 707
 708                         gpio-controller;
 709                         #gpio-cells = <0x2>;
 710
 711                         interrupt-controller;
 712                         #interrupt-cells = <0x2>;
 713                 };
 714
 715                 gpio4: gpio4@ff790000 {
 716                         compatible = "rockchip,gpio-bank";
 717                         reg = <0x0 0xff790000 0x0 0x100>;
 718                         clocks = <&cru PCLK_GPIO4>;
 719                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 720
 721                         gpio-controller;
 722                         #gpio-cells = <0x2>;
 723
 724                         interrupt-controller;
 725                         #interrupt-cells = <0x2>;
 726                 };
 727
 728                 pcfg_pull_up: pcfg-pull-up {
 729                         bias-pull-up;
 730                 };
 731
 732                 pcfg_pull_down: pcfg-pull-down {
 733                         bias-pull-down;
 734                 };
 735
 736                 pcfg_pull_none: pcfg-pull-none {
 737                         bias-disable;
 738                 };
 739
 740                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 741                         bias-disable;
 742                         drive-strength = <12>;
 743                 };
 744
 745                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 746                         bias-pull-up;
 747                         drive-strength = <8>;
 748                 };
 749
 750                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 751                         bias-pull-down;
 752                         drive-strength = <4>;
 753                 };
 754
 755                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 756                         bias-pull-up;
 757                         drive-strength = <2>;
 758                 };
 759
 760                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
 761                         bias-pull-down;
 762                         drive-strength = <12>;
 763                 };
 764
 765                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
 766                         bias-disable;
 767                         drive-strength = <13>;
 768                 };
 769
 770                 i2c0 {
 771                         i2c0_xfer: i2c0-xfer {
 772                                 rockchip,pins =
 773                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
 774                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
 775                         };
 776                 };
 777
 778                 i2c1 {
 779                         i2c1_xfer: i2c1-xfer {
 780                                 rockchip,pins =
 781                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
 782                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
 783                         };
 784                 };
 785
 786                 i2c2 {
 787                         i2c2_xfer: i2c2-xfer {
 788                                 rockchip,pins =
 789                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
 790                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
 791                         };
 792                 };
 793
 794                 i2c3 {
 795                         i2c3_xfer: i2c3-xfer {
 796                                 rockchip,pins =
 797                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
 798                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
 799                         };
 800                 };
 801
 802                 i2c4 {
 803                         i2c4_xfer: i2c4-xfer {
 804                                 rockchip,pins =
 805                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
 806                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 807                         };
 808                 };
 809
 810                 i2c5 {
 811                         i2c5_xfer: i2c5-xfer {
 812                                 rockchip,pins =
 813                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
 814                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
 815                         };
 816                 };
 817
 818                 i2c6 {
 819                         i2c6_xfer: i2c6-xfer {
 820                                 rockchip,pins =
 821                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
 822                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
 823                         };
 824                 };
 825
 826                 i2c7 {
 827                         i2c7_xfer: i2c7-xfer {
 828                                 rockchip,pins =
 829                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
 830                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
 831                         };
 832                 };
 833
 834                 i2c8 {
 835                         i2c8_xfer: i2c8-xfer {
 836                                 rockchip,pins =
 837                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
 838                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
 839                         };
 840                 };
 841
 842                 i2s0 {
 843                         i2s0_8ch_bus: i2s0-8ch-bus {
 844                                 rockchip,pins =
 845                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
 846                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
 847                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
 848                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
 849                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
 850                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
 851                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
 852                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
 853                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
 854                         };
 855                 };
 856
 857                 i2s1 {
 858                         i2s1_2ch_bus: i2s1-2ch-bus {
 859                                 rockchip,pins =
 860                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
 861                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
 862                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
 863                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
 864                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
 865                         };
 866                 };
 867
 868                 sdmmc {
 869                         sdmmc_bus1: sdmmc-bus1 {
 870                                 rockchip,pins =
 871                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
 872                         };
 873
 874                         sdmmc_bus4: sdmmc-bus4 {
 875                                 rockchip,pins =
 876                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
 877                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
 878                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
 879                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
 880                         };
 881
 882                         sdmmc_clk: sdmmc-clk {
 883                                 rockchip,pins =
 884                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
 885                         };
 886
 887                         sdmmc_cmd: sdmmc-cmd {
 888                                 rockchip,pins =
 889                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
 890                         };
 891
 892                         sdmmc_cd: sdmcc-cd {
 893                                 rockchip,pins =
 894                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
 895                         };
 896
 897                         sdmmc_wp: sdmmc-wp {
 898                                 rockchip,pins =
 899                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
 900                         };
 901                 };
 902
 903                 spdif {
 904                         spdif_bus: spdif-bus {
 905                                 rockchip,pins =
 906                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
 907                         };
 908                 };
 909
 910                 spi0 {
 911                         spi0_clk: spi0-clk {
 912                                 rockchip,pins =
 913                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
 914                         };
 915                         spi0_cs0: spi0-cs0 {
 916                                 rockchip,pins =
 917                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
 918                         };
 919                         spi0_cs1: spi0-cs1 {
 920                                 rockchip,pins =
 921                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
 922                         };
 923                         spi0_tx: spi0-tx {
 924                                 rockchip,pins =
 925                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
 926                         };
 927                         spi0_rx: spi0-rx {
 928                                 rockchip,pins =
 929                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
 930                         };
 931                 };
 932
 933                 spi1 {
 934                         spi1_clk: spi1-clk {
 935                                 rockchip,pins =
 936                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
 937                         };
 938                         spi1_cs0: spi1-cs0 {
 939                                 rockchip,pins =
 940                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
 941                         };
 942                         spi1_rx: spi1-rx {
 943                                 rockchip,pins =
 944                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
 945                         };
 946                         spi1_tx: spi1-tx {
 947                                 rockchip,pins =
 948                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
 949                         };
 950                 };
 951
 952                 spi2 {
 953                         spi2_clk: spi2-clk {
 954                                 rockchip,pins =
 955                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
 956                         };
 957                         spi2_cs0: spi2-cs0 {
 958                                 rockchip,pins =
 959                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
 960                         };
 961                         spi2_rx: spi2-rx {
 962                                 rockchip,pins =
 963                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
 964                         };
 965                         spi2_tx: spi2-tx {
 966                                 rockchip,pins =
 967                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
 968                         };
 969                 };
 970
 971                 spi3 {
 972                         spi3_clk: spi3-clk {
 973                                 rockchip,pins =
 974                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
 975                         };
 976                         spi3_cs0: spi3-cs0 {
 977                                 rockchip,pins =
 978                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
 979                         };
 980                         spi3_rx: spi3-rx {
 981                                 rockchip,pins =
 982                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
 983                         };
 984                         spi3_tx: spi3-tx {
 985                                 rockchip,pins =
 986                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
 987                         };
 988                 };
 989
 990                 spi4 {
 991                         spi4_clk: spi4-clk {
 992                                 rockchip,pins =
 993                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
 994                         };
 995                         spi4_cs0: spi4-cs0 {
 996                                 rockchip,pins =
 997                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
 998                         };
 999                         spi4_rx: spi4-rx {
1000                                 rockchip,pins =
1001                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1002                         };
1003                         spi4_tx: spi4-tx {
1004                                 rockchip,pins =
1005                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1006                         };
1007                 };
1008
1009                 spi5 {
1010                         spi5_clk: spi5-clk {
1011                                 rockchip,pins =
1012                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1013                         };
1014                         spi5_cs0: spi5-cs0 {
1015                                 rockchip,pins =
1016                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1017                         };
1018                         spi5_rx: spi5-rx {
1019                                 rockchip,pins =
1020                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1021                         };
1022                         spi5_tx: spi5-tx {
1023                                 rockchip,pins =
1024                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1025                         };
1026                 };
1027
1028                 uart0 {
1029                         uart0_xfer: uart0-xfer {
1030                                 rockchip,pins =
1031                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1032                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1033                         };
1034
1035                         uart0_cts: uart0-cts {
1036                                 rockchip,pins =
1037                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1038                         };
1039
1040                         uart0_rts: uart0-rts {
1041                                 rockchip,pins =
1042                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1043                         };
1044                 };
1045
1046                 uart1 {
1047                         uart1_xfer: uart1-xfer {
1048                                 rockchip,pins =
1049                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1050                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1051                         };
1052                 };
1053
1054                 uart2a {
1055                         uart2a_xfer: uart2a-xfer {
1056                                 rockchip,pins =
1057                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1058                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1059                         };
1060                 };
1061
1062                 uart2b {
1063                         uart2b_xfer: uart2b-xfer {
1064                                 rockchip,pins =
1065                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1066                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1067                         };
1068                 };
1069
1070                 uart2c {
1071                         uart2c_xfer: uart2c-xfer {
1072                                 rockchip,pins =
1073                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1074                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1075                         };
1076                 };
1077
1078                 uart3 {
1079                         uart3_xfer: uart3-xfer {
1080                                 rockchip,pins =
1081                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1082                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1083                         };
1084
1085                         uart3_cts: uart3-cts {
1086                                 rockchip,pins =
1087                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1088                         };
1089
1090                         uart3_rts: uart3-rts {
1091                                 rockchip,pins =
1092                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1093                         };
1094                 };
1095
1096                 uart4 {
1097                         uart4_xfer: uart4-xfer {
1098                                 rockchip,pins =
1099                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1100                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1101                         };
1102                 };
1103
1104                 uarthdcp {
1105                         uarthdcp_xfer: uarthdcp-xfer {
1106                                 rockchip,pins =
1107                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1108                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1109                         };
1110                 };
1111
1112                 pwm0 {
1113                         pwm0_pin: pwm0-pin {
1114                                 rockchip,pins =
1115                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1116                         };
1117
1118                         vop0_pwm_pin: vop0-pwm-pin {
1119                                 rockchip,pins =
1120                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1121                         };
1122                 };
1123
1124                 pwm1 {
1125                         pwm1_pin: pwm1-pin {
1126                                 rockchip,pins =
1127                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1128                         };
1129
1130                         vop1_pwm_pin: vop1-pwm-pin {
1131                                 rockchip,pins =
1132                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1133                         };
1134                 };
1135
1136                 pwm2 {
1137                         pwm2_pin: pwm2-pin {
1138                                 rockchip,pins =
1139                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1140                         };
1141                 };
1142
1143                 pwm3a {
1144                         pwm3a_pin: pwm3a-pin {
1145                                 rockchip,pins =
1146                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1147                         };
1148                 };
1149
1150                 pwm3b {
1151                         pwm3b_pin: pwm3b-pin {
1152                                 rockchip,pins =
1153                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1154                         };
1155                 };
1156         };
1157 };