git.sur5r.net Git - u-boot/blob - arch/arm/dts/rk3399.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd.
   4  */
   5
   6 #include <dt-bindings/clock/rk3399-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3399-power.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13 #define USB_CLASS_HUB                   9
  14
  15 / {
  16         compatible = "rockchip,rk3399";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 i2c6 = &i2c6;
  30                 i2c7 = &i2c7;
  31                 i2c8 = &i2c8;
  32                 serial0 = &uart0;
  33                 serial1 = &uart1;
  34                 serial2 = &uart2;
  35                 serial3 = &uart3;
  36                 serial4 = &uart4;
  37                 mmc0 = &sdhci;
  38                 mmc1 = &sdmmc;
  39         };
  40
  41         cpus {
  42                 #address-cells = <2>;
  43                 #size-cells = <0>;
  44
  45                 cpu-map {
  46                         cluster0 {
  47                                 core0 {
  48                                         cpu = <&cpu_l0>;
  49                                 };
  50                                 core1 {
  51                                         cpu = <&cpu_l1>;
  52                                 };
  53                                 core2 {
  54                                         cpu = <&cpu_l2>;
  55                                 };
  56                                 core3 {
  57                                         cpu = <&cpu_l3>;
  58                                 };
  59                         };
  60
  61                         cluster1 {
  62                                 core0 {
  63                                         cpu = <&cpu_b0>;
  64                                 };
  65                                 core1 {
  66                                         cpu = <&cpu_b1>;
  67                                 };
  68                         };
  69                 };
  70
  71                 cpu_l0: cpu@0 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53", "arm,armv8";
  74                         reg = <0x0 0x0>;
  75                         enable-method = "psci";
  76                         #cooling-cells = <2>; /* min followed by max */
  77                         clocks = <&cru ARMCLKL>;
  78                 };
  79
  80                 cpu_l1: cpu@1 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a53", "arm,armv8";
  83                         reg = <0x0 0x1>;
  84                         enable-method = "psci";
  85                         clocks = <&cru ARMCLKL>;
  86                 };
  87
  88                 cpu_l2: cpu@2 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a53", "arm,armv8";
  91                         reg = <0x0 0x2>;
  92                         enable-method = "psci";
  93                         clocks = <&cru ARMCLKL>;
  94                 };
  95
  96                 cpu_l3: cpu@3 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a53", "arm,armv8";
  99                         reg = <0x0 0x3>;
 100                         enable-method = "psci";
 101                         clocks = <&cru ARMCLKL>;
 102                 };
 103
 104                 cpu_b0: cpu@100 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a72", "arm,armv8";
 107                         reg = <0x0 0x100>;
 108                         enable-method = "psci";
 109                         #cooling-cells = <2>; /* min followed by max */
 110                         clocks = <&cru ARMCLKB>;
 111                 };
 112
 113                 cpu_b1: cpu@101 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a72", "arm,armv8";
 116                         reg = <0x0 0x101>;
 117                         enable-method = "psci";
 118                         clocks = <&cru ARMCLKB>;
 119                 };
 120         };
 121
 122         pmu_a53 {
 123                 compatible = "arm,cortex-a53-pmu";
 124                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 125         };
 126
 127         pmu_a72 {
 128                 compatible = "arm,cortex-a72-pmu";
 129                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 130         };
 131
 132         psci {
 133                 compatible = "arm,psci-1.0";
 134                 method = "smc";
 135         };
 136
 137         timer {
 138                 compatible = "arm,armv8-timer";
 139                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 140                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 141                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 142                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 143                 arm,no-tick-in-suspend;
 144         };
 145
 146         xin24m: xin24m {
 147                 compatible = "fixed-clock";
 148                 clock-frequency = <24000000>;
 149                 clock-output-names = "xin24m";
 150                 #clock-cells = <0>;
 151         };
 152
 153         amba {
 154                 compatible = "simple-bus";
 155                 #address-cells = <2>;
 156                 #size-cells = <2>;
 157                 ranges;
 158
 159                 dmac_bus: dma-controller@ff6d0000 {
 160                         compatible = "arm,pl330", "arm,primecell";
 161                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 162                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 163                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 164                         #dma-cells = <1>;
 165                         clocks = <&cru ACLK_DMAC0_PERILP>;
 166                         clock-names = "apb_pclk";
 167                 };
 168
 169                 dmac_peri: dma-controller@ff6e0000 {
 170                         compatible = "arm,pl330", "arm,primecell";
 171                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 172                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 173                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 174                         #dma-cells = <1>;
 175                         clocks = <&cru ACLK_DMAC1_PERILP>;
 176                         clock-names = "apb_pclk";
 177                 };
 178         };
 179
 180         pcie0: pcie@f8000000 {
 181                 compatible = "rockchip,rk3399-pcie";
 182                 reg = <0x0 0xf8000000 0x0 0x2000000>,
 183                       <0x0 0xfd000000 0x0 0x1000000>;
 184                 reg-names = "axi-base", "apb-base";
 185                 #address-cells = <3>;
 186                 #size-cells = <2>;
 187                 #interrupt-cells = <1>;
 188                 aspm-no-l0s;
 189                 bus-range = <0x0 0x1>;
 190                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 191                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
 192                 clock-names = "aclk", "aclk-perf",
 193                               "hclk", "pm";
 194                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
 195                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
 196                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
 197                 interrupt-names = "sys", "legacy", "client";
 198                 interrupt-map-mask = <0 0 0 7>;
 199                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
 200                                 <0 0 0 2 &pcie0_intc 1>,
 201                                 <0 0 0 3 &pcie0_intc 2>,
 202                                 <0 0 0 4 &pcie0_intc 3>;
 203                 linux,pci-domain = <0>;
 204                 max-link-speed = <1>;
 205                 msi-map = <0x0 &its 0x0 0x1000>;
 206                 phys = <&pcie_phy>;
 207                 phy-names = "pcie-phy";
 208                 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
 209                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
 210                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
 211                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
 212                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
 213                          <&cru SRST_A_PCIE>;
 214                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
 215                               "pm", "pclk", "aclk";
 216                 status = "disabled";
 217
 218                 pcie0_intc: interrupt-controller {
 219                         interrupt-controller;
 220                         #address-cells = <0>;
 221                         #interrupt-cells = <1>;
 222                 };
 223         };
 224
 225         gmac: ethernet@fe300000 {
 226                 compatible = "rockchip,rk3399-gmac";
 227                 reg = <0x0 0xfe300000 0x0 0x10000>;
 228                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 229                 interrupt-names = "macirq";
 230                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 231                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 232                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 233                          <&cru PCLK_GMAC>;
 234                 clock-names = "stmmaceth", "mac_clk_rx",
 235                               "mac_clk_tx", "clk_mac_ref",
 236                               "clk_mac_refout", "aclk_mac",
 237                               "pclk_mac";
 238                 power-domains = <&power RK3399_PD_GMAC>;
 239                 resets = <&cru SRST_A_GMAC>;
 240                 reset-names = "stmmaceth";
 241                 rockchip,grf = <&grf>;
 242                 status = "disabled";
 243         };
 244
 245         sdio0: dwmmc@fe310000 {
 246                 compatible = "rockchip,rk3399-dw-mshc",
 247                              "rockchip,rk3288-dw-mshc";
 248                 reg = <0x0 0xfe310000 0x0 0x4000>;
 249                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 250                 max-frequency = <150000000>;
 251                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 252                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 253                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 254                 fifo-depth = <0x100>;
 255                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 256                 resets = <&cru SRST_SDIO0>;
 257                 reset-names = "reset";
 258                 status = "disabled";
 259         };
 260
 261         sdmmc: dwmmc@fe320000 {
 262                 compatible = "rockchip,rk3399-dw-mshc",
 263                              "rockchip,rk3288-dw-mshc";
 264                 reg = <0x0 0xfe320000 0x0 0x4000>;
 265                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 266                 max-frequency = <150000000>;
 267                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 268                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 269                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 270                 fifo-depth = <0x100>;
 271                 power-domains = <&power RK3399_PD_SD>;
 272                 resets = <&cru SRST_SDMMC>;
 273                 reset-names = "reset";
 274                 status = "disabled";
 275         };
 276
 277         sdhci: sdhci@fe330000 {
 278                 u-boot,dm-pre-reloc;
 279                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 280                 reg = <0x0 0xfe330000 0x0 0x10000>;
 281                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 282                 arasan,soc-ctl-syscon = <&grf>;
 283                 assigned-clocks = <&cru SCLK_EMMC>;
 284                 assigned-clock-rates = <200000000>;
 285                 max-frequency = <200000000>;
 286                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 287                 clock-names = "clk_xin", "clk_ahb";
 288                 clock-output-names = "emmc_cardclock";
 289                 #clock-cells = <0>;
 290                 phys = <&emmc_phy>;
 291                 phy-names = "phy_arasan";
 292                 power-domains = <&power RK3399_PD_EMMC>;
 293                 status = "disabled";
 294         };
 295
 296         usb_host0_ehci: usb@fe380000 {
 297                 compatible = "generic-ehci";
 298                 reg = <0x0 0xfe380000 0x0 0x20000>;
 299                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 300                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 301                          <&u2phy0>;
 302                 clock-names = "usbhost", "arbiter",
 303                               "utmi";
 304                 phys = <&u2phy0_host>;
 305                 phy-names = "usb";
 306                 power-domains = <&power RK3399_PD_PERIHP>;
 307                 status = "disabled";
 308         };
 309
 310         usb_host0_ohci: usb@fe3a0000 {
 311                 compatible = "generic-ohci";
 312                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 313                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 314                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 315                          <&u2phy0>;
 316                 clock-names = "usbhost", "arbiter",
 317                               "utmi";
 318                 phys = <&u2phy0_host>;
 319                 phy-names = "usb";
 320                 power-domains = <&power RK3399_PD_PERIHP>;
 321                 status = "disabled";
 322         };
 323
 324         usb_host1_ehci: usb@fe3c0000 {
 325                 compatible = "generic-ehci";
 326                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 327                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 328                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 329                          <&u2phy1>;
 330                 clock-names = "usbhost", "arbiter",
 331                               "utmi";
 332                 phys = <&u2phy1_host>;
 333                 phy-names = "usb";
 334                 power-domains = <&power RK3399_PD_PERIHP>;
 335                 status = "disabled";
 336         };
 337
 338         usb_host1_ohci: usb@fe3e0000 {
 339                 compatible = "generic-ohci";
 340                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 341                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 342                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 343                          <&u2phy1>;
 344                 clock-names = "usbhost", "arbiter",
 345                               "utmi";
 346                 phys = <&u2phy1_host>;
 347                 phy-names = "usb";
 348                 power-domains = <&power RK3399_PD_PERIHP>;
 349                 status = "disabled";
 350         };
 351
 352         dwc3_typec0: usb@fe800000 {
 353                 compatible = "rockchip,rk3399-xhci";
 354                 reg = <0x0 0xfe800000 0x0 0x100000>;
 355                 status = "disabled";
 356                 snps,dis-enblslpm-quirk;
 357                 snps,phyif-utmi-bits = <16>;
 358                 snps,dis-u2-freeclk-exists-quirk;
 359                 snps,dis-u2-susphy-quirk;
 360
 361                 #address-cells = <2>;
 362                 #size-cells = <2>;
 363                 hub {
 364                         compatible = "usb-hub";
 365                         usb,device-class = <USB_CLASS_HUB>;
 366                 };
 367                 typec_phy0 {
 368                         compatible = "rockchip,rk3399-usb3-phy";
 369                         reg = <0x0 0xff7c0000 0x0 0x40000>;
 370                 };
 371         };
 372
 373         dwc3_typec1: usb@fe900000 {
 374                 compatible = "rockchip,rk3399-xhci";
 375                 reg = <0x0 0xfe900000 0x0 0x100000>;
 376                 status = "disabled";
 377                 snps,dis-enblslpm-quirk;
 378                 snps,phyif-utmi-bits = <16>;
 379                 snps,dis-u2-freeclk-exists-quirk;
 380                 snps,dis-u2-susphy-quirk;
 381
 382                 #address-cells = <2>;
 383                 #size-cells = <2>;
 384                 hub {
 385                         compatible = "usb-hub";
 386                         usb,device-class = <USB_CLASS_HUB>;
 387                 };
 388                 typec_phy1 {
 389                         compatible = "rockchip,rk3399-usb3-phy";
 390                         reg = <0x0 0xff800000 0x0 0x40000>;
 391                 };
 392         };
 393
 394         gic: interrupt-controller@fee00000 {
 395                 compatible = "arm,gic-v3";
 396                 #interrupt-cells = <4>;
 397                 #address-cells = <2>;
 398                 #size-cells = <2>;
 399                 ranges;
 400                 interrupt-controller;
 401
 402                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 403                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 404                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 405                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 406                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 407                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 408                 its: interrupt-controller@fee20000 {
 409                         compatible = "arm,gic-v3-its";
 410                         msi-controller;
 411                         reg = <0x0 0xfee20000 0x0 0x20000>;
 412                 };
 413
 414                 ppi-partitions {
 415                         ppi_cluster0: interrupt-partition-0 {
 416                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 417                         };
 418
 419                         ppi_cluster1: interrupt-partition-1 {
 420                                 affinity = <&cpu_b0 &cpu_b1>;
 421                         };
 422                 };
 423         };
 424
 425         saradc: saradc@ff100000 {
 426                 compatible = "rockchip,rk3399-saradc";
 427                 reg = <0x0 0xff100000 0x0 0x100>;
 428                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 429                 #io-channel-cells = <1>;
 430                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 431                 clock-names = "saradc", "apb_pclk";
 432                 resets = <&cru SRST_P_SARADC>;
 433                 reset-names = "saradc-apb";
 434                 status = "disabled";
 435         };
 436
 437         i2c1: i2c@ff110000 {
 438                 compatible = "rockchip,rk3399-i2c";
 439                 reg = <0x0 0xff110000 0x0 0x1000>;
 440                 assigned-clocks = <&cru SCLK_I2C1>;
 441                 assigned-clock-rates = <200000000>;
 442                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 443                 clock-names = "i2c", "pclk";
 444                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 445                 pinctrl-names = "default";
 446                 pinctrl-0 = <&i2c1_xfer>;
 447                 #address-cells = <1>;
 448                 #size-cells = <0>;
 449                 status = "disabled";
 450         };
 451
 452         i2c2: i2c@ff120000 {
 453                 compatible = "rockchip,rk3399-i2c";
 454                 reg = <0x0 0xff120000 0x0 0x1000>;
 455                 assigned-clocks = <&cru SCLK_I2C2>;
 456                 assigned-clock-rates = <200000000>;
 457                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 458                 clock-names = "i2c", "pclk";
 459                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 460                 pinctrl-names = "default";
 461                 pinctrl-0 = <&i2c2_xfer>;
 462                 #address-cells = <1>;
 463                 #size-cells = <0>;
 464                 status = "disabled";
 465         };
 466
 467         i2c3: i2c@ff130000 {
 468                 compatible = "rockchip,rk3399-i2c";
 469                 reg = <0x0 0xff130000 0x0 0x1000>;
 470                 assigned-clocks = <&cru SCLK_I2C3>;
 471                 assigned-clock-rates = <200000000>;
 472                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 473                 clock-names = "i2c", "pclk";
 474                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 475                 pinctrl-names = "default";
 476                 pinctrl-0 = <&i2c3_xfer>;
 477                 #address-cells = <1>;
 478                 #size-cells = <0>;
 479                 status = "disabled";
 480         };
 481
 482         i2c5: i2c@ff140000 {
 483                 compatible = "rockchip,rk3399-i2c";
 484                 reg = <0x0 0xff140000 0x0 0x1000>;
 485                 assigned-clocks = <&cru SCLK_I2C5>;
 486                 assigned-clock-rates = <200000000>;
 487                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 488                 clock-names = "i2c", "pclk";
 489                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 490                 pinctrl-names = "default";
 491                 pinctrl-0 = <&i2c5_xfer>;
 492                 #address-cells = <1>;
 493                 #size-cells = <0>;
 494                 status = "disabled";
 495         };
 496
 497         i2c6: i2c@ff150000 {
 498                 compatible = "rockchip,rk3399-i2c";
 499                 reg = <0x0 0xff150000 0x0 0x1000>;
 500                 assigned-clocks = <&cru SCLK_I2C6>;
 501                 assigned-clock-rates = <200000000>;
 502                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 503                 clock-names = "i2c", "pclk";
 504                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 505                 pinctrl-names = "default";
 506                 pinctrl-0 = <&i2c6_xfer>;
 507                 #address-cells = <1>;
 508                 #size-cells = <0>;
 509                 status = "disabled";
 510         };
 511
 512         i2c7: i2c@ff160000 {
 513                 compatible = "rockchip,rk3399-i2c";
 514                 reg = <0x0 0xff160000 0x0 0x1000>;
 515                 assigned-clocks = <&cru SCLK_I2C7>;
 516                 assigned-clock-rates = <200000000>;
 517                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 518                 clock-names = "i2c", "pclk";
 519                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 520                 pinctrl-names = "default";
 521                 pinctrl-0 = <&i2c7_xfer>;
 522                 #address-cells = <1>;
 523                 #size-cells = <0>;
 524                 status = "disabled";
 525         };
 526
 527         uart0: serial@ff180000 {
 528                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 529                 reg = <0x0 0xff180000 0x0 0x100>;
 530                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 531                 clock-names = "baudclk", "apb_pclk";
 532                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 533                 reg-shift = <2>;
 534                 reg-io-width = <4>;
 535                 pinctrl-names = "default";
 536                 pinctrl-0 = <&uart0_xfer>;
 537                 status = "disabled";
 538         };
 539
 540         uart1: serial@ff190000 {
 541                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 542                 reg = <0x0 0xff190000 0x0 0x100>;
 543                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 544                 clock-names = "baudclk", "apb_pclk";
 545                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 546                 reg-shift = <2>;
 547                 reg-io-width = <4>;
 548                 pinctrl-names = "default";
 549                 pinctrl-0 = <&uart1_xfer>;
 550                 status = "disabled";
 551         };
 552
 553         uart2: serial@ff1a0000 {
 554                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 555                 reg = <0x0 0xff1a0000 0x0 0x100>;
 556                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 557                 clock-names = "baudclk", "apb_pclk";
 558                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 559                 clock-frequency = <24000000>;
 560                 reg-shift = <2>;
 561                 reg-io-width = <4>;
 562                 pinctrl-names = "default";
 563                 pinctrl-0 = <&uart2c_xfer>;
 564                 status = "disabled";
 565         };
 566
 567         uart3: serial@ff1b0000 {
 568                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 569                 reg = <0x0 0xff1b0000 0x0 0x100>;
 570                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 571                 clock-names = "baudclk", "apb_pclk";
 572                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 573                 reg-shift = <2>;
 574                 reg-io-width = <4>;
 575                 pinctrl-names = "default";
 576                 pinctrl-0 = <&uart3_xfer>;
 577                 status = "disabled";
 578         };
 579
 580         spi0: spi@ff1c0000 {
 581                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 582                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 583                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 584                 clock-names = "spiclk", "apb_pclk";
 585                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 586                 pinctrl-names = "default";
 587                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 588                 #address-cells = <1>;
 589                 #size-cells = <0>;
 590                 status = "disabled";
 591         };
 592
 593         spi1: spi@ff1d0000 {
 594                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 595                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 596                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 597                 clock-names = "spiclk", "apb_pclk";
 598                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 599                 pinctrl-names = "default";
 600                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 601                 #address-cells = <1>;
 602                 #size-cells = <0>;
 603                 status = "disabled";
 604         };
 605
 606         spi2: spi@ff1e0000 {
 607                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 608                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 609                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 610                 clock-names = "spiclk", "apb_pclk";
 611                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 612                 pinctrl-names = "default";
 613                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 614                 #address-cells = <1>;
 615                 #size-cells = <0>;
 616                 status = "disabled";
 617         };
 618
 619         spi4: spi@ff1f0000 {
 620                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 621                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 622                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 623                 clock-names = "spiclk", "apb_pclk";
 624                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 625                 pinctrl-names = "default";
 626                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 627                 #address-cells = <1>;
 628                 #size-cells = <0>;
 629                 status = "disabled";
 630         };
 631
 632         spi5: spi@ff200000 {
 633                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 634                 reg = <0x0 0xff200000 0x0 0x1000>;
 635                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 636                 clock-names = "spiclk", "apb_pclk";
 637                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 638                 pinctrl-names = "default";
 639                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 640                 #address-cells = <1>;
 641                 #size-cells = <0>;
 642                 status = "disabled";
 643         };
 644
 645         thermal_zones: thermal-zones {
 646                 cpu_thermal: cpu {
 647                         polling-delay-passive = <100>;
 648                         polling-delay = <1000>;
 649
 650                         thermal-sensors = <&tsadc 0>;
 651
 652                         trips {
 653                                 cpu_alert0: cpu_alert0 {
 654                                         temperature = <70000>;
 655                                         hysteresis = <2000>;
 656                                         type = "passive";
 657                                 };
 658                                 cpu_alert1: cpu_alert1 {
 659                                         temperature = <75000>;
 660                                         hysteresis = <2000>;
 661                                         type = "passive";
 662                                 };
 663                                 cpu_crit: cpu_crit {
 664                                         temperature = <95000>;
 665                                         hysteresis = <2000>;
 666                                         type = "critical";
 667                                 };
 668                         };
 669
 670                         cooling-maps {
 671                                 map0 {
 672                                         trip = <&cpu_alert0>;
 673                                         cooling-device =
 674                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 675                                 };
 676                                 map1 {
 677                                         trip = <&cpu_alert1>;
 678                                         cooling-device =
 679                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 680                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 681                                 };
 682                         };
 683                 };
 684
 685                 gpu_thermal: gpu {
 686                         polling-delay-passive = <100>;
 687                         polling-delay = <1000>;
 688
 689                         thermal-sensors = <&tsadc 1>;
 690
 691                         trips {
 692                                 gpu_alert0: gpu_alert0 {
 693                                         temperature = <75000>;
 694                                         hysteresis = <2000>;
 695                                         type = "passive";
 696                                 };
 697                                 gpu_crit: gpu_crit {
 698                                         temperature = <95000>;
 699                                         hysteresis = <2000>;
 700                                         type = "critical";
 701                                 };
 702                         };
 703
 704                         cooling-maps {
 705                                 map0 {
 706                                         trip = <&gpu_alert0>;
 707                                         cooling-device =
 708                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 709                                 };
 710                         };
 711                 };
 712         };
 713
 714         tsadc: tsadc@ff260000 {
 715                 compatible = "rockchip,rk3399-tsadc";
 716                 reg = <0x0 0xff260000 0x0 0x100>;
 717                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 718                 assigned-clocks = <&cru SCLK_TSADC>;
 719                 assigned-clock-rates = <750000>;
 720                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 721                 clock-names = "tsadc", "apb_pclk";
 722                 resets = <&cru SRST_TSADC>;
 723                 reset-names = "tsadc-apb";
 724                 rockchip,grf = <&grf>;
 725                 rockchip,hw-tshut-temp = <95000>;
 726                 pinctrl-names = "init", "default", "sleep";
 727                 pinctrl-0 = <&otp_gpio>;
 728                 pinctrl-1 = <&otp_out>;
 729                 pinctrl-2 = <&otp_gpio>;
 730                 #thermal-sensor-cells = <1>;
 731                 status = "disabled";
 732         };
 733
 734         qos_emmc: qos@ffa58000 {
 735                 compatible = "syscon";
 736                 reg = <0x0 0xffa58000 0x0 0x20>;
 737         };
 738
 739         qos_gmac: qos@ffa5c000 {
 740                 compatible = "syscon";
 741                 reg = <0x0 0xffa5c000 0x0 0x20>;
 742         };
 743
 744         qos_pcie: qos@ffa60080 {
 745                 compatible = "syscon";
 746                 reg = <0x0 0xffa60080 0x0 0x20>;
 747         };
 748
 749         qos_usb_host0: qos@ffa60100 {
 750                 compatible = "syscon";
 751                 reg = <0x0 0xffa60100 0x0 0x20>;
 752         };
 753
 754         qos_usb_host1: qos@ffa60180 {
 755                 compatible = "syscon";
 756                 reg = <0x0 0xffa60180 0x0 0x20>;
 757         };
 758
 759         qos_usb_otg0: qos@ffa70000 {
 760                 compatible = "syscon";
 761                 reg = <0x0 0xffa70000 0x0 0x20>;
 762         };
 763
 764         qos_usb_otg1: qos@ffa70080 {
 765                 compatible = "syscon";
 766                 reg = <0x0 0xffa70080 0x0 0x20>;
 767         };
 768
 769         qos_sd: qos@ffa74000 {
 770                 compatible = "syscon";
 771                 reg = <0x0 0xffa74000 0x0 0x20>;
 772         };
 773
 774         qos_sdioaudio: qos@ffa76000 {
 775                 compatible = "syscon";
 776                 reg = <0x0 0xffa76000 0x0 0x20>;
 777         };
 778
 779         qos_hdcp: qos@ffa90000 {
 780                 compatible = "syscon";
 781                 reg = <0x0 0xffa90000 0x0 0x20>;
 782         };
 783
 784         qos_iep: qos@ffa98000 {
 785                 compatible = "syscon";
 786                 reg = <0x0 0xffa98000 0x0 0x20>;
 787         };
 788
 789         qos_isp0_m0: qos@ffaa0000 {
 790                 compatible = "syscon";
 791                 reg = <0x0 0xffaa0000 0x0 0x20>;
 792         };
 793
 794         qos_isp0_m1: qos@ffaa0080 {
 795                 compatible = "syscon";
 796                 reg = <0x0 0xffaa0080 0x0 0x20>;
 797         };
 798
 799         qos_isp1_m0: qos@ffaa8000 {
 800                 compatible = "syscon";
 801                 reg = <0x0 0xffaa8000 0x0 0x20>;
 802         };
 803
 804         qos_isp1_m1: qos@ffaa8080 {
 805                 compatible = "syscon";
 806                 reg = <0x0 0xffaa8080 0x0 0x20>;
 807         };
 808
 809         qos_rga_r: qos@ffab0000 {
 810                 compatible = "syscon";
 811                 reg = <0x0 0xffab0000 0x0 0x20>;
 812         };
 813
 814         qos_rga_w: qos@ffab0080 {
 815                 compatible = "syscon";
 816                 reg = <0x0 0xffab0080 0x0 0x20>;
 817         };
 818
 819         qos_video_m0: qos@ffab8000 {
 820                 compatible = "syscon";
 821                 reg = <0x0 0xffab8000 0x0 0x20>;
 822         };
 823
 824         qos_video_m1_r: qos@ffac0000 {
 825                 compatible = "syscon";
 826                 reg = <0x0 0xffac0000 0x0 0x20>;
 827         };
 828
 829         qos_video_m1_w: qos@ffac0080 {
 830                 compatible = "syscon";
 831                 reg = <0x0 0xffac0080 0x0 0x20>;
 832         };
 833
 834         qos_vop_big_r: qos@ffac8000 {
 835                 compatible = "syscon";
 836                 reg = <0x0 0xffac8000 0x0 0x20>;
 837         };
 838
 839         qos_vop_big_w: qos@ffac8080 {
 840                 compatible = "syscon";
 841                 reg = <0x0 0xffac8080 0x0 0x20>;
 842         };
 843
 844         qos_vop_little: qos@ffad0000 {
 845                 compatible = "syscon";
 846                 reg = <0x0 0xffad0000 0x0 0x20>;
 847         };
 848
 849         qos_perihp: qos@ffad8080 {
 850                 compatible = "syscon";
 851                 reg = <0x0 0xffad8080 0x0 0x20>;
 852         };
 853
 854         qos_gpu: qos@ffae0000 {
 855                 compatible = "syscon";
 856                 reg = <0x0 0xffae0000 0x0 0x20>;
 857         };
 858
 859         pmu: power-management@ff310000 {
 860                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 861                 reg = <0x0 0xff310000 0x0 0x1000>;
 862
 863                 /*
 864                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 865                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 866                  * Some of the power domains are grouped together for every
 867                  * voltage domain.
 868                  * The detail contents as below.
 869                  */
 870                 power: power-controller {
 871                         compatible = "rockchip,rk3399-power-controller";
 872                         #power-domain-cells = <1>;
 873                         #address-cells = <1>;
 874                         #size-cells = <0>;
 875
 876                         /* These power domains are grouped by VD_CENTER */
 877                         pd_iep@RK3399_PD_IEP {
 878                                 reg = <RK3399_PD_IEP>;
 879                                 clocks = <&cru ACLK_IEP>,
 880                                          <&cru HCLK_IEP>;
 881                                 pm_qos = <&qos_iep>;
 882                         };
 883                         pd_rga@RK3399_PD_RGA {
 884                                 reg = <RK3399_PD_RGA>;
 885                                 clocks = <&cru ACLK_RGA>,
 886                                          <&cru HCLK_RGA>;
 887                                 pm_qos = <&qos_rga_r>,
 888                                          <&qos_rga_w>;
 889                         };
 890                         pd_vcodec@RK3399_PD_VCODEC {
 891                                 reg = <RK3399_PD_VCODEC>;
 892                                 clocks = <&cru ACLK_VCODEC>,
 893                                          <&cru HCLK_VCODEC>;
 894                                 pm_qos = <&qos_video_m0>;
 895                         };
 896                         pd_vdu@RK3399_PD_VDU {
 897                                 reg = <RK3399_PD_VDU>;
 898                                 clocks = <&cru ACLK_VDU>,
 899                                          <&cru HCLK_VDU>;
 900                                 pm_qos = <&qos_video_m1_r>,
 901                                          <&qos_video_m1_w>;
 902                         };
 903
 904                         /* These power domains are grouped by VD_GPU */
 905                         pd_gpu@RK3399_PD_GPU {
 906                                 reg = <RK3399_PD_GPU>;
 907                                 clocks = <&cru ACLK_GPU>;
 908                                 pm_qos = <&qos_gpu>;
 909                         };
 910
 911                         /* These power domains are grouped by VD_LOGIC */
 912                         pd_edp@RK3399_PD_EDP {
 913                                 reg = <RK3399_PD_EDP>;
 914                                 clocks = <&cru PCLK_EDP_CTRL>;
 915                         };
 916                         pd_emmc@RK3399_PD_EMMC {
 917                                 reg = <RK3399_PD_EMMC>;
 918                                 clocks = <&cru ACLK_EMMC>;
 919                                 pm_qos = <&qos_emmc>;
 920                         };
 921                         pd_gmac@RK3399_PD_GMAC {
 922                                 reg = <RK3399_PD_GMAC>;
 923                                 clocks = <&cru ACLK_GMAC>,
 924                                          <&cru PCLK_GMAC>;
 925                                 pm_qos = <&qos_gmac>;
 926                         };
 927                         pd_perihp@RK3399_PD_PERIHP {
 928                                 reg = <RK3399_PD_PERIHP>;
 929                                 #address-cells = <1>;
 930                                 #size-cells = <0>;
 931                                 clocks = <&cru ACLK_PERIHP>;
 932                                 pm_qos = <&qos_perihp>,
 933                                          <&qos_pcie>,
 934                                          <&qos_usb_host0>,
 935                                          <&qos_usb_host1>;
 936
 937                                 pd_sd@RK3399_PD_SD {
 938                                         reg = <RK3399_PD_SD>;
 939                                         clocks = <&cru HCLK_SDMMC>,
 940                                                  <&cru SCLK_SDMMC>;
 941                                         pm_qos = <&qos_sd>;
 942                                 };
 943                         };
 944                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
 945                                 reg = <RK3399_PD_SDIOAUDIO>;
 946                                 clocks = <&cru HCLK_SDIO>;
 947                                 pm_qos = <&qos_sdioaudio>;
 948                         };
 949                         pd_usb3@RK3399_PD_USB3 {
 950                                 reg = <RK3399_PD_USB3>;
 951                                 clocks = <&cru ACLK_USB3>;
 952                                 pm_qos = <&qos_usb_otg0>,
 953                                          <&qos_usb_otg1>;
 954                         };
 955                         pd_vio@RK3399_PD_VIO {
 956                                 reg = <RK3399_PD_VIO>;
 957                                 #address-cells = <1>;
 958                                 #size-cells = <0>;
 959
 960                                 pd_hdcp@RK3399_PD_HDCP {
 961                                         reg = <RK3399_PD_HDCP>;
 962                                         clocks = <&cru ACLK_HDCP>,
 963                                                  <&cru HCLK_HDCP>,
 964                                                  <&cru PCLK_HDCP>;
 965                                         pm_qos = <&qos_hdcp>;
 966                                 };
 967                                 pd_isp0@RK3399_PD_ISP0 {
 968                                         reg = <RK3399_PD_ISP0>;
 969                                         clocks = <&cru ACLK_ISP0>,
 970                                                  <&cru HCLK_ISP0>;
 971                                         pm_qos = <&qos_isp0_m0>,
 972                                                  <&qos_isp0_m1>;
 973                                 };
 974                                 pd_isp1@RK3399_PD_ISP1 {
 975                                         reg = <RK3399_PD_ISP1>;
 976                                         clocks = <&cru ACLK_ISP1>,
 977                                                  <&cru HCLK_ISP1>;
 978                                         pm_qos = <&qos_isp1_m0>,
 979                                                  <&qos_isp1_m1>;
 980                                 };
 981                                 pd_tcpc0@RK3399_PD_TCPC0 {
 982                                         reg = <RK3399_PD_TCPD0>;
 983                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
 984                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
 985                                 };
 986                                 pd_tcpc1@RK3399_PD_TCPC1 {
 987                                         reg = <RK3399_PD_TCPD1>;
 988                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
 989                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
 990                                 };
 991                                 pd_vo@RK3399_PD_VO {
 992                                         reg = <RK3399_PD_VO>;
 993                                         #address-cells = <1>;
 994                                         #size-cells = <0>;
 995
 996                                         pd_vopb@RK3399_PD_VOPB {
 997                                                 reg = <RK3399_PD_VOPB>;
 998                                                 clocks = <&cru ACLK_VOP0>,
 999                                                          <&cru HCLK_VOP0>;
1000                                                 pm_qos = <&qos_vop_big_r>,
1001                                                          <&qos_vop_big_w>;
1002                                         };
1003                                         pd_vopl@RK3399_PD_VOPL {
1004                                                 reg = <RK3399_PD_VOPL>;
1005                                                 clocks = <&cru ACLK_VOP1>,
1006                                                          <&cru HCLK_VOP1>;
1007                                                 pm_qos = <&qos_vop_little>;
1008                                         };
1009                                 };
1010                         };
1011                 };
1012         };
1013
1014         pmugrf: syscon@ff320000 {
1015                 u-boot,dm-pre-reloc;
1016                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1017                 reg = <0x0 0xff320000 0x0 0x1000>;
1018                 #address-cells = <1>;
1019                 #size-cells = <1>;
1020
1021                 pmu_io_domains: io-domains {
1022                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1023                         status = "disabled";
1024                 };
1025         };
1026
1027         pmusgrf: syscon@ff330000 {
1028                 u-boot,dm-pre-reloc;
1029                 compatible = "rockchip,rk3399-pmusgrf", "syscon";
1030                 reg = <0x0 0xff330000 0x0 0xe3d4>;
1031         };
1032
1033         spi3: spi@ff350000 {
1034                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1035                 reg = <0x0 0xff350000 0x0 0x1000>;
1036                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1037                 clock-names = "spiclk", "apb_pclk";
1038                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1039                 pinctrl-names = "default";
1040                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1041                 #address-cells = <1>;
1042                 #size-cells = <0>;
1043                 status = "disabled";
1044         };
1045
1046         uart4: serial@ff370000 {
1047                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1048                 reg = <0x0 0xff370000 0x0 0x100>;
1049                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1050                 clock-names = "baudclk", "apb_pclk";
1051                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1052                 reg-shift = <2>;
1053                 reg-io-width = <4>;
1054                 pinctrl-names = "default";
1055                 pinctrl-0 = <&uart4_xfer>;
1056                 status = "disabled";
1057         };
1058
1059         i2c4: i2c@ff3d0000 {
1060                 compatible = "rockchip,rk3399-i2c";
1061                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1062                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1063                 assigned-clock-rates = <200000000>;
1064                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1065                 clock-names = "i2c", "pclk";
1066                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1067                 pinctrl-names = "default";
1068                 pinctrl-0 = <&i2c4_xfer>;
1069                 #address-cells = <1>;
1070                 #size-cells = <0>;
1071                 status = "disabled";
1072         };
1073
1074         i2c8: i2c@ff3e0000 {
1075                 compatible = "rockchip,rk3399-i2c";
1076                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1077                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1078                 assigned-clock-rates = <200000000>;
1079                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1080                 clock-names = "i2c", "pclk";
1081                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1082                 pinctrl-names = "default";
1083                 pinctrl-0 = <&i2c8_xfer>;
1084                 #address-cells = <1>;
1085                 #size-cells = <0>;
1086                 status = "disabled";
1087         };
1088
1089         pwm0: pwm@ff420000 {
1090                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1091                 reg = <0x0 0xff420000 0x0 0x10>;
1092                 #pwm-cells = <3>;
1093                 pinctrl-names = "default";
1094                 pinctrl-0 = <&pwm0_pin>;
1095                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1096                 clock-names = "pwm";
1097                 status = "disabled";
1098         };
1099
1100         pwm1: pwm@ff420010 {
1101                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1102                 reg = <0x0 0xff420010 0x0 0x10>;
1103                 #pwm-cells = <3>;
1104                 pinctrl-names = "default";
1105                 pinctrl-0 = <&pwm1_pin>;
1106                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1107                 clock-names = "pwm";
1108                 status = "disabled";
1109         };
1110
1111         pwm2: pwm@ff420020 {
1112                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1113                 reg = <0x0 0xff420020 0x0 0x10>;
1114                 #pwm-cells = <3>;
1115                 pinctrl-names = "default";
1116                 pinctrl-0 = <&pwm2_pin>;
1117                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1118                 clock-names = "pwm";
1119                 status = "disabled";
1120         };
1121
1122         pwm3: pwm@ff420030 {
1123                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1124                 reg = <0x0 0xff420030 0x0 0x10>;
1125                 #pwm-cells = <3>;
1126                 pinctrl-names = "default";
1127                 pinctrl-0 = <&pwm3a_pin>;
1128                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1129                 clock-names = "pwm";
1130                 status = "disabled";
1131         };
1132
1133         cic: syscon@ff620000 {
1134                 u-boot,dm-pre-reloc;
1135                 compatible = "rockchip,rk3399-cic", "syscon";
1136                 reg = <0x0 0xff620000 0x0 0x100>;
1137         };
1138
1139         dfi: dfi@ff630000 {
1140                 reg = <0x00 0xff630000 0x00 0x4000>;
1141                 compatible = "rockchip,rk3399-dfi";
1142                 rockchip,pmu = <&pmugrf>;
1143                 clocks = <&cru PCLK_DDR_MON>;
1144                 clock-names = "pclk_ddr_mon";
1145                 status = "disabled";
1146         };
1147
1148         dmc: dmc {
1149                 u-boot,dm-pre-reloc;
1150                 compatible = "rockchip,rk3399-dmc";
1151                 devfreq-events = <&dfi>;
1152                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1153                 clocks = <&cru SCLK_DDRCLK>;
1154                 clock-names = "dmc_clk";
1155                 reg = <0x0 0xffa80000 0x0 0x0800
1156                        0x0 0xffa80800 0x0 0x1800
1157                        0x0 0xffa82000 0x0 0x2000
1158                        0x0 0xffa84000 0x0 0x1000
1159                        0x0 0xffa88000 0x0 0x0800
1160                        0x0 0xffa88800 0x0 0x1800
1161                        0x0 0xffa8a000 0x0 0x2000
1162                        0x0 0xffa8c000 0x0 0x1000>;
1163         };
1164
1165         efuse0: efuse@ff690000 {
1166                 compatible = "rockchip,rk3399-efuse";
1167                 reg = <0x0 0xff690000 0x0 0x80>;
1168                 #address-cells = <1>;
1169                 #size-cells = <1>;
1170                 clocks = <&cru PCLK_EFUSE1024NS>;
1171                 clock-names = "pclk_efuse";
1172
1173                 /* Data cells */
1174                 cpu_id: cpu-id@7 {
1175                         reg = <0x07 0x10>;
1176                 };
1177                 cpub_leakage: cpu-leakage@17 {
1178                         reg = <0x17 0x1>;
1179                 };
1180                 gpu_leakage: gpu-leakage@18 {
1181                         reg = <0x18 0x1>;
1182                 };
1183                 center_leakage: center-leakage@19 {
1184                         reg = <0x19 0x1>;
1185                 };
1186                 cpul_leakage: cpu-leakage@1a {
1187                         reg = <0x1a 0x1>;
1188                 };
1189                 logic_leakage: logic-leakage@1b {
1190                         reg = <0x1b 0x1>;
1191                 };
1192                 wafer_info: wafer-info@1c {
1193                         reg = <0x1c 0x1>;
1194                 };
1195         };
1196
1197         pmucru: pmu-clock-controller@ff750000 {
1198                 u-boot,dm-pre-reloc;
1199                 compatible = "rockchip,rk3399-pmucru";
1200                 reg = <0x0 0xff750000 0x0 0x1000>;
1201                 rockchip,grf = <&pmugrf>;
1202                 #clock-cells = <1>;
1203                 #reset-cells = <1>;
1204                 assigned-clocks = <&pmucru PLL_PPLL>;
1205                 assigned-clock-rates = <676000000>;
1206         };
1207
1208         cru: clock-controller@ff760000 {
1209                 u-boot,dm-pre-reloc;
1210                 compatible = "rockchip,rk3399-cru";
1211                 reg = <0x0 0xff760000 0x0 0x1000>;
1212                 rockchip,grf = <&grf>;
1213                 #clock-cells = <1>;
1214                 #reset-cells = <1>;
1215                 assigned-clocks =
1216                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1217                         <&cru PLL_NPLL>,
1218                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1219                         <&cru PCLK_PERIHP>,
1220                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1221                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1222                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1223                 assigned-clock-rates =
1224                          <594000000>,  <800000000>,
1225                         <1000000000>,
1226                          <150000000>,   <75000000>,
1227                           <37500000>,
1228                          <100000000>,  <100000000>,
1229                           <50000000>, <600000000>,
1230                          <100000000>,   <50000000>;
1231         };
1232
1233         grf: syscon@ff770000 {
1234                 u-boot,dm-pre-reloc;
1235                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1236                 reg = <0x0 0xff770000 0x0 0x10000>;
1237                 #address-cells = <1>;
1238                 #size-cells = <1>;
1239
1240                 io_domains: io-domains {
1241                         compatible = "rockchip,rk3399-io-voltage-domain";
1242                         status = "disabled";
1243                 };
1244
1245                 u2phy0: usb2-phy@e450 {
1246                         compatible = "rockchip,rk3399-usb2phy";
1247                         reg = <0xe450 0x10>;
1248                         clocks = <&cru SCLK_USB2PHY0_REF>;
1249                         clock-names = "phyclk";
1250                         #clock-cells = <0>;
1251                         clock-output-names = "clk_usbphy0_480m";
1252                         status = "disabled";
1253
1254                         u2phy0_host: host-port {
1255                                 #phy-cells = <0>;
1256                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1257                                 interrupt-names = "linestate";
1258                                 status = "disabled";
1259                         };
1260
1261                         u2phy0_otg: otg-port {
1262                                 #phy-cells = <0>;
1263                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1264                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1265                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1266                                 interrupt-names = "otg-bvalid", "otg-id",
1267                                                   "linestate";
1268                                 status = "disabled";
1269                         };
1270                 };
1271
1272                 u2phy1: usb2-phy@e460 {
1273                         compatible = "rockchip,rk3399-usb2phy";
1274                         reg = <0xe460 0x10>;
1275                         clocks = <&cru SCLK_USB2PHY1_REF>;
1276                         clock-names = "phyclk";
1277                         #clock-cells = <0>;
1278                         clock-output-names = "clk_usbphy1_480m";
1279                         status = "disabled";
1280
1281                         u2phy1_host: host-port {
1282                                 #phy-cells = <0>;
1283                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1284                                 interrupt-names = "linestate";
1285                                 status = "disabled";
1286                         };
1287
1288                         u2phy1_otg: otg-port {
1289                                 #phy-cells = <0>;
1290                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1291                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1292                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1293                                 interrupt-names = "otg-bvalid", "otg-id",
1294                                                   "linestate";
1295                                 status = "disabled";
1296                         };
1297                 };
1298
1299                 emmc_phy: phy@f780 {
1300                         compatible = "rockchip,rk3399-emmc-phy";
1301                         reg = <0xf780 0x24>;
1302                         clocks = <&sdhci>;
1303                         clock-names = "emmcclk";
1304                         #phy-cells = <0>;
1305                         status = "disabled";
1306                 };
1307
1308                 pcie_phy: pcie-phy {
1309                         compatible = "rockchip,rk3399-pcie-phy";
1310                         clocks = <&cru SCLK_PCIEPHY_REF>;
1311                         clock-names = "refclk";
1312                         #phy-cells = <0>;
1313                         resets = <&cru SRST_PCIEPHY>;
1314                         reset-names = "phy";
1315                         status = "disabled";
1316                 };
1317         };
1318
1319         watchdog@ff848000 {
1320                 compatible = "snps,dw-wdt";
1321                 reg = <0x0 0xff848000 0x0 0x100>;
1322                 clocks = <&cru PCLK_WDT>;
1323                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1324         };
1325
1326         rktimer: rktimer@ff850000 {
1327                 compatible = "rockchip,rk3399-timer";
1328                 reg = <0x0 0xff850000 0x0 0x1000>;
1329                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1330                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1331                 clock-names = "pclk", "timer";
1332         };
1333
1334         spdif: spdif@ff870000 {
1335                 compatible = "rockchip,rk3399-spdif";
1336                 reg = <0x0 0xff870000 0x0 0x1000>;
1337                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1338                 dmas = <&dmac_bus 7>;
1339                 dma-names = "tx";
1340                 clock-names = "mclk", "hclk";
1341                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1342                 pinctrl-names = "default";
1343                 pinctrl-0 = <&spdif_bus>;
1344                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1345                 status = "disabled";
1346         };
1347
1348         i2s0: i2s@ff880000 {
1349                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1350                 reg = <0x0 0xff880000 0x0 0x1000>;
1351                 rockchip,grf = <&grf>;
1352                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1353                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1354                 dma-names = "tx", "rx";
1355                 clock-names = "i2s_clk", "i2s_hclk";
1356                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1357                 pinctrl-names = "default";
1358                 pinctrl-0 = <&i2s0_8ch_bus>;
1359                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1360                 status = "disabled";
1361         };
1362
1363         i2s1: i2s@ff890000 {
1364                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1365                 reg = <0x0 0xff890000 0x0 0x1000>;
1366                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1367                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1368                 dma-names = "tx", "rx";
1369                 clock-names = "i2s_clk", "i2s_hclk";
1370                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1371                 pinctrl-names = "default";
1372                 pinctrl-0 = <&i2s1_2ch_bus>;
1373                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1374                 status = "disabled";
1375         };
1376
1377         i2s2: i2s@ff8a0000 {
1378                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1379                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1380                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1381                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1382                 dma-names = "tx", "rx";
1383                 clock-names = "i2s_clk", "i2s_hclk";
1384                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1385                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1386                 status = "disabled";
1387         };
1388
1389         i2c0: i2c@ff3c0000 {
1390                 compatible = "rockchip,rk3399-i2c";
1391                 reg = <0x0 0xff3c0000 0x0 0x1000>;
1392                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1393                 assigned-clock-rates = <200000000>;
1394                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1395                 clock-names = "i2c", "pclk";
1396                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1397                 pinctrl-names = "default";
1398                 pinctrl-0 = <&i2c0_xfer>;
1399                 #address-cells = <1>;
1400                 #size-cells = <0>;
1401                 status = "disabled";
1402         };
1403
1404         vopl: vop@ff8f0000 {
1405                 u-boot,dm-pre-reloc;
1406                 compatible = "rockchip,rk3399-vop-lit";
1407                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1408                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1409                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1410                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1411                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1412                 reset-names = "axi", "ahb", "dclk";
1413                 status = "disabled";
1414                 vopl_out: port {
1415                         #address-cells = <1>;
1416                         #size-cells = <0>;
1417                         vopl_out_mipi: endpoint@0 {
1418                                 reg = <3>;
1419                                 remote-endpoint = <&mipi_in_vopl>;
1420                         };
1421
1422                         vopl_out_hdmi: endpoint@1 {
1423                                 reg = <1>;
1424                                 remote-endpoint = <&hdmi_in_vopl>;
1425                         };
1426                 };
1427         };
1428
1429         vopb: vop@ff900000 {
1430                 u-boot,dm-pre-reloc;
1431                 compatible = "rockchip,rk3399-vop-big";
1432                 reg = <0x0 0xff900000 0x0 0x3efc>;
1433                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1434                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1435                 #clock-cells = <0>;
1436                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1437                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1438                 reset-names = "axi", "ahb", "dclk";
1439                 status = "disabled";
1440                 vopb_out: port {
1441                         #address-cells = <1>;
1442                         #size-cells = <0>;
1443                         vopb_out_mipi: endpoint@0 {
1444                                 reg = <3>;
1445                                 remote-endpoint = <&mipi_in_vopb>;
1446                         };
1447
1448                         vopb_out_hdmi: endpoint@1 {
1449                                 reg = <1>;
1450                                 remote-endpoint = <&hdmi_in_vopb>;
1451                         };
1452                 };
1453         };
1454
1455         hdmi: hdmi@ff940000 {
1456                 compatible = "rockchip,rk3399-dw-hdmi";
1457                 reg = <0x0 0xff940000 0x0 0x20000>;
1458                 reg-io-width = <4>;
1459                 rockchip,grf = <&grf>;
1460                 pinctrl-names = "default";
1461                 pinctrl-0 = <&hdmi_i2c_xfer>;
1462                 power-domains = <&power RK3399_PD_HDCP>;
1463                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1464                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
1465                 clock-names = "iahb", "isfr", "vpll", "grf";
1466                 status = "disabled";
1467
1468                 ports {
1469                         hdmi_in: port {
1470                                 #address-cells = <1>;
1471                                 #size-cells = <0>;
1472                                 hdmi_in_vopb: endpoint@0 {
1473                                         reg = <0>;
1474                                         remote-endpoint = <&vopb_out_hdmi>;
1475                                 };
1476                                 hdmi_in_vopl: endpoint@1 {
1477                                         reg = <1>;
1478                                         remote-endpoint = <&vopl_out_hdmi>;
1479                                 };
1480                         };
1481                 };
1482         };
1483
1484         mipi_dsi: mipi@ff960000 {
1485                 compatible = "rockchip,rk3399_mipi_dsi";
1486                 reg = <0x0 0xff960000 0x0 0x8000>;
1487                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1488                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1489                          <&cru SCLK_DPHY_TX0_CFG>;
1490                 clock-names = "ref", "pclk", "phy_cfg";
1491                 rockchip,grf = <&grf>;
1492                 #address-cells = <1>;
1493                 #size-cells = <0>;
1494                 status = "disabled";
1495                 ports {
1496                         #address-cells = <1>;
1497                         #size-cells = <0>;
1498                         reg = <1>;
1499                         mipi_in: port {
1500                                 #address-cells = <1>;
1501                                 #size-cells = <0>;
1502                                 mipi_in_vopb: endpoint@0 {
1503                                         reg = <0>;
1504                                         remote-endpoint = <&vopb_out_mipi>;
1505                                 };
1506                                 mipi_in_vopl: endpoint@1 {
1507                                         reg = <1>;
1508                                         remote-endpoint = <&vopl_out_mipi>;
1509                                 };
1510                         };
1511                 };
1512         };
1513
1514         pinctrl: pinctrl {
1515                 u-boot,dm-pre-reloc;
1516                 compatible = "rockchip,rk3399-pinctrl";
1517                 rockchip,grf = <&grf>;
1518                 rockchip,pmu = <&pmugrf>;
1519                 #address-cells = <2>;
1520                 #size-cells = <2>;
1521                 ranges;
1522
1523                 gpio0: gpio0@ff720000 {
1524                         compatible = "rockchip,gpio-bank";
1525                         reg = <0x0 0xff720000 0x0 0x100>;
1526                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1527                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1528
1529                         gpio-controller;
1530                         #gpio-cells = <0x2>;
1531
1532                         interrupt-controller;
1533                         #interrupt-cells = <0x2>;
1534                 };
1535
1536                 gpio1: gpio1@ff730000 {
1537                         compatible = "rockchip,gpio-bank";
1538                         reg = <0x0 0xff730000 0x0 0x100>;
1539                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1540                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1541
1542                         gpio-controller;
1543                         #gpio-cells = <0x2>;
1544
1545                         interrupt-controller;
1546                         #interrupt-cells = <0x2>;
1547                 };
1548
1549                 gpio2: gpio2@ff780000 {
1550                         compatible = "rockchip,gpio-bank";
1551                         reg = <0x0 0xff780000 0x0 0x100>;
1552                         clocks = <&cru PCLK_GPIO2>;
1553                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1554
1555                         gpio-controller;
1556                         #gpio-cells = <0x2>;
1557
1558                         interrupt-controller;
1559                         #interrupt-cells = <0x2>;
1560                 };
1561
1562                 gpio3: gpio3@ff788000 {
1563                         compatible = "rockchip,gpio-bank";
1564                         reg = <0x0 0xff788000 0x0 0x100>;
1565                         clocks = <&cru PCLK_GPIO3>;
1566                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1567
1568                         gpio-controller;
1569                         #gpio-cells = <0x2>;
1570
1571                         interrupt-controller;
1572                         #interrupt-cells = <0x2>;
1573                 };
1574
1575                 gpio4: gpio4@ff790000 {
1576                         compatible = "rockchip,gpio-bank";
1577                         reg = <0x0 0xff790000 0x0 0x100>;
1578                         clocks = <&cru PCLK_GPIO4>;
1579                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1580
1581                         gpio-controller;
1582                         #gpio-cells = <0x2>;
1583
1584                         interrupt-controller;
1585                         #interrupt-cells = <0x2>;
1586                 };
1587
1588                 pcfg_pull_up: pcfg-pull-up {
1589                         bias-pull-up;
1590                 };
1591
1592                 pcfg_pull_down: pcfg-pull-down {
1593                         bias-pull-down;
1594                 };
1595
1596                 pcfg_pull_none: pcfg-pull-none {
1597                         bias-disable;
1598                 };
1599
1600                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1601                         bias-disable;
1602                         drive-strength = <12>;
1603                 };
1604
1605                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1606                         bias-pull-up;
1607                         drive-strength = <8>;
1608                 };
1609
1610                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1611                         bias-pull-down;
1612                         drive-strength = <4>;
1613                 };
1614
1615                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1616                         bias-pull-up;
1617                         drive-strength = <2>;
1618                 };
1619
1620                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1621                         bias-pull-down;
1622                         drive-strength = <12>;
1623                 };
1624
1625                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1626                         bias-disable;
1627                         drive-strength = <13>;
1628                 };
1629
1630                 clock {
1631                         clk_32k: clk-32k {
1632                                 rockchip,pins = <0 RK_PA0 RK_FUNC_2 &pcfg_pull_none>;
1633                         };
1634                 };
1635
1636                 edp {
1637                         edp_hpd: edp-hpd {
1638                                 rockchip,pins =
1639                                         <4 RK_PC7 RK_FUNC_2 &pcfg_pull_none>;
1640                         };
1641                 };
1642
1643                 gmac {
1644                         rgmii_pins: rgmii-pins {
1645                                 rockchip,pins =
1646                                         /* mac_txclk */
1647                                         <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1648                                         /* mac_rxclk */
1649                                         <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
1650                                         /* mac_mdio */
1651                                         <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
1652                                         /* mac_txen */
1653                                         <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1654                                         /* mac_clk */
1655                                         <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
1656                                         /* mac_rxdv */
1657                                         <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
1658                                         /* mac_mdc */
1659                                         <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
1660                                         /* mac_rxd1 */
1661                                         <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
1662                                         /* mac_rxd0 */
1663                                         <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
1664                                         /* mac_txd1 */
1665                                         <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1666                                         /* mac_txd0 */
1667                                         <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1668                                         /* mac_rxd3 */
1669                                         <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
1670                                         /* mac_rxd2 */
1671                                         <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
1672                                         /* mac_txd3 */
1673                                         <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1674                                         /* mac_txd2 */
1675                                         <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1676                         };
1677
1678                         rmii_pins: rmii-pins {
1679                                 rockchip,pins =
1680                                         /* mac_mdio */
1681                                         <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
1682                                         /* mac_txen */
1683                                         <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1684                                         /* mac_clk */
1685                                         <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
1686                                         /* mac_rxer */
1687                                         <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,
1688                                         /* mac_rxdv */
1689                                         <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
1690                                         /* mac_mdc */
1691                                         <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
1692                                         /* mac_rxd1 */
1693                                         <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
1694                                         /* mac_rxd0 */
1695                                         <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
1696                                         /* mac_txd1 */
1697                                         <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1698                                         /* mac_txd0 */
1699                                         <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1700                         };
1701                 };
1702
1703                 i2c0 {
1704                         i2c0_xfer: i2c0-xfer {
1705                                 rockchip,pins =
1706                                         <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>,
1707                                         <1 RK_PC0 RK_FUNC_2 &pcfg_pull_none>;
1708                         };
1709                 };
1710
1711                 i2c1 {
1712                         i2c1_xfer: i2c1-xfer {
1713                                 rockchip,pins =
1714                                         <4 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
1715                                         <4 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
1716                         };
1717                 };
1718
1719                 i2c2 {
1720                         i2c2_xfer: i2c2-xfer {
1721                                 rockchip,pins =
1722                                         <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1723                                         <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1724                         };
1725                 };
1726
1727                 i2c3 {
1728                         i2c3_xfer: i2c3-xfer {
1729                                 rockchip,pins =
1730                                         <4 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
1731                                         <4 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
1732                         };
1733                 };
1734
1735                 i2c4 {
1736                         i2c4_xfer: i2c4-xfer {
1737                                 rockchip,pins =
1738                                         <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
1739                                         <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
1740                         };
1741                 };
1742
1743                 i2c5 {
1744                         i2c5_xfer: i2c5-xfer {
1745                                 rockchip,pins =
1746                                         <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>,
1747                                         <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>;
1748                         };
1749                 };
1750
1751                 i2c6 {
1752                         i2c6_xfer: i2c6-xfer {
1753                                 rockchip,pins =
1754                                         <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>,
1755                                         <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
1756                         };
1757                 };
1758
1759                 i2c7 {
1760                         i2c7_xfer: i2c7-xfer {
1761                                 rockchip,pins =
1762                                         <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>,
1763                                         <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
1764                         };
1765                 };
1766
1767                 i2c8 {
1768                         i2c8_xfer: i2c8-xfer {
1769                                 rockchip,pins =
1770                                         <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>,
1771                                         <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
1772                         };
1773                 };
1774
1775                 i2s0 {
1776                         i2s0_8ch_bus: i2s0-8ch-bus {
1777                                 rockchip,pins =
1778                                         <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
1779                                         <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
1780                                         <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>,
1781                                         <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>,
1782                                         <3 RK_PD4 RK_FUNC_1 &pcfg_pull_none>,
1783                                         <3 RK_PD5 RK_FUNC_1 &pcfg_pull_none>,
1784                                         <3 RK_PD6 RK_FUNC_1 &pcfg_pull_none>,
1785                                         <3 RK_PD7 RK_FUNC_1 &pcfg_pull_none>,
1786                                         <4 RK_PA0 RK_FUNC_1 &pcfg_pull_none>;
1787                         };
1788                 };
1789
1790                 i2s1 {
1791                         i2s1_2ch_bus: i2s1-2ch-bus {
1792                                 rockchip,pins =
1793                                         <4 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
1794                                         <4 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
1795                                         <4 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
1796                                         <4 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
1797                                         <4 RK_PA7 RK_FUNC_1 &pcfg_pull_none>;
1798                         };
1799                 };
1800
1801                 sdio0 {
1802                         sdio0_bus1: sdio0-bus1 {
1803                                 rockchip,pins =
1804                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
1805                         };
1806
1807                         sdio0_bus4: sdio0-bus4 {
1808                                 rockchip,pins =
1809                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
1810                                         <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
1811                                         <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
1812                                         <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
1813                         };
1814
1815                         sdio0_cmd: sdio0-cmd {
1816                                 rockchip,pins =
1817                                         <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
1818                         };
1819
1820                         sdio0_clk: sdio0-clk {
1821                                 rockchip,pins =
1822                                         <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
1823                         };
1824
1825                         sdio0_cd: sdio0-cd {
1826                                 rockchip,pins =
1827                                         <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
1828                         };
1829
1830                         sdio0_pwr: sdio0-pwr {
1831                                 rockchip,pins =
1832                                         <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
1833                         };
1834
1835                         sdio0_bkpwr: sdio0-bkpwr {
1836                                 rockchip,pins =
1837                                         <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
1838                         };
1839
1840                         sdio0_wp: sdio0-wp {
1841                                 rockchip,pins =
1842                                         <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
1843                         };
1844
1845                         sdio0_int: sdio0-int {
1846                                 rockchip,pins =
1847                                         <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
1848                         };
1849                 };
1850
1851                 sdmmc {
1852                         sdmmc_bus1: sdmmc-bus1 {
1853                                 rockchip,pins =
1854                                         <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
1855                         };
1856
1857                         sdmmc_bus4: sdmmc-bus4 {
1858                                 rockchip,pins =
1859                                         <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
1860                                         <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
1861                                         <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
1862                                         <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
1863                         };
1864
1865                         sdmmc_clk: sdmmc-clk {
1866                                 rockchip,pins =
1867                                         <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
1868                         };
1869
1870                         sdmmc_cmd: sdmmc-cmd {
1871                                 rockchip,pins =
1872                                         <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
1873                         };
1874
1875                         sdmmc_cd: sdmcc-cd {
1876                                 rockchip,pins =
1877                                         <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
1878                         };
1879
1880                         sdmmc_wp: sdmmc-wp {
1881                                 rockchip,pins =
1882                                         <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
1883                         };
1884                 };
1885
1886                 sleep {
1887                         ap_pwroff: ap-pwroff {
1888                                 rockchip,pins = <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
1889                         };
1890
1891                         ddrio_pwroff: ddrio-pwroff {
1892                                 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
1893                         };
1894                 };
1895
1896                 spdif {
1897                         spdif_bus: spdif-bus {
1898                                 rockchip,pins =
1899                                         <4 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1900                         };
1901
1902                         spdif_bus_1: spdif-bus-1 {
1903                                 rockchip,pins =
1904                                         <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
1905                         };
1906                 };
1907
1908                 spi0 {
1909                         spi0_clk: spi0-clk {
1910                                 rockchip,pins =
1911                                         <3 RK_PA6 RK_FUNC_2 &pcfg_pull_up>;
1912                         };
1913                         spi0_cs0: spi0-cs0 {
1914                                 rockchip,pins =
1915                                         <3 RK_PA7 RK_FUNC_2 &pcfg_pull_up>;
1916                         };
1917                         spi0_cs1: spi0-cs1 {
1918                                 rockchip,pins =
1919                                         <3 RK_PB0 RK_FUNC_2 &pcfg_pull_up>;
1920                         };
1921                         spi0_tx: spi0-tx {
1922                                 rockchip,pins =
1923                                         <3 RK_PA5 RK_FUNC_2 &pcfg_pull_up>;
1924                         };
1925                         spi0_rx: spi0-rx {
1926                                 rockchip,pins =
1927                                         <3 RK_PA4 RK_FUNC_2 &pcfg_pull_up>;
1928                         };
1929                 };
1930
1931                 spi1 {
1932                         spi1_clk: spi1-clk {
1933                                 rockchip,pins =
1934                                         <1 RK_PB1 RK_FUNC_2 &pcfg_pull_up>;
1935                         };
1936                         spi1_cs0: spi1-cs0 {
1937                                 rockchip,pins =
1938                                         <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up>;
1939                         };
1940                         spi1_rx: spi1-rx {
1941                                 rockchip,pins =
1942                                         <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up>;
1943                         };
1944                         spi1_tx: spi1-tx {
1945                                 rockchip,pins =
1946                                         <1 RK_PB0 RK_FUNC_2 &pcfg_pull_up>;
1947                         };
1948                 };
1949
1950                 spi2 {
1951                         spi2_clk: spi2-clk {
1952                                 rockchip,pins =
1953                                         <2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
1954                         };
1955                         spi2_cs0: spi2-cs0 {
1956                                 rockchip,pins =
1957                                         <2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>;
1958                         };
1959                         spi2_rx: spi2-rx {
1960                                 rockchip,pins =
1961                                         <2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>;
1962                         };
1963                         spi2_tx: spi2-tx {
1964                                 rockchip,pins =
1965                                         <2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>;
1966                         };
1967                 };
1968
1969                 spi3 {
1970                         spi3_clk: spi3-clk {
1971                                 rockchip,pins =
1972                                         <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>;
1973                         };
1974                         spi3_cs0: spi3-cs0 {
1975                                 rockchip,pins =
1976                                         <1 RK_PC2 RK_FUNC_1 &pcfg_pull_up>;
1977                         };
1978                         spi3_rx: spi3-rx {
1979                                 rockchip,pins =
1980                                         <1 RK_PB7 RK_FUNC_1 &pcfg_pull_up>;
1981                         };
1982                         spi3_tx: spi3-tx {
1983                                 rockchip,pins =
1984                                         <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up>;
1985                         };
1986                 };
1987
1988                 spi4 {
1989                         spi4_clk: spi4-clk {
1990                                 rockchip,pins =
1991                                         <3 RK_PA2 RK_FUNC_2 &pcfg_pull_up>;
1992                         };
1993                         spi4_cs0: spi4-cs0 {
1994                                 rockchip,pins =
1995                                         <3 RK_PA3 RK_FUNC_2 &pcfg_pull_up>;
1996                         };
1997                         spi4_rx: spi4-rx {
1998                                 rockchip,pins =
1999                                         <3 RK_PA0 RK_FUNC_2 &pcfg_pull_up>;
2000                         };
2001                         spi4_tx: spi4-tx {
2002                                 rockchip,pins =
2003                                         <3 RK_PA1 RK_FUNC_2 &pcfg_pull_up>;
2004                         };
2005                 };
2006
2007                 spi5 {
2008                         spi5_clk: spi5-clk {
2009                                 rockchip,pins =
2010                                         <2 RK_PC6 RK_FUNC_2 &pcfg_pull_up>;
2011                         };
2012                         spi5_cs0: spi5-cs0 {
2013                                 rockchip,pins =
2014                                         <2 RK_PC7 RK_FUNC_2 &pcfg_pull_up>;
2015                         };
2016                         spi5_rx: spi5-rx {
2017                                 rockchip,pins =
2018                                         <2 RK_PC4 RK_FUNC_2 &pcfg_pull_up>;
2019                         };
2020                         spi5_tx: spi5-tx {
2021                                 rockchip,pins =
2022                                         <2 RK_PC5 RK_FUNC_2 &pcfg_pull_up>;
2023                         };
2024                 };
2025
2026                 tsadc {
2027                         otp_gpio: otp-gpio {
2028                                 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
2029                         };
2030
2031                         otp_out: otp-out {
2032                                 rockchip,pins = <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
2033                         };
2034                 };
2035
2036                 uart0 {
2037                         uart0_xfer: uart0-xfer {
2038                                 rockchip,pins =
2039                                         <2 RK_PC0 RK_FUNC_1 &pcfg_pull_up>,
2040                                         <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
2041                         };
2042
2043                         uart0_cts: uart0-cts {
2044                                 rockchip,pins =
2045                                         <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
2046                         };
2047
2048                         uart0_rts: uart0-rts {
2049                                 rockchip,pins =
2050                                         <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
2051                         };
2052                 };
2053
2054                 uart1 {
2055                         uart1_xfer: uart1-xfer {
2056                                 rockchip,pins =
2057                                         <3 RK_PB4 RK_FUNC_2 &pcfg_pull_up>,
2058                                         <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>;
2059                         };
2060                 };
2061
2062                 uart2a {
2063                         uart2a_xfer: uart2a-xfer {
2064                                 rockchip,pins =
2065                                         <4 RK_PB0 RK_FUNC_2 &pcfg_pull_up>,
2066                                         <4 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
2067                         };
2068                 };
2069
2070                 uart2b {
2071                         uart2b_xfer: uart2b-xfer {
2072                                 rockchip,pins =
2073                                         <4 RK_PC0 RK_FUNC_2 &pcfg_pull_up>,
2074                                         <4 RK_PC1 RK_FUNC_2 &pcfg_pull_none>;
2075                         };
2076                 };
2077
2078                 uart2c {
2079                         uart2c_xfer: uart2c-xfer {
2080                                 rockchip,pins =
2081                                         <4 RK_PC3 RK_FUNC_1 &pcfg_pull_up>,
2082                                         <4 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
2083                         };
2084                 };
2085
2086                 uart3 {
2087                         uart3_xfer: uart3-xfer {
2088                                 rockchip,pins =
2089                                         <3 RK_PB6 RK_FUNC_2 &pcfg_pull_up>,
2090                                         <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>;
2091                         };
2092
2093                         uart3_cts: uart3-cts {
2094                                 rockchip,pins =
2095                                         <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
2096                         };
2097
2098                         uart3_rts: uart3-rts {
2099                                 rockchip,pins =
2100                                         <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
2101                         };
2102                 };
2103
2104                 uart4 {
2105                         uart4_xfer: uart4-xfer {
2106                                 rockchip,pins =
2107                                         <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up>,
2108                                         <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
2109                         };
2110                 };
2111
2112                 uarthdcp {
2113                         uarthdcp_xfer: uarthdcp-xfer {
2114                                 rockchip,pins =
2115                                         <4 RK_PC5 RK_FUNC_2 &pcfg_pull_up>,
2116                                         <4 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
2117                         };
2118                 };
2119
2120                 pwm0 {
2121                         pwm0_pin: pwm0-pin {
2122                                 rockchip,pins =
2123                                         <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
2124                         };
2125
2126                         vop0_pwm_pin: vop0-pwm-pin {
2127                                 rockchip,pins =
2128                                         <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
2129                         };
2130                 };
2131
2132                 pwm1 {
2133                         pwm1_pin: pwm1-pin {
2134                                 rockchip,pins =
2135                                         <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
2136                         };
2137
2138                         vop1_pwm_pin: vop1-pwm-pin {
2139                                 rockchip,pins =
2140                                         <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
2141                         };
2142                 };
2143
2144                 pwm2 {
2145                         pwm2_pin: pwm2-pin {
2146                                 rockchip,pins =
2147                                         <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
2148                         };
2149                 };
2150
2151                 pwm3a {
2152                         pwm3a_pin: pwm3a-pin {
2153                                 rockchip,pins =
2154                                         <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
2155                         };
2156                 };
2157
2158                 pwm3b {
2159                         pwm3b_pin: pwm3b-pin {
2160                                 rockchip,pins =
2161                                         <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
2162                         };
2163                 };
2164
2165                 hdmi {
2166                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2167                                 rockchip,pins =
2168                                         <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
2169                                         <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2170                         };
2171
2172                         hdmi_cec: hdmi-cec {
2173                                 rockchip,pins =
2174                                         <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
2175                         };
2176                 };
2177
2178                 pcie {
2179                         pcie_clkreqn: pci-clkreqn {
2180                                 rockchip,pins =
2181                                         <2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>;
2182                         };
2183
2184                         pcie_clkreqnb: pci-clkreqnb {
2185                                 rockchip,pins =
2186                                         <4 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
2187                         };
2188
2189                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
2190                                 rockchip,pins =
2191                                         <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2192                         };
2193
2194                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2195                                 rockchip,pins =
2196                                         <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2197                         };
2198                 };
2199
2200         };
2201 };