git.sur5r.net Git - u-boot/blob - arch/arm/dts/rk3399.dtsi

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <dt-bindings/clock/rk3399-cru.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/pinctrl/rockchip.h>
  12 #define USB_CLASS_HUB                   9
  13
  14 / {
  15         compatible = "rockchip,rk3399";
  16
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 serial0 = &uart0;
  23                 serial1 = &uart1;
  24                 serial2 = &uart2;
  25                 serial3 = &uart3;
  26                 serial4 = &uart4;
  27                 mmc0 = &sdhci;
  28                 mmc1 = &sdmmc;
  29                 i2c0 = &i2c0;
  30         };
  31
  32         cpus {
  33                 #address-cells = <2>;
  34                 #size-cells = <0>;
  35
  36                 cpu-map {
  37                         cluster0 {
  38                                 core0 {
  39                                         cpu = <&cpu_l0>;
  40                                 };
  41                                 core1 {
  42                                         cpu = <&cpu_l1>;
  43                                 };
  44                                 core2 {
  45                                         cpu = <&cpu_l2>;
  46                                 };
  47                                 core3 {
  48                                         cpu = <&cpu_l3>;
  49                                 };
  50                         };
  51
  52                         cluster1 {
  53                                 core0 {
  54                                         cpu = <&cpu_b0>;
  55                                 };
  56                                 core1 {
  57                                         cpu = <&cpu_b1>;
  58                                 };
  59                         };
  60                 };
  61
  62                 cpu_l0: cpu@0 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a53", "arm,armv8";
  65                         reg = <0x0 0x0>;
  66                         enable-method = "psci";
  67                         #cooling-cells = <2>; /* min followed by max */
  68                         clocks = <&cru ARMCLKL>;
  69                 };
  70
  71                 cpu_l1: cpu@1 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53", "arm,armv8";
  74                         reg = <0x0 0x1>;
  75                         enable-method = "psci";
  76                         clocks = <&cru ARMCLKL>;
  77                 };
  78
  79                 cpu_l2: cpu@2 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53", "arm,armv8";
  82                         reg = <0x0 0x2>;
  83                         enable-method = "psci";
  84                         clocks = <&cru ARMCLKL>;
  85                 };
  86
  87                 cpu_l3: cpu@3 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a53", "arm,armv8";
  90                         reg = <0x0 0x3>;
  91                         enable-method = "psci";
  92                         clocks = <&cru ARMCLKL>;
  93                 };
  94
  95                 cpu_b0: cpu@100 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a72", "arm,armv8";
  98                         reg = <0x0 0x100>;
  99                         enable-method = "psci";
 100                         #cooling-cells = <2>; /* min followed by max */
 101                         clocks = <&cru ARMCLKB>;
 102                 };
 103
 104                 cpu_b1: cpu@101 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a72", "arm,armv8";
 107                         reg = <0x0 0x101>;
 108                         enable-method = "psci";
 109                         clocks = <&cru ARMCLKB>;
 110                 };
 111         };
 112
 113         psci {
 114                 compatible = "arm,psci-1.0";
 115                 method = "smc";
 116         };
 117
 118         timer {
 119                 compatible = "arm,armv8-timer";
 120                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 121                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 122                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 123                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 124         };
 125
 126         xin24m: xin24m {
 127                 compatible = "fixed-clock";
 128                 clock-frequency = <24000000>;
 129                 clock-output-names = "xin24m";
 130                 #clock-cells = <0>;
 131         };
 132
 133         amba {
 134                 compatible = "simple-bus";
 135                 #address-cells = <2>;
 136                 #size-cells = <2>;
 137                 ranges;
 138
 139                 dmac_bus: dma-controller@ff6d0000 {
 140                         compatible = "arm,pl330", "arm,primecell";
 141                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 142                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 143                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 144                         #dma-cells = <1>;
 145                         clocks = <&cru ACLK_DMAC0_PERILP>;
 146                         clock-names = "apb_pclk";
 147                 };
 148
 149                 dmac_peri: dma-controller@ff6e0000 {
 150                         compatible = "arm,pl330", "arm,primecell";
 151                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 152                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 153                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 154                         #dma-cells = <1>;
 155                         clocks = <&cru ACLK_DMAC1_PERILP>;
 156                         clock-names = "apb_pclk";
 157                 };
 158         };
 159
 160         sdio0: dwmmc@fe310000 {
 161                 compatible = "rockchip,rk3399-dw-mshc",
 162                              "rockchip,rk3288-dw-mshc";
 163                 reg = <0x0 0xfe310000 0x0 0x4000>;
 164                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 165                 clock-freq-min-max = <400000 150000000>;
 166                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 167                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 168                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 169                 fifo-depth = <0x100>;
 170                 status = "disabled";
 171         };
 172
 173         sdmmc: dwmmc@fe320000 {
 174                 compatible = "rockchip,rk3399-dw-mshc",
 175                              "rockchip,rk3288-dw-mshc";
 176                 reg = <0x0 0xfe320000 0x0 0x4000>;
 177                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 178                 clock-freq-min-max = <400000 150000000>;
 179                 clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>,
 180                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 181                 clock-names = "ciu", "biu", "ciu-drive", "ciu-sample";
 182                 pinctrl-names = "default";
 183                 pinctrl-0 = <&sdmmc_clk>;
 184                 fifo-depth = <0x100>;
 185                 status = "disabled";
 186         };
 187
 188         sdhci: sdhci@fe330000 {
 189                 u-boot,dm-pre-reloc;
 190                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 191                 reg = <0x0 0xfe330000 0x0 0x10000>;
 192                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 193                 assigned-clocks = <&cru SCLK_EMMC>;
 194                 assigned-clock-rates = <200000000>;
 195                 max-frequency = <200000000>;
 196                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 197                 clock-names = "clk_xin", "clk_ahb";
 198                 phys = <&emmc_phy>;
 199                 phy-names = "phy_arasan";
 200                 status = "disabled";
 201         };
 202
 203         usb_host0_ehci: usb@fe380000 {
 204                 compatible = "generic-ehci";
 205                 reg = <0x0 0xfe380000 0x0 0x20000>;
 206                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 207                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 208                 clock-names = "hclk_host0", "hclk_host0_arb";
 209                 status = "disabled";
 210         };
 211
 212         usb_host0_ohci: usb@fe3a0000 {
 213                 compatible = "generic-ohci";
 214                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 215                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 216                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 217                 clock-names = "hclk_host0", "hclk_host0_arb";
 218                 status = "disabled";
 219         };
 220
 221         usb_host1_ehci: usb@fe3c0000 {
 222                 compatible = "generic-ehci";
 223                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 224                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 225                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 226                 clock-names = "hclk_host1", "hclk_host1_arb";
 227                 status = "disabled";
 228         };
 229
 230         usb_host1_ohci: usb@fe3e0000 {
 231                 compatible = "generic-ohci";
 232                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 233                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 234                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 235                 clock-names = "hclk_host1", "hclk_host1_arb";
 236                 status = "disabled";
 237         };
 238
 239         dwc3_typec0: usb@fe800000 {
 240                 compatible = "rockchip,rk3399-xhci";
 241                 reg = <0x0 0xfe800000 0x0 0x100000>;
 242                 status = "disabled";
 243                 snps,dis-enblslpm-quirk;
 244                 snps,phyif-utmi-bits = <16>;
 245                 snps,dis-u2-freeclk-exists-quirk;
 246                 snps,dis-u2-susphy-quirk;
 247
 248                 #address-cells = <2>;
 249                 #size-cells = <2>;
 250                 hub {
 251                         compatible = "usb-hub";
 252                         usb,device-class = <USB_CLASS_HUB>;
 253                 };
 254                 typec_phy0 {
 255                         compatible = "rockchip,rk3399-usb3-phy";
 256                         reg = <0x0 0xff7c0000 0x0 0x40000>;
 257                 };
 258         };
 259
 260         dwc3_typec1: usb@fe900000 {
 261                 compatible = "rockchip,rk3399-xhci";
 262                 reg = <0x0 0xfe900000 0x0 0x100000>;
 263                 status = "disabled";
 264                 snps,dis-enblslpm-quirk;
 265                 snps,phyif-utmi-bits = <16>;
 266                 snps,dis-u2-freeclk-exists-quirk;
 267                 snps,dis-u2-susphy-quirk;
 268
 269                 #address-cells = <2>;
 270                 #size-cells = <2>;
 271                 hub {
 272                         compatible = "usb-hub";
 273                         usb,device-class = <USB_CLASS_HUB>;
 274                 };
 275                 typec_phy1 {
 276                         compatible = "rockchip,rk3399-usb3-phy";
 277                         reg = <0x0 0xff800000 0x0 0x40000>;
 278                 };
 279         };
 280
 281         gic: interrupt-controller@fee00000 {
 282                 compatible = "arm,gic-v3";
 283                 #interrupt-cells = <3>;
 284                 #address-cells = <2>;
 285                 #size-cells = <2>;
 286                 ranges;
 287                 interrupt-controller;
 288
 289                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 290                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 291                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 292                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 293                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 294                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 295                 its: interrupt-controller@fee20000 {
 296                         compatible = "arm,gic-v3-its";
 297                         msi-controller;
 298                         reg = <0x0 0xfee20000 0x0 0x20000>;
 299                 };
 300         };
 301
 302         uart0: serial@ff180000 {
 303                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 304                 reg = <0x0 0xff180000 0x0 0x100>;
 305                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 306                 clock-names = "baudclk", "apb_pclk";
 307                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 308                 reg-shift = <2>;
 309                 reg-io-width = <4>;
 310                 pinctrl-names = "default";
 311                 pinctrl-0 = <&uart0_xfer>;
 312                 status = "disabled";
 313         };
 314
 315         uart1: serial@ff190000 {
 316                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 317                 reg = <0x0 0xff190000 0x0 0x100>;
 318                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 319                 clock-names = "baudclk", "apb_pclk";
 320                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 321                 reg-shift = <2>;
 322                 reg-io-width = <4>;
 323                 pinctrl-names = "default";
 324                 pinctrl-0 = <&uart1_xfer>;
 325                 status = "disabled";
 326         };
 327
 328         uart2: serial@ff1a0000 {
 329                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 330                 reg = <0x0 0xff1a0000 0x0 0x100>;
 331                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 332                 clock-names = "baudclk", "apb_pclk";
 333                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 334                 clock-frequency = <24000000>;
 335                 reg-shift = <2>;
 336                 reg-io-width = <4>;
 337                 pinctrl-names = "default";
 338                 pinctrl-0 = <&uart2c_xfer>;
 339                 status = "disabled";
 340         };
 341
 342         uart3: serial@ff1b0000 {
 343                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 344                 reg = <0x0 0xff1b0000 0x0 0x100>;
 345                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 346                 clock-names = "baudclk", "apb_pclk";
 347                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 348                 reg-shift = <2>;
 349                 reg-io-width = <4>;
 350                 pinctrl-names = "default";
 351                 pinctrl-0 = <&uart3_xfer>;
 352                 status = "disabled";
 353         };
 354
 355         spi0: spi@ff1c0000 {
 356                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 357                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 358                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 359                 clock-names = "spiclk", "apb_pclk";
 360                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 361                 pinctrl-names = "default";
 362                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 363                 #address-cells = <1>;
 364                 #size-cells = <0>;
 365                 status = "disabled";
 366         };
 367
 368         spi1: spi@ff1d0000 {
 369                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 370                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 371                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 372                 clock-names = "spiclk", "apb_pclk";
 373                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 374                 pinctrl-names = "default";
 375                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 376                 #address-cells = <1>;
 377                 #size-cells = <0>;
 378                 status = "disabled";
 379         };
 380
 381         spi2: spi@ff1e0000 {
 382                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 383                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 384                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 385                 clock-names = "spiclk", "apb_pclk";
 386                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 387                 pinctrl-names = "default";
 388                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 389                 #address-cells = <1>;
 390                 #size-cells = <0>;
 391                 status = "disabled";
 392         };
 393
 394         spi4: spi@ff1f0000 {
 395                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 396                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 397                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 398                 clock-names = "spiclk", "apb_pclk";
 399                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 400                 pinctrl-names = "default";
 401                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 402                 #address-cells = <1>;
 403                 #size-cells = <0>;
 404                 status = "disabled";
 405         };
 406
 407         spi5: spi@ff200000 {
 408                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 409                 reg = <0x0 0xff200000 0x0 0x1000>;
 410                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 411                 clock-names = "spiclk", "apb_pclk";
 412                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 413                 pinctrl-names = "default";
 414                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 415                 #address-cells = <1>;
 416                 #size-cells = <0>;
 417                 status = "disabled";
 418         };
 419
 420         pmugrf: syscon@ff320000 {
 421                 u-boot,dm-pre-reloc;
 422                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 423                 reg = <0x0 0xff320000 0x0 0x1000>;
 424                 #address-cells = <1>;
 425                 #size-cells = <1>;
 426
 427                 pmu_io_domains: io-domains {
 428                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
 429                         status = "disabled";
 430                 };
 431         };
 432
 433         pmusgrf: syscon@ff330000 {
 434                 u-boot,dm-pre-reloc;
 435                 compatible = "rockchip,rk3399-pmusgrf", "syscon";
 436                 reg = <0x0 0xff330000 0x0 0xe3d4>;
 437         };
 438
 439         spi3: spi@ff350000 {
 440                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 441                 reg = <0x0 0xff350000 0x0 0x1000>;
 442                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 443                 clock-names = "spiclk", "apb_pclk";
 444                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 445                 pinctrl-names = "default";
 446                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 447                 #address-cells = <1>;
 448                 #size-cells = <0>;
 449                 status = "disabled";
 450         };
 451
 452         uart4: serial@ff370000 {
 453                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 454                 reg = <0x0 0xff370000 0x0 0x100>;
 455                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 456                 clock-names = "baudclk", "apb_pclk";
 457                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 458                 reg-shift = <2>;
 459                 reg-io-width = <4>;
 460                 pinctrl-names = "default";
 461                 pinctrl-0 = <&uart4_xfer>;
 462                 status = "disabled";
 463         };
 464
 465         pwm0: pwm@ff420000 {
 466                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 467                 reg = <0x0 0xff420000 0x0 0x10>;
 468                 #pwm-cells = <3>;
 469                 pinctrl-names = "default";
 470                 pinctrl-0 = <&pwm0_pin>;
 471                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 472                 clock-names = "pwm";
 473                 status = "disabled";
 474         };
 475
 476         pwm1: pwm@ff420010 {
 477                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 478                 reg = <0x0 0xff420010 0x0 0x10>;
 479                 #pwm-cells = <3>;
 480                 pinctrl-names = "default";
 481                 pinctrl-0 = <&pwm1_pin>;
 482                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 483                 clock-names = "pwm";
 484                 status = "disabled";
 485         };
 486
 487         pwm2: pwm@ff420020 {
 488                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 489                 reg = <0x0 0xff420020 0x0 0x10>;
 490                 #pwm-cells = <3>;
 491                 pinctrl-names = "default";
 492                 pinctrl-0 = <&pwm2_pin>;
 493                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 494                 clock-names = "pwm";
 495                 status = "disabled";
 496         };
 497
 498         pwm3: pwm@ff420030 {
 499                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 500                 reg = <0x0 0xff420030 0x0 0x10>;
 501                 #pwm-cells = <3>;
 502                 pinctrl-names = "default";
 503                 pinctrl-0 = <&pwm3a_pin>;
 504                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 505                 clock-names = "pwm";
 506                 status = "disabled";
 507         };
 508
 509         cic: syscon@ff620000 {
 510                 u-boot,dm-pre-reloc;
 511                 compatible = "rockchip,rk3399-cic", "syscon";
 512                 reg = <0x0 0xff620000 0x0 0x100>;
 513         };
 514
 515         dfi: dfi@ff630000 {
 516                 reg = <0x00 0xff630000 0x00 0x4000>;
 517                 compatible = "rockchip,rk3399-dfi";
 518                 rockchip,pmu = <&pmugrf>;
 519                 clocks = <&cru PCLK_DDR_MON>;
 520                 clock-names = "pclk_ddr_mon";
 521                 status = "disabled";
 522         };
 523
 524         dmc: dmc {
 525                 u-boot,dm-pre-reloc;
 526                 compatible = "rockchip,rk3399-dmc";
 527                 devfreq-events = <&dfi>;
 528                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
 529                 clocks = <&cru SCLK_DDRCLK>;
 530                 clock-names = "dmc_clk";
 531                 reg = <0x0 0xffa80000 0x0 0x0800
 532                        0x0 0xffa80800 0x0 0x1800
 533                        0x0 0xffa82000 0x0 0x2000
 534                        0x0 0xffa84000 0x0 0x1000
 535                        0x0 0xffa88000 0x0 0x0800
 536                        0x0 0xffa88800 0x0 0x1800
 537                        0x0 0xffa8a000 0x0 0x2000
 538                        0x0 0xffa8c000 0x0 0x1000>;
 539         };
 540
 541         pmucru: pmu-clock-controller@ff750000 {
 542                 u-boot,dm-pre-reloc;
 543                 compatible = "rockchip,rk3399-pmucru";
 544                 reg = <0x0 0xff750000 0x0 0x1000>;
 545                 #clock-cells = <1>;
 546                 #reset-cells = <1>;
 547                 assigned-clocks = <&pmucru PLL_PPLL>;
 548                 assigned-clock-rates = <676000000>;
 549         };
 550
 551         cru: clock-controller@ff760000 {
 552                 u-boot,dm-pre-reloc;
 553                 compatible = "rockchip,rk3399-cru";
 554                 reg = <0x0 0xff760000 0x0 0x1000>;
 555                 #clock-cells = <1>;
 556                 #reset-cells = <1>;
 557                 assigned-clocks =
 558                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 559                         <&cru PLL_NPLL>,
 560                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 561                         <&cru PCLK_PERIHP>,
 562                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 563                         <&cru PCLK_PERILP0>,
 564                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 565                 assigned-clock-rates =
 566                          <594000000>,  <800000000>,
 567                         <1000000000>,
 568                          <150000000>,   <75000000>,
 569                           <37500000>,
 570                          <100000000>,  <100000000>,
 571                           <50000000>,
 572                          <100000000>,   <50000000>;
 573         };
 574
 575         grf: syscon@ff770000 {
 576                 u-boot,dm-pre-reloc;
 577                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
 578                 reg = <0x0 0xff770000 0x0 0x10000>;
 579                 #address-cells = <1>;
 580                 #size-cells = <1>;
 581
 582                 io_domains: io-domains {
 583                         compatible = "rockchip,rk3399-io-voltage-domain";
 584                         status = "disabled";
 585                 };
 586
 587                 emmc_phy: phy@f780 {
 588                         compatible = "rockchip,rk3399-emmc-phy";
 589                         reg = <0xf780 0x24>;
 590                         #phy-cells = <0>;
 591                         status = "disabled";
 592                 };
 593         };
 594
 595         watchdog@ff840000 {
 596                 compatible = "snps,dw-wdt";
 597                 reg = <0x0 0xff840000 0x0 0x100>;
 598                 clocks = <&cru PCLK_WDT>;
 599                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 600         };
 601
 602         gmac: eth@fe300000 {
 603                 compatible = "rockchip,rk3399-gmac";
 604                 reg = <0x0 0xfe300000 0x0 0x10000>;
 605                 rockchip,grf = <&grf>;
 606                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 607                 interrupt-names = "macirq";
 608                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 609                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 610                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 611                          <&cru PCLK_GMAC>;
 612                 clock-names = "stmmaceth", "mac_clk_rx",
 613                               "mac_clk_tx", "clk_mac_ref",
 614                               "clk_mac_refout", "aclk_mac",
 615                               "pclk_mac";
 616                 resets = <&cru SRST_A_GMAC>;
 617                 reset-names = "stmmaceth";
 618                 status = "disabled";
 619         };
 620
 621         spdif: spdif@ff870000 {
 622                 compatible = "rockchip,rk3399-spdif";
 623                 reg = <0x0 0xff870000 0x0 0x1000>;
 624                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 625                 dmas = <&dmac_bus 7>;
 626                 dma-names = "tx";
 627                 clock-names = "mclk", "hclk";
 628                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 629                 pinctrl-names = "default";
 630                 pinctrl-0 = <&spdif_bus>;
 631                 status = "disabled";
 632         };
 633
 634         i2s0: i2s@ff880000 {
 635                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 636                 reg = <0x0 0xff880000 0x0 0x1000>;
 637                 rockchip,grf = <&grf>;
 638                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 639                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 640                 dma-names = "tx", "rx";
 641                 clock-names = "i2s_clk", "i2s_hclk";
 642                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
 643                 pinctrl-names = "default";
 644                 pinctrl-0 = <&i2s0_8ch_bus>;
 645                 status = "disabled";
 646         };
 647
 648         i2s1: i2s@ff890000 {
 649                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 650                 reg = <0x0 0xff890000 0x0 0x1000>;
 651                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 652                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 653                 dma-names = "tx", "rx";
 654                 clock-names = "i2s_clk", "i2s_hclk";
 655                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
 656                 pinctrl-names = "default";
 657                 pinctrl-0 = <&i2s1_2ch_bus>;
 658                 status = "disabled";
 659         };
 660
 661         i2s2: i2s@ff8a0000 {
 662                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 663                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 664                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 665                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 666                 dma-names = "tx", "rx";
 667                 clock-names = "i2s_clk", "i2s_hclk";
 668                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
 669                 status = "disabled";
 670         };
 671
 672         i2c0: i2c@ff3c0000 {
 673                 compatible = "rockchip,rk3399-i2c";
 674                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 675                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
 676                 assigned-clock-rates = <200000000>;
 677                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 678                 clock-names = "i2c", "pclk";
 679                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 680                 pinctrl-names = "default";
 681                 pinctrl-0 = <&i2c0_xfer>;
 682                 #address-cells = <1>;
 683                 #size-cells = <0>;
 684                 status = "disabled";
 685         };
 686
 687         pinctrl: pinctrl {
 688                 u-boot,dm-pre-reloc;
 689                 compatible = "rockchip,rk3399-pinctrl";
 690                 rockchip,grf = <&grf>;
 691                 rockchip,pmu = <&pmugrf>;
 692                 #address-cells = <2>;
 693                 #size-cells = <2>;
 694                 ranges;
 695
 696                 gpio0: gpio0@ff720000 {
 697                         compatible = "rockchip,gpio-bank";
 698                         reg = <0x0 0xff720000 0x0 0x100>;
 699                         clocks = <&pmucru PCLK_GPIO0_PMU>;
 700                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 701
 702                         gpio-controller;
 703                         #gpio-cells = <0x2>;
 704
 705                         interrupt-controller;
 706                         #interrupt-cells = <0x2>;
 707                 };
 708
 709                 gpio1: gpio1@ff730000 {
 710                         compatible = "rockchip,gpio-bank";
 711                         reg = <0x0 0xff730000 0x0 0x100>;
 712                         clocks = <&pmucru PCLK_GPIO1_PMU>;
 713                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 714
 715                         gpio-controller;
 716                         #gpio-cells = <0x2>;
 717
 718                         interrupt-controller;
 719                         #interrupt-cells = <0x2>;
 720                 };
 721
 722                 gpio2: gpio2@ff780000 {
 723                         compatible = "rockchip,gpio-bank";
 724                         reg = <0x0 0xff780000 0x0 0x100>;
 725                         clocks = <&cru PCLK_GPIO2>;
 726                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 727
 728                         gpio-controller;
 729                         #gpio-cells = <0x2>;
 730
 731                         interrupt-controller;
 732                         #interrupt-cells = <0x2>;
 733                 };
 734
 735                 gpio3: gpio3@ff788000 {
 736                         compatible = "rockchip,gpio-bank";
 737                         reg = <0x0 0xff788000 0x0 0x100>;
 738                         clocks = <&cru PCLK_GPIO3>;
 739                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 740
 741                         gpio-controller;
 742                         #gpio-cells = <0x2>;
 743
 744                         interrupt-controller;
 745                         #interrupt-cells = <0x2>;
 746                 };
 747
 748                 gpio4: gpio4@ff790000 {
 749                         compatible = "rockchip,gpio-bank";
 750                         reg = <0x0 0xff790000 0x0 0x100>;
 751                         clocks = <&cru PCLK_GPIO4>;
 752                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 753
 754                         gpio-controller;
 755                         #gpio-cells = <0x2>;
 756
 757                         interrupt-controller;
 758                         #interrupt-cells = <0x2>;
 759                 };
 760
 761                 pcfg_pull_up: pcfg-pull-up {
 762                         bias-pull-up;
 763                 };
 764
 765                 pcfg_pull_down: pcfg-pull-down {
 766                         bias-pull-down;
 767                 };
 768
 769                 pcfg_pull_none: pcfg-pull-none {
 770                         bias-disable;
 771                 };
 772
 773                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 774                         bias-disable;
 775                         drive-strength = <12>;
 776                 };
 777
 778                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 779                         bias-pull-up;
 780                         drive-strength = <8>;
 781                 };
 782
 783                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 784                         bias-pull-down;
 785                         drive-strength = <4>;
 786                 };
 787
 788                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 789                         bias-pull-up;
 790                         drive-strength = <2>;
 791                 };
 792
 793                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
 794                         bias-pull-down;
 795                         drive-strength = <12>;
 796                 };
 797
 798                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
 799                         bias-disable;
 800                         drive-strength = <13>;
 801                 };
 802
 803                 i2c0 {
 804                         i2c0_xfer: i2c0-xfer {
 805                                 rockchip,pins =
 806                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
 807                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
 808                         };
 809                 };
 810
 811                 i2c1 {
 812                         i2c1_xfer: i2c1-xfer {
 813                                 rockchip,pins =
 814                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
 815                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
 816                         };
 817                 };
 818
 819                 i2c2 {
 820                         i2c2_xfer: i2c2-xfer {
 821                                 rockchip,pins =
 822                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
 823                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
 824                         };
 825                 };
 826
 827                 i2c3 {
 828                         i2c3_xfer: i2c3-xfer {
 829                                 rockchip,pins =
 830                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
 831                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
 832                         };
 833                 };
 834
 835                 i2c4 {
 836                         i2c4_xfer: i2c4-xfer {
 837                                 rockchip,pins =
 838                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
 839                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 840                         };
 841                 };
 842
 843                 i2c5 {
 844                         i2c5_xfer: i2c5-xfer {
 845                                 rockchip,pins =
 846                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
 847                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
 848                         };
 849                 };
 850
 851                 i2c6 {
 852                         i2c6_xfer: i2c6-xfer {
 853                                 rockchip,pins =
 854                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
 855                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
 856                         };
 857                 };
 858
 859                 i2c7 {
 860                         i2c7_xfer: i2c7-xfer {
 861                                 rockchip,pins =
 862                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
 863                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
 864                         };
 865                 };
 866
 867                 i2c8 {
 868                         i2c8_xfer: i2c8-xfer {
 869                                 rockchip,pins =
 870                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
 871                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
 872                         };
 873                 };
 874
 875                 i2s0 {
 876                         i2s0_8ch_bus: i2s0-8ch-bus {
 877                                 rockchip,pins =
 878                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
 879                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
 880                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
 881                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
 882                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
 883                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
 884                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
 885                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
 886                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
 887                         };
 888                 };
 889
 890                 i2s1 {
 891                         i2s1_2ch_bus: i2s1-2ch-bus {
 892                                 rockchip,pins =
 893                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
 894                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
 895                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
 896                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
 897                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
 898                         };
 899                 };
 900
 901                 gmac {
 902                         rgmii_pins: rgmii-pins {
 903                                 rockchip,pins =
 904                                         /* mac_txclk */
 905                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
 906                                         /* mac_rxclk */
 907                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
 908                                         /* mac_mdio */
 909                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 910                                         /* mac_txen */
 911                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
 912                                         /* mac_clk */
 913                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 914                                         /* mac_rxdv */
 915                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
 916                                         /* mac_mdc */
 917                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 918                                         /* mac_rxd1 */
 919                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 920                                         /* mac_rxd0 */
 921                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 922                                         /* mac_txd1 */
 923                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
 924                                         /* mac_txd0 */
 925                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
 926                                         /* mac_rxd3 */
 927                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
 928                                         /* mac_rxd2 */
 929                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
 930                                         /* mac_txd3 */
 931                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
 932                                         /* mac_txd2 */
 933                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
 934                         };
 935                 };
 936
 937                 sdmmc {
 938                         sdmmc_bus1: sdmmc-bus1 {
 939                                 rockchip,pins =
 940                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
 941                         };
 942
 943                         sdmmc_bus4: sdmmc-bus4 {
 944                                 rockchip,pins =
 945                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
 946                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
 947                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
 948                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
 949                         };
 950
 951                         sdmmc_clk: sdmmc-clk {
 952                                 rockchip,pins =
 953                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
 954                         };
 955
 956                         sdmmc_cmd: sdmmc-cmd {
 957                                 rockchip,pins =
 958                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
 959                         };
 960
 961                         sdmmc_cd: sdmcc-cd {
 962                                 rockchip,pins =
 963                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
 964                         };
 965
 966                         sdmmc_wp: sdmmc-wp {
 967                                 rockchip,pins =
 968                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
 969                         };
 970                 };
 971
 972                 spdif {
 973                         spdif_bus: spdif-bus {
 974                                 rockchip,pins =
 975                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
 976                         };
 977                 };
 978
 979                 spi0 {
 980                         spi0_clk: spi0-clk {
 981                                 rockchip,pins =
 982                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
 983                         };
 984                         spi0_cs0: spi0-cs0 {
 985                                 rockchip,pins =
 986                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
 987                         };
 988                         spi0_cs1: spi0-cs1 {
 989                                 rockchip,pins =
 990                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
 991                         };
 992                         spi0_tx: spi0-tx {
 993                                 rockchip,pins =
 994                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
 995                         };
 996                         spi0_rx: spi0-rx {
 997                                 rockchip,pins =
 998                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
 999                         };
1000                 };
1001
1002                 spi1 {
1003                         spi1_clk: spi1-clk {
1004                                 rockchip,pins =
1005                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1006                         };
1007                         spi1_cs0: spi1-cs0 {
1008                                 rockchip,pins =
1009                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1010                         };
1011                         spi1_rx: spi1-rx {
1012                                 rockchip,pins =
1013                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1014                         };
1015                         spi1_tx: spi1-tx {
1016                                 rockchip,pins =
1017                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1018                         };
1019                 };
1020
1021                 spi2 {
1022                         spi2_clk: spi2-clk {
1023                                 rockchip,pins =
1024                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1025                         };
1026                         spi2_cs0: spi2-cs0 {
1027                                 rockchip,pins =
1028                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1029                         };
1030                         spi2_rx: spi2-rx {
1031                                 rockchip,pins =
1032                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1033                         };
1034                         spi2_tx: spi2-tx {
1035                                 rockchip,pins =
1036                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1037                         };
1038                 };
1039
1040                 spi3 {
1041                         spi3_clk: spi3-clk {
1042                                 rockchip,pins =
1043                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1044                         };
1045                         spi3_cs0: spi3-cs0 {
1046                                 rockchip,pins =
1047                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1048                         };
1049                         spi3_rx: spi3-rx {
1050                                 rockchip,pins =
1051                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1052                         };
1053                         spi3_tx: spi3-tx {
1054                                 rockchip,pins =
1055                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1056                         };
1057                 };
1058
1059                 spi4 {
1060                         spi4_clk: spi4-clk {
1061                                 rockchip,pins =
1062                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1063                         };
1064                         spi4_cs0: spi4-cs0 {
1065                                 rockchip,pins =
1066                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1067                         };
1068                         spi4_rx: spi4-rx {
1069                                 rockchip,pins =
1070                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1071                         };
1072                         spi4_tx: spi4-tx {
1073                                 rockchip,pins =
1074                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1075                         };
1076                 };
1077
1078                 spi5 {
1079                         spi5_clk: spi5-clk {
1080                                 rockchip,pins =
1081                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1082                         };
1083                         spi5_cs0: spi5-cs0 {
1084                                 rockchip,pins =
1085                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1086                         };
1087                         spi5_rx: spi5-rx {
1088                                 rockchip,pins =
1089                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1090                         };
1091                         spi5_tx: spi5-tx {
1092                                 rockchip,pins =
1093                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1094                         };
1095                 };
1096
1097                 uart0 {
1098                         uart0_xfer: uart0-xfer {
1099                                 rockchip,pins =
1100                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1101                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1102                         };
1103
1104                         uart0_cts: uart0-cts {
1105                                 rockchip,pins =
1106                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1107                         };
1108
1109                         uart0_rts: uart0-rts {
1110                                 rockchip,pins =
1111                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1112                         };
1113                 };
1114
1115                 uart1 {
1116                         uart1_xfer: uart1-xfer {
1117                                 rockchip,pins =
1118                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1119                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1120                         };
1121                 };
1122
1123                 uart2a {
1124                         uart2a_xfer: uart2a-xfer {
1125                                 rockchip,pins =
1126                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1127                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1128                         };
1129                 };
1130
1131                 uart2b {
1132                         uart2b_xfer: uart2b-xfer {
1133                                 rockchip,pins =
1134                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1135                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1136                         };
1137                 };
1138
1139                 uart2c {
1140                         uart2c_xfer: uart2c-xfer {
1141                                 rockchip,pins =
1142                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1143                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1144                         };
1145                 };
1146
1147                 uart3 {
1148                         uart3_xfer: uart3-xfer {
1149                                 rockchip,pins =
1150                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1151                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1152                         };
1153
1154                         uart3_cts: uart3-cts {
1155                                 rockchip,pins =
1156                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1157                         };
1158
1159                         uart3_rts: uart3-rts {
1160                                 rockchip,pins =
1161                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1162                         };
1163                 };
1164
1165                 uart4 {
1166                         uart4_xfer: uart4-xfer {
1167                                 rockchip,pins =
1168                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1169                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1170                         };
1171                 };
1172
1173                 uarthdcp {
1174                         uarthdcp_xfer: uarthdcp-xfer {
1175                                 rockchip,pins =
1176                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1177                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1178                         };
1179                 };
1180
1181                 pwm0 {
1182                         pwm0_pin: pwm0-pin {
1183                                 rockchip,pins =
1184                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1185                         };
1186
1187                         vop0_pwm_pin: vop0-pwm-pin {
1188                                 rockchip,pins =
1189                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1190                         };
1191                 };
1192
1193                 pwm1 {
1194                         pwm1_pin: pwm1-pin {
1195                                 rockchip,pins =
1196                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1197                         };
1198
1199                         vop1_pwm_pin: vop1-pwm-pin {
1200                                 rockchip,pins =
1201                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1202                         };
1203                 };
1204
1205                 pwm2 {
1206                         pwm2_pin: pwm2-pin {
1207                                 rockchip,pins =
1208                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1209                         };
1210                 };
1211
1212                 pwm3a {
1213                         pwm3a_pin: pwm3a-pin {
1214                                 rockchip,pins =
1215                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1216                         };
1217                 };
1218
1219                 pwm3b {
1220                         pwm3b_pin: pwm3b-pin {
1221                                 rockchip,pins =
1222                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1223                         };
1224                 };
1225         };
1226 };