git.sur5r.net Git - u-boot/blob - arch/arm/dts/rk3xxx.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+ or X11
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include "skeleton.dtsi"
  11
  12 / {
  13         interrupt-parent = <&gic>;
  14
  15         aliases {
  16                 ethernet0 = &emac;
  17                 i2c0 = &i2c0;
  18                 i2c1 = &i2c1;
  19                 i2c2 = &i2c2;
  20                 i2c3 = &i2c3;
  21                 i2c4 = &i2c4;
  22                 mshc0 = &emmc;
  23                 mshc1 = &mmc0;
  24                 mshc2 = &mmc1;
  25                 serial0 = &uart0;
  26                 serial1 = &uart1;
  27                 serial2 = &uart2;
  28                 serial3 = &uart3;
  29                 spi0 = &spi0;
  30                 spi1 = &spi1;
  31         };
  32
  33         amba {
  34                 compatible = "simple-bus";
  35                 #address-cells = <1>;
  36                 #size-cells = <1>;
  37                 ranges;
  38
  39                 dmac1_s: dma-controller@20018000 {
  40                         compatible = "arm,pl330", "arm,primecell";
  41                         reg = <0x20018000 0x4000>;
  42                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  43                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  44                         #dma-cells = <1>;
  45                         arm,pl330-broken-no-flushp;
  46                         clocks = <&cru ACLK_DMA1>;
  47                         clock-names = "apb_pclk";
  48                 };
  49
  50                 dmac1_ns: dma-controller@2001c000 {
  51                         compatible = "arm,pl330", "arm,primecell";
  52                         reg = <0x2001c000 0x4000>;
  53                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  54                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  55                         #dma-cells = <1>;
  56                         arm,pl330-broken-no-flushp;
  57                         clocks = <&cru ACLK_DMA1>;
  58                         clock-names = "apb_pclk";
  59                         status = "disabled";
  60                 };
  61
  62                 dmac2: dma-controller@20078000 {
  63                         compatible = "arm,pl330", "arm,primecell";
  64                         reg = <0x20078000 0x4000>;
  65                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  66                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  67                         #dma-cells = <1>;
  68                         arm,pl330-broken-no-flushp;
  69                         clocks = <&cru ACLK_DMA2>;
  70                         clock-names = "apb_pclk";
  71                 };
  72         };
  73
  74         xin24m: oscillator {
  75                 compatible = "fixed-clock";
  76                 clock-frequency = <24000000>;
  77                 #clock-cells = <0>;
  78                 clock-output-names = "xin24m";
  79         };
  80
  81         L2: l2-cache-controller@10138000 {
  82                 compatible = "arm,pl310-cache";
  83                 reg = <0x10138000 0x1000>;
  84                 cache-unified;
  85                 cache-level = <2>;
  86         };
  87
  88         scu@1013c000 {
  89                 compatible = "arm,cortex-a9-scu";
  90                 reg = <0x1013c000 0x100>;
  91         };
  92
  93         global_timer: global-timer@1013c200 {
  94                 compatible = "arm,cortex-a9-global-timer";
  95                 reg = <0x1013c200 0x20>;
  96                 interrupts = <GIC_PPI 11 0x304>;
  97                 clocks = <&cru CORE_PERI>;
  98         };
  99
 100         local_timer: local-timer@1013c600 {
 101                 compatible = "arm,cortex-a9-twd-timer";
 102                 reg = <0x1013c600 0x20>;
 103                 interrupts = <GIC_PPI 13 0x304>;
 104                 clocks = <&cru CORE_PERI>;
 105         };
 106
 107         gic: interrupt-controller@1013d000 {
 108                 compatible = "arm,cortex-a9-gic";
 109                 interrupt-controller;
 110                 #interrupt-cells = <3>;
 111                 reg = <0x1013d000 0x1000>,
 112                       <0x1013c100 0x0100>;
 113         };
 114
 115         uart0: serial@10124000 {
 116                 compatible = "snps,dw-apb-uart";
 117                 reg = <0x10124000 0x400>;
 118                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 119                 reg-shift = <2>;
 120                 reg-io-width = <1>;
 121                 clock-names = "baudclk", "apb_pclk";
 122                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 123                 status = "disabled";
 124         };
 125
 126         uart1: serial@10126000 {
 127                 compatible = "snps,dw-apb-uart";
 128                 reg = <0x10126000 0x400>;
 129                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 130                 reg-shift = <2>;
 131                 reg-io-width = <1>;
 132                 clock-names = "baudclk", "apb_pclk";
 133                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 134                 status = "disabled";
 135         };
 136
 137         noc: syscon@10128000 {
 138                 u-boot,dm-spl;
 139                 compatible = "rockchip,rk3188-noc", "syscon";
 140                 reg = <0x10128000 0x2000>;
 141         };
 142
 143         usb_otg: usb@10180000 {
 144                 compatible = "rockchip,rk3066-usb", "snps,dwc2";
 145                 reg = <0x10180000 0x40000>;
 146                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 147                 clocks = <&cru HCLK_OTG0>;
 148                 clock-names = "otg";
 149                 dr_mode = "otg";
 150                 g-np-tx-fifo-size = <16>;
 151                 g-rx-fifo-size = <275>;
 152                 g-tx-fifo-size = <256 128 128 64 64 32>;
 153                 g-use-dma;
 154                 phys = <&usbphy0>;
 155                 phy-names = "usb2-phy";
 156                 status = "disabled";
 157         };
 158
 159         usb_host: usb@101c0000 {
 160                 compatible = "snps,dwc2";
 161                 reg = <0x101c0000 0x40000>;
 162                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 163                 clocks = <&cru HCLK_OTG1>;
 164                 clock-names = "otg";
 165                 dr_mode = "host";
 166                 phys = <&usbphy1>;
 167                 phy-names = "usb2-phy";
 168                 status = "disabled";
 169         };
 170
 171         emac: ethernet@10204000 {
 172                 compatible = "snps,arc-emac";
 173                 reg = <0x10204000 0x3c>;
 174                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 175                 #address-cells = <1>;
 176                 #size-cells = <0>;
 177
 178                 rockchip,grf = <&grf>;
 179
 180                 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
 181                 clock-names = "hclk", "macref";
 182                 max-speed = <100>;
 183                 phy-mode = "rmii";
 184
 185                 status = "disabled";
 186         };
 187
 188         mmc0: dwmmc@10214000 {
 189                 compatible = "rockchip,rk2928-dw-mshc";
 190                 reg = <0x10214000 0x1000>;
 191                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 192                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 193                 clock-names = "biu", "ciu";
 194                 fifo-depth = <256>;
 195                 status = "disabled";
 196         };
 197
 198         mmc1: dwmmc@10218000 {
 199                 compatible = "rockchip,rk2928-dw-mshc";
 200                 reg = <0x10218000 0x1000>;
 201                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 202                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 203                 clock-names = "biu", "ciu";
 204                 fifo-depth = <256>;
 205                 status = "disabled";
 206         };
 207
 208         emmc: dwmmc@1021c000 {
 209                 compatible = "rockchip,rk2928-dw-mshc";
 210                 reg = <0x1021c000 0x1000>;
 211                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 212                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 213                 clock-names = "biu", "ciu";
 214                 fifo-depth = <256>;
 215                 status = "disabled";
 216         };
 217
 218         pmu: pmu@20004000 {
 219                 compatible = "rockchip,rk3066-pmu", "syscon";
 220                 reg = <0x20004000 0x100>;
 221                 u-boot,dm-spl;
 222         };
 223
 224         grf: grf@20008000 {
 225                 compatible = "syscon";
 226                 reg = <0x20008000 0x200>;
 227                 u-boot,dm-spl;
 228         };
 229
 230         dmc: dmc@20020000 {
 231                 /* unreviewed u-boot-specific binding */
 232                 compatible = "rockchip,rk3188-dmc", "syscon";
 233                 rockchip,cru = <&cru>;
 234                 rockchip,grf = <&grf>;
 235                 rockchip,pmu = <&pmu>;
 236                 rockchip,noc = <&noc>;
 237                 reg = <0x20020000 0x3fc
 238                        0x20040000 0x294>;
 239                 clocks = <&cru PCLK_DDRUPCTL>, <&cru PCLK_PUBL>;
 240                 clock-names = "pclk_ddrupctl", "pclk_publ";
 241                 u-boot,dm-spl;
 242         };
 243
 244         i2c0: i2c@2002d000 {
 245                 compatible = "rockchip,rk3066-i2c";
 246                 reg = <0x2002d000 0x1000>;
 247                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 248                 #address-cells = <1>;
 249                 #size-cells = <0>;
 250
 251                 rockchip,grf = <&grf>;
 252
 253                 clock-names = "i2c";
 254                 clocks = <&cru PCLK_I2C0>;
 255
 256                 status = "disabled";
 257         };
 258
 259         i2c1: i2c@2002f000 {
 260                 compatible = "rockchip,rk3066-i2c";
 261                 reg = <0x2002f000 0x1000>;
 262                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 263                 #address-cells = <1>;
 264                 #size-cells = <0>;
 265
 266                 rockchip,grf = <&grf>;
 267
 268                 clocks = <&cru PCLK_I2C1>;
 269                 clock-names = "i2c";
 270
 271                 status = "disabled";
 272         };
 273
 274         pwm0: pwm@20030000 {
 275                 compatible = "rockchip,rk2928-pwm";
 276                 reg = <0x20030000 0x10>;
 277                 #pwm-cells = <2>;
 278                 clocks = <&cru PCLK_PWM01>;
 279                 status = "disabled";
 280         };
 281
 282         pwm1: pwm@20030010 {
 283                 compatible = "rockchip,rk2928-pwm";
 284                 reg = <0x20030010 0x10>;
 285                 #pwm-cells = <2>;
 286                 clocks = <&cru PCLK_PWM01>;
 287                 status = "disabled";
 288         };
 289
 290         wdt: watchdog@2004c000 {
 291                 compatible = "snps,dw-wdt";
 292                 reg = <0x2004c000 0x100>;
 293                 clocks = <&cru PCLK_WDT>;
 294                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 295                 status = "disabled";
 296         };
 297
 298         pwm2: pwm@20050020 {
 299                 compatible = "rockchip,rk2928-pwm";
 300                 reg = <0x20050020 0x10>;
 301                 #pwm-cells = <2>;
 302                 clocks = <&cru PCLK_PWM23>;
 303                 status = "disabled";
 304         };
 305
 306         pwm3: pwm@20050030 {
 307                 compatible = "rockchip,rk2928-pwm";
 308                 reg = <0x20050030 0x10>;
 309                 #pwm-cells = <2>;
 310                 clocks = <&cru PCLK_PWM23>;
 311                 status = "disabled";
 312         };
 313
 314         i2c2: i2c@20056000 {
 315                 compatible = "rockchip,rk3066-i2c";
 316                 reg = <0x20056000 0x1000>;
 317                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 318                 #address-cells = <1>;
 319                 #size-cells = <0>;
 320
 321                 rockchip,grf = <&grf>;
 322
 323                 clocks = <&cru PCLK_I2C2>;
 324                 clock-names = "i2c";
 325
 326                 status = "disabled";
 327         };
 328
 329         i2c3: i2c@2005a000 {
 330                 compatible = "rockchip,rk3066-i2c";
 331                 reg = <0x2005a000 0x1000>;
 332                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 333                 #address-cells = <1>;
 334                 #size-cells = <0>;
 335
 336                 rockchip,grf = <&grf>;
 337
 338                 clocks = <&cru PCLK_I2C3>;
 339                 clock-names = "i2c";
 340
 341                 status = "disabled";
 342         };
 343
 344         i2c4: i2c@2005e000 {
 345                 compatible = "rockchip,rk3066-i2c";
 346                 reg = <0x2005e000 0x1000>;
 347                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 348                 #address-cells = <1>;
 349                 #size-cells = <0>;
 350
 351                 rockchip,grf = <&grf>;
 352
 353                 clocks = <&cru PCLK_I2C4>;
 354                 clock-names = "i2c";
 355
 356                 status = "disabled";
 357         };
 358
 359         uart2: serial@20064000 {
 360                 compatible = "snps,dw-apb-uart";
 361                 reg = <0x20064000 0x400>;
 362                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 363                 reg-shift = <2>;
 364                 reg-io-width = <1>;
 365                 clock-frequency = <24000000>;
 366                 clock-names = "baudclk", "apb_pclk";
 367                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 368                 status = "disabled";
 369         };
 370
 371         uart3: serial@20068000 {
 372                 compatible = "snps,dw-apb-uart";
 373                 reg = <0x20068000 0x400>;
 374                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 375                 reg-shift = <2>;
 376                 reg-io-width = <1>;
 377                 clock-names = "baudclk", "apb_pclk";
 378                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 379                 status = "disabled";
 380         };
 381
 382         saradc: saradc@2006c000 {
 383                 compatible = "rockchip,saradc";
 384                 reg = <0x2006c000 0x100>;
 385                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 386                 #io-channel-cells = <1>;
 387                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 388                 clock-names = "saradc", "apb_pclk";
 389                 status = "disabled";
 390         };
 391
 392         spi0: spi@20070000 {
 393                 compatible = "rockchip,rk3066-spi";
 394                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 395                 clock-names = "spiclk", "apb_pclk";
 396                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 397                 reg = <0x20070000 0x1000>;
 398                 #address-cells = <1>;
 399                 #size-cells = <0>;
 400                 dmas = <&dmac2 10>, <&dmac2 11>;
 401                 dma-names = "tx", "rx";
 402                 status = "disabled";
 403         };
 404
 405         spi1: spi@20074000 {
 406                 compatible = "rockchip,rk3066-spi";
 407                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 408                 clock-names = "spiclk", "apb_pclk";
 409                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 410                 reg = <0x20074000 0x1000>;
 411                 #address-cells = <1>;
 412                 #size-cells = <0>;
 413                 dmas = <&dmac2 12>, <&dmac2 13>;
 414                 dma-names = "tx", "rx";
 415                 status = "disabled";
 416         };
 417 };