git.sur5r.net Git - u-boot/blob - arch/arm/dts/rv1108.dtsi

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/clock/rv1108-cru.h>
  11 #include <dt-bindings/pinctrl/rockchip.h>
  12 / {
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15
  16         compatible = "rockchip,rv1108";
  17
  18         interrupt-parent = <&gic>;
  19
  20         aliases {
  21                 serial0 = &uart0;
  22                 serial1 = &uart1;
  23                 serial2 = &uart2;
  24                 spi0    = &sfc;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu0: cpu@f00 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a7";
  34                         reg = <0xf00>;
  35                 };
  36         };
  37
  38         arm-pmu {
  39                 compatible = "arm,cortex-a7-pmu";
  40                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
  41         };
  42
  43         timer {
  44                 compatible = "arm,armv7-timer";
  45                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
  46                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
  47                 clock-frequency = <24000000>;
  48         };
  49
  50         xin24m: oscillator {
  51                 compatible = "fixed-clock";
  52                 clock-frequency = <24000000>;
  53                 clock-output-names = "xin24m";
  54                 #clock-cells = <0>;
  55         };
  56
  57         amba {
  58                 compatible = "simple-bus";
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61                 ranges;
  62
  63                 pdma: pdma@102a0000 {
  64                         compatible = "arm,pl330", "arm,primecell";
  65                         reg = <0x102a0000 0x4000>;
  66                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  67                         #dma-cells = <1>;
  68                         arm,pl330-broken-no-flushp;
  69                         clocks = <&cru ACLK_DMAC>;
  70                         clock-names = "apb_pclk";
  71                 };
  72         };
  73
  74         bus_intmem@10080000 {
  75                 compatible = "mmio-sram";
  76                 reg = <0x10080000 0x2000>;
  77                 #address-cells = <1>;
  78                 #size-cells = <1>;
  79                 ranges = <0 0x10080000 0x2000>;
  80         };
  81
  82         uart2: serial@10210000 {
  83                 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
  84                 reg = <0x10210000 0x100>;
  85                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  86                 reg-shift = <2>;
  87                 reg-io-width = <4>;
  88                 clock-frequency = <24000000>;
  89                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
  90                 clock-names = "baudclk", "apb_pclk";
  91                 pinctrl-names = "default";
  92                 pinctrl-0 = <&uart2m0_xfer>;
  93                 status = "disabled";
  94         };
  95
  96         uart1: serial@10220000 {
  97                 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
  98                 reg = <0x10220000 0x100>;
  99                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 100                 reg-shift = <2>;
 101                 reg-io-width = <4>;
 102                 clock-frequency = <24000000>;
 103                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 104                 clock-names = "baudclk", "apb_pclk";
 105                 pinctrl-names = "default";
 106                 pinctrl-0 = <&uart1_xfer>;
 107                 status = "disabled";
 108         };
 109
 110         uart0: serial@10230000 {
 111                 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
 112                 reg = <0x10230000 0x100>;
 113                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 114                 reg-shift = <2>;
 115                 reg-io-width = <4>;
 116                 clock-frequency = <24000000>;
 117                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 118                 clock-names = "baudclk", "apb_pclk";
 119                 pinctrl-names = "default";
 120                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 121                 status = "disabled";
 122         };
 123
 124         grf: syscon@10300000 {
 125                 compatible = "rockchip,rv1108-grf", "syscon";
 126                 reg = <0x10300000 0x1000>;
 127         };
 128
 129         pmugrf: syscon@20060000 {
 130                 compatible = "rockchip,rv1108-pmugrf", "syscon";
 131                 reg = <0x20060000 0x1000>;
 132         };
 133
 134         cru: clock-controller@20200000 {
 135                 compatible = "rockchip,rv1108-cru";
 136                 reg = <0x20200000 0x1000>;
 137                 rockchip,grf = <&grf>;
 138                 #clock-cells = <1>;
 139                 #reset-cells = <1>;
 140         };
 141
 142         emmc: dwmmc@30110000 {
 143                 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
 144                 clock-freq-min-max = <400000 150000000>;
 145                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 146                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 147                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 148                 fifo-depth = <0x100>;
 149                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 150                 reg = <0x30110000 0x4000>;
 151                 status = "disabled";
 152         };
 153
 154         sdio: dwmmc@30120000 {
 155                 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
 156                 clock-freq-min-max = <400000 150000000>;
 157                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 158                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 159                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 160                 fifo-depth = <0x100>;
 161                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 162                 reg = <0x30120000 0x4000>;
 163                 status = "disabled";
 164         };
 165
 166         sdmmc: dwmmc@30130000 {
 167                 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
 168                 clock-freq-min-max = <400000 100000000>;
 169                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 170                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 171                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 172                 fifo-depth = <0x100>;
 173                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 174                 reg = <0x30130000 0x4000>;
 175                 status = "disabled";
 176         };
 177
 178         sfc: sfc@301c0000 {
 179                 compatible = "rockchip,sfc";
 180                 reg = <0x301c0000 0x200>;
 181                 #address-cells = <1>;
 182                 #size-cells = <0>;
 183                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 184                 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
 185                 clock-names = "clk_sfc", "hclk_sfc";
 186                 pinctrl-0 = <&sfc_pins>;
 187                 pinctrl-names = "default";
 188                 status = "disabled";
 189         };
 190
 191         gmac: ethernet@30200000 {
 192                 compatible = "rockchip,rv1108-gmac";
 193                 reg = <0x30200000 0x10000>;
 194                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 195                 interrupt-names = "macirq";
 196                 rockchip,grf = <&grf>;
 197                 clocks = <&cru SCLK_MAC>,
 198                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 199                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 200                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 201                 clock-names = "stmmaceth",
 202                         "mac_clk_rx", "mac_clk_tx",
 203                         "clk_mac_ref", "clk_mac_refout",
 204                         "aclk_mac", "pclk_mac";
 205                 pinctrl-names = "default";
 206                 pinctrl-0 = <&rmii_pins>;
 207                 phy-mode = "rmii";
 208                 max-speed = <100>;
 209                 status = "disabled";
 210         };
 211
 212         gic: interrupt-controller@32010000 {
 213                 compatible = "arm,gic-400";
 214                 interrupt-controller;
 215                 #interrupt-cells = <3>;
 216                 #address-cells = <0>;
 217
 218                 reg = <0x32011000 0x1000>,
 219                       <0x32012000 0x1000>,
 220                       <0x32014000 0x2000>,
 221                       <0x32016000 0x2000>;
 222                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
 223         };
 224
 225         pinctrl: pinctrl {
 226                 compatible = "rockchip,rv1108-pinctrl";
 227                 rockchip,grf = <&grf>;
 228                 rockchip,pmu = <&pmugrf>;
 229                 #address-cells = <1>;
 230                 #size-cells = <1>;
 231                 ranges;
 232
 233                 gpio0: gpio0@20030000 {
 234                         compatible = "rockchip,gpio-bank";
 235                         reg = <0x20030000 0x100>;
 236                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 237                         clocks = <&xin24m>;
 238
 239                         gpio-controller;
 240                         #gpio-cells = <2>;
 241
 242                         interrupt-controller;
 243                         #interrupt-cells = <2>;
 244                 };
 245
 246                 gpio1: gpio1@10310000 {
 247                         compatible = "rockchip,gpio-bank";
 248                         reg = <0x10310000 0x100>;
 249                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 250                         clocks = <&xin24m>;
 251
 252                         gpio-controller;
 253                         #gpio-cells = <2>;
 254
 255                         interrupt-controller;
 256                         #interrupt-cells = <2>;
 257                 };
 258
 259                 gpio2: gpio2@10320000 {
 260                         compatible = "rockchip,gpio-bank";
 261                         reg = <0x10320000 0x100>;
 262                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 263                         clocks = <&xin24m>;
 264
 265                         gpio-controller;
 266                         #gpio-cells = <2>;
 267
 268                         interrupt-controller;
 269                         #interrupt-cells = <2>;
 270                 };
 271
 272                 gpio3: gpio3@10330000 {
 273                         compatible = "rockchip,gpio-bank";
 274                         reg = <0x10330000 0x100>;
 275                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 276                         clocks = <&xin24m>;
 277
 278                         gpio-controller;
 279                         #gpio-cells = <2>;
 280
 281                         interrupt-controller;
 282                         #interrupt-cells = <2>;
 283                 };
 284
 285                 pcfg_pull_up: pcfg-pull-up {
 286                         bias-pull-up;
 287                 };
 288
 289                 pcfg_pull_down: pcfg-pull-down {
 290                         bias-pull-down;
 291                 };
 292
 293                 pcfg_pull_none: pcfg-pull-none {
 294                         bias-disable;
 295                 };
 296
 297                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
 298                         drive-strength = <8>;
 299                 };
 300
 301                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
 302                         drive-strength = <12>;
 303                 };
 304
 305                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
 306                         bias-pull-up;
 307                         drive-strength = <8>;
 308                 };
 309
 310                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
 311                         drive-strength = <4>;
 312                 };
 313
 314                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
 315                         bias-pull-up;
 316                         drive-strength = <4>;
 317                 };
 318
 319                 pcfg_output_high: pcfg-output-high {
 320                         output-high;
 321                 };
 322
 323                 pcfg_output_low: pcfg-output-low {
 324                         output-low;
 325                 };
 326
 327                 pcfg_input_high: pcfg-input-high {
 328                         bias-pull-up;
 329                         input-enable;
 330                 };
 331
 332                 gmac {
 333                         rmii_pins: rmii-pins {
 334                                 rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
 335                                                 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>,
 336                                                 <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
 337                                                 <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
 338                                                 <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
 339                                                 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
 340                                                 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>,
 341                                                 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>,
 342                                                 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>,
 343                                                 <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
 344                         };
 345                 };
 346
 347                 i2c1 {
 348                         i2c1_xfer: i2c1-xfer {
 349                                 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
 350                                                 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
 351                         };
 352                 };
 353
 354                 i2c2m1 {
 355                         i2c2m1_xfer: i2c2m1-xfer {
 356                                 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
 357                                                 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
 358                         };
 359
 360                         i2c2m1_gpio: i2c2m1-gpio {
 361                                 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
 362                                                 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
 363                         };
 364                 };
 365
 366                 i2c2m05v {
 367                         i2c2m05v_xfer: i2c2m05v-xfer {
 368                                 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
 369                                                 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
 370                         };
 371
 372                         i2c2m05v_gpio: i2c2m05v-gpio {
 373                                 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
 374                                                 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
 375                         };
 376                 };
 377
 378                 i2c3 {
 379                         i2c3_xfer: i2c3-xfer {
 380                                 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
 381                                                 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
 382                         };
 383                 };
 384
 385                 sfc {
 386                         sfc_pins: sfc-pins {
 387                                 rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>,
 388                                                 <2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>,
 389                                                 <2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,
 390                                                 <2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>,
 391                                                 <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>,
 392                                                 <2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>;
 393                         };
 394                 };
 395
 396                 sdmmc {
 397                         sdmmc_clk: sdmmc-clk {
 398                                 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
 399                         };
 400
 401                         sdmmc_cmd: sdmmc-cmd {
 402                                 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 403                         };
 404
 405                         sdmmc_cd: sdmmc-cd {
 406                                 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 407                         };
 408
 409                         sdmmc_bus1: sdmmc-bus1 {
 410                                 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 411                         };
 412
 413                         sdmmc_bus4: sdmmc-bus4 {
 414                                 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 415                                                 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 416                                                 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 417                                                 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 418                         };
 419                 };
 420
 421                 uart0 {
 422                         uart0_xfer: uart0-xfer {
 423                                 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
 424                                                 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
 425                         };
 426
 427                         uart0_cts: uart0-cts {
 428                                 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
 429                         };
 430
 431                         uart0_rts: uart0-rts {
 432                                 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
 433                         };
 434
 435                         uart0_rts_gpio: uart0-rts-gpio {
 436                                 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
 437                         };
 438                 };
 439
 440                 uart1 {
 441                         uart1_xfer: uart1-xfer {
 442                                 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
 443                                                 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
 444                         };
 445
 446                         uart1_cts: uart1-cts {
 447                                 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
 448                         };
 449
 450                         uart01rts: uart1-rts {
 451                                 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
 452                         };
 453                 };
 454
 455                 uart2m0 {
 456                         uart2m0_xfer: uart2m0-xfer {
 457                                 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
 458                                                 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
 459                         };
 460                 };
 461
 462                 uart2m1 {
 463                         uart2m1_xfer: uart2m1-xfer {
 464                                 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
 465                                                 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
 466                         };
 467                 };
 468
 469                 uart2_5v {
 470                         uart2_5v_cts: uart2_5v-cts {
 471                                 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
 472                         };
 473
 474                         uart2_5v_rts: uart2_5v-rts {
 475                                 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
 476                         };
 477                 };
 478         };
 479 };