2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/rv1108-cru.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
16 compatible = "rockchip,rv1108";
18 interrupt-parent = <&gic>;
33 compatible = "arm,cortex-a7";
39 compatible = "arm,cortex-a7-pmu";
40 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
44 compatible = "arm,armv7-timer";
45 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
46 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
47 clock-frequency = <24000000>;
51 compatible = "fixed-clock";
52 clock-frequency = <24000000>;
53 clock-output-names = "xin24m";
58 compatible = "simple-bus";
64 compatible = "arm,pl330", "arm,primecell";
65 reg = <0x102a0000 0x4000>;
66 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
68 arm,pl330-broken-no-flushp;
69 clocks = <&cru ACLK_DMAC>;
70 clock-names = "apb_pclk";
75 compatible = "mmio-sram";
76 reg = <0x10080000 0x2000>;
79 ranges = <0 0x10080000 0x2000>;
82 uart2: serial@10210000 {
83 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
84 reg = <0x10210000 0x100>;
85 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
88 clock-frequency = <24000000>;
89 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
90 clock-names = "baudclk", "apb_pclk";
91 pinctrl-names = "default";
92 pinctrl-0 = <&uart2m0_xfer>;
96 uart1: serial@10220000 {
97 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
98 reg = <0x10220000 0x100>;
99 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
102 clock-frequency = <24000000>;
103 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
104 clock-names = "baudclk", "apb_pclk";
105 pinctrl-names = "default";
106 pinctrl-0 = <&uart1_xfer>;
110 uart0: serial@10230000 {
111 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
112 reg = <0x10230000 0x100>;
113 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
116 clock-frequency = <24000000>;
117 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
118 clock-names = "baudclk", "apb_pclk";
119 pinctrl-names = "default";
120 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
124 grf: syscon@10300000 {
125 compatible = "rockchip,rv1108-grf", "syscon";
126 reg = <0x10300000 0x1000>;
129 pmugrf: syscon@20060000 {
130 compatible = "rockchip,rv1108-pmugrf", "syscon";
131 reg = <0x20060000 0x1000>;
134 cru: clock-controller@20200000 {
135 compatible = "rockchip,rv1108-cru";
136 reg = <0x20200000 0x1000>;
137 rockchip,grf = <&grf>;
142 emmc: dwmmc@30110000 {
143 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
144 clock-freq-min-max = <400000 150000000>;
145 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
146 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
147 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
148 fifo-depth = <0x100>;
149 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
150 reg = <0x30110000 0x4000>;
154 sdio: dwmmc@30120000 {
155 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
156 clock-freq-min-max = <400000 150000000>;
157 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
158 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
159 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
160 fifo-depth = <0x100>;
161 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
162 reg = <0x30120000 0x4000>;
166 sdmmc: dwmmc@30130000 {
167 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
168 clock-freq-min-max = <400000 100000000>;
169 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
170 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
171 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
172 fifo-depth = <0x100>;
173 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
174 reg = <0x30130000 0x4000>;
179 compatible = "rockchip,sfc";
180 reg = <0x301c0000 0x200>;
181 #address-cells = <1>;
183 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
185 clock-names = "clk_sfc", "hclk_sfc";
186 pinctrl-0 = <&sfc_pins>;
187 pinctrl-names = "default";
191 gmac: ethernet@30200000 {
192 compatible = "rockchip,rv1108-gmac";
193 reg = <0x30200000 0x10000>;
194 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
195 interrupt-names = "macirq";
196 rockchip,grf = <&grf>;
197 clocks = <&cru SCLK_MAC>,
198 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
199 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
200 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
201 clock-names = "stmmaceth",
202 "mac_clk_rx", "mac_clk_tx",
203 "clk_mac_ref", "clk_mac_refout",
204 "aclk_mac", "pclk_mac";
205 pinctrl-names = "default";
206 pinctrl-0 = <&rmii_pins>;
212 gic: interrupt-controller@32010000 {
213 compatible = "arm,gic-400";
214 interrupt-controller;
215 #interrupt-cells = <3>;
216 #address-cells = <0>;
218 reg = <0x32011000 0x1000>,
222 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
226 compatible = "rockchip,rv1108-pinctrl";
227 rockchip,grf = <&grf>;
228 rockchip,pmu = <&pmugrf>;
229 #address-cells = <1>;
233 gpio0: gpio0@20030000 {
234 compatible = "rockchip,gpio-bank";
235 reg = <0x20030000 0x100>;
236 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
242 interrupt-controller;
243 #interrupt-cells = <2>;
246 gpio1: gpio1@10310000 {
247 compatible = "rockchip,gpio-bank";
248 reg = <0x10310000 0x100>;
249 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
255 interrupt-controller;
256 #interrupt-cells = <2>;
259 gpio2: gpio2@10320000 {
260 compatible = "rockchip,gpio-bank";
261 reg = <0x10320000 0x100>;
262 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
268 interrupt-controller;
269 #interrupt-cells = <2>;
272 gpio3: gpio3@10330000 {
273 compatible = "rockchip,gpio-bank";
274 reg = <0x10330000 0x100>;
275 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
281 interrupt-controller;
282 #interrupt-cells = <2>;
285 pcfg_pull_up: pcfg-pull-up {
289 pcfg_pull_down: pcfg-pull-down {
293 pcfg_pull_none: pcfg-pull-none {
297 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
298 drive-strength = <8>;
301 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
302 drive-strength = <12>;
305 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
307 drive-strength = <8>;
310 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
311 drive-strength = <4>;
314 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
316 drive-strength = <4>;
319 pcfg_output_high: pcfg-output-high {
323 pcfg_output_low: pcfg-output-low {
327 pcfg_input_high: pcfg-input-high {
333 rmii_pins: rmii-pins {
334 rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
335 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>,
336 <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
337 <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
338 <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
339 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
340 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>,
341 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>,
342 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>,
343 <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
348 i2c1_xfer: i2c1-xfer {
349 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
350 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
355 i2c2m1_xfer: i2c2m1-xfer {
356 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
357 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
360 i2c2m1_gpio: i2c2m1-gpio {
361 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
362 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
367 i2c2m05v_xfer: i2c2m05v-xfer {
368 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
369 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
372 i2c2m05v_gpio: i2c2m05v-gpio {
373 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
374 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
379 i2c3_xfer: i2c3-xfer {
380 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
381 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
387 rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>,
388 <2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>,
389 <2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,
390 <2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>,
391 <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>,
392 <2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>;
397 sdmmc_clk: sdmmc-clk {
398 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
401 sdmmc_cmd: sdmmc-cmd {
402 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
406 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
409 sdmmc_bus1: sdmmc-bus1 {
410 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
413 sdmmc_bus4: sdmmc-bus4 {
414 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
415 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
416 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
417 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
422 uart0_xfer: uart0-xfer {
423 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
424 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
427 uart0_cts: uart0-cts {
428 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
431 uart0_rts: uart0-rts {
432 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
435 uart0_rts_gpio: uart0-rts-gpio {
436 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
441 uart1_xfer: uart1-xfer {
442 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
443 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
446 uart1_cts: uart1-cts {
447 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
450 uart01rts: uart1-rts {
451 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
456 uart2m0_xfer: uart2m0-xfer {
457 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
458 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
463 uart2m1_xfer: uart2m1-xfer {
464 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
465 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
470 uart2_5v_cts: uart2_5v-cts {
471 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
474 uart2_5v_rts: uart2_5v-rts {
475 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;