git.sur5r.net Git - u-boot/blob - arch/arm/dts/sama5d2.dtsi

   1 #include "skeleton.dtsi"
   2
   3 / {
   4         model = "Atmel SAMA5D2 family SoC";
   5         compatible = "atmel,sama5d2";
   6
   7         aliases {
   8                 spi0 = &spi0;
   9                 spi1 = &qspi0;
  10                 i2c0 = &i2c0;
  11                 i2c1 = &i2c1;
  12         };
  13
  14         clocks {
  15                 slow_xtal: slow_xtal {
  16                         compatible = "fixed-clock";
  17                         #clock-cells = <0>;
  18                         clock-frequency = <0>;
  19                 };
  20
  21                 main_xtal: main_xtal {
  22                         compatible = "fixed-clock";
  23                         #clock-cells = <0>;
  24                         clock-frequency = <0>;
  25                 };
  26         };
  27
  28         ahb {
  29                 compatible = "simple-bus";
  30                 #address-cells = <1>;
  31                 #size-cells = <1>;
  32
  33                 usb1: ohci@00400000 {
  34                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  35                         reg = <0x00400000 0x100000>;
  36                         clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
  37                         clock-names = "ohci_clk", "hclk", "uhpck";
  38                         status = "disabled";
  39                 };
  40
  41                 usb2: ehci@00500000 {
  42                         compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  43                         reg = <0x00500000 0x100000>;
  44                         clocks = <&utmi>, <&uhphs_clk>;
  45                         clock-names = "usb_clk", "ehci_clk";
  46                         status = "disabled";
  47                 };
  48
  49                 sdmmc0: sdio-host@a0000000 {
  50                         compatible = "atmel,sama5d2-sdhci";
  51                         reg = <0xa0000000 0x300>;
  52                         clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
  53                         clock-names = "hclock", "multclk", "baseclk";
  54                         status = "disabled";
  55                 };
  56
  57                 sdmmc1: sdio-host@b0000000 {
  58                         compatible = "atmel,sama5d2-sdhci";
  59                         reg = <0xb0000000 0x300>;
  60                         clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
  61                         clock-names = "hclock", "multclk", "baseclk";
  62                         status = "disabled";
  63                 };
  64
  65                 apb {
  66                         compatible = "simple-bus";
  67                         #address-cells = <1>;
  68                         #size-cells = <1>;
  69
  70                         pmc: pmc@f0014000 {
  71                                 compatible = "atmel,sama5d2-pmc", "syscon";
  72                                 reg = <0xf0014000 0x160>;
  73                                 #address-cells = <1>;
  74                                 #size-cells = <0>;
  75                                 #interrupt-cells = <1>;
  76
  77                                 main: mainck {
  78                                         compatible = "atmel,at91sam9x5-clk-main";
  79                                         #clock-cells = <0>;
  80                                 };
  81
  82                                 plla: pllack@0 {
  83                                         compatible = "atmel,sama5d3-clk-pll";
  84                                         #clock-cells = <0>;
  85                                         clocks = <&main>;
  86                                         reg = <0>;
  87                                         atmel,clk-input-range = <12000000 12000000>;
  88                                         #atmel,pll-clk-output-range-cells = <4>;
  89                                         atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
  90                                 };
  91
  92                                 plladiv: plladivck {
  93                                         compatible = "atmel,at91sam9x5-clk-plldiv";
  94                                         #clock-cells = <0>;
  95                                         clocks = <&plla>;
  96                                 };
  97
  98                                 audio_pll_frac: audiopll_fracck {
  99                                         compatible = "atmel,sama5d2-clk-audio-pll-frac";
 100                                         #clock-cells = <0>;
 101                                         clocks = <&main>;
 102                                 };
 103
 104                                 audio_pll_pad: audiopll_padck {
 105                                         compatible = "atmel,sama5d2-clk-audio-pll-pad";
 106                                         #clock-cells = <0>;
 107                                         clocks = <&audio_pll_frac>;
 108                                 };
 109
 110                                 audio_pll_pmc: audiopll_pmcck {
 111                                         compatible = "atmel,sama5d2-clk-audio-pll-pmc";
 112                                         #clock-cells = <0>;
 113                                         clocks = <&audio_pll_frac>;
 114                                 };
 115
 116                                 utmi: utmick {
 117                                         compatible = "atmel,at91sam9x5-clk-utmi";
 118                                         #clock-cells = <0>;
 119                                         clocks = <&main>;
 120                                 };
 121
 122                                 mck: masterck {
 123                                         compatible = "atmel,at91sam9x5-clk-master";
 124                                         #clock-cells = <0>;
 125                                         clocks = <&main>, <&plladiv>, <&utmi>;
 126                                         atmel,clk-output-range = <124000000 166000000>;
 127                                         atmel,clk-divisors = <1 2 4 3>;
 128                                 };
 129
 130                                 h32ck: h32mxck {
 131                                         #clock-cells = <0>;
 132                                         compatible = "atmel,sama5d4-clk-h32mx";
 133                                         clocks = <&mck>;
 134                                 };
 135
 136                                 usb: usbck {
 137                                         compatible = "atmel,at91sam9x5-clk-usb";
 138                                         #clock-cells = <0>;
 139                                         clocks = <&plladiv>, <&utmi>;
 140                                 };
 141
 142                                 prog: progck {
 143                                         compatible = "atmel,at91sam9x5-clk-programmable";
 144                                         #address-cells = <1>;
 145                                         #size-cells = <0>;
 146                                         interrupt-parent = <&pmc>;
 147                                         clocks = <&main>, <&plladiv>, <&utmi>, <&mck>;
 148
 149                                         prog0: prog@0 {
 150                                                 #clock-cells = <0>;
 151                                                 reg = <0>;
 152                                         };
 153
 154                                         prog1: prog@1 {
 155                                                 #clock-cells = <0>;
 156                                                 reg = <1>;
 157                                         };
 158
 159                                         prog2: prog@2 {
 160                                                 #clock-cells = <0>;
 161                                                 reg = <2>;
 162                                         };
 163                                 };
 164
 165                                 systemck {
 166                                         compatible = "atmel,at91rm9200-clk-system";
 167                                         #address-cells = <1>;
 168                                         #size-cells = <0>;
 169
 170                                         ddrck: ddrck@2 {
 171                                                 #clock-cells = <0>;
 172                                                 reg = <2>;
 173                                                 clocks = <&mck>;
 174                                         };
 175
 176                                         lcdck: lcdck@3 {
 177                                                 #clock-cells = <0>;
 178                                                 reg = <3>;
 179                                                 clocks = <&mck>;
 180                                         };
 181
 182                                         uhpck: uhpck@6 {
 183                                                 #clock-cells = <0>;
 184                                                 reg = <6>;
 185                                                 clocks = <&usb>;
 186                                         };
 187
 188                                         udpck: udpck@7 {
 189                                                 #clock-cells = <0>;
 190                                                 reg = <7>;
 191                                                 clocks = <&usb>;
 192                                         };
 193
 194                                         pck0: pck0@8 {
 195                                                 #clock-cells = <0>;
 196                                                 reg = <8>;
 197                                                 clocks = <&prog0>;
 198                                         };
 199
 200                                         pck1: pck1@9 {
 201                                                 #clock-cells = <0>;
 202                                                 reg = <9>;
 203                                                 clocks = <&prog1>;
 204                                         };
 205
 206                                         pck2: pck2@10 {
 207                                                 #clock-cells = <0>;
 208                                                 reg = <10>;
 209                                                 clocks = <&prog2>;
 210                                         };
 211
 212                                         iscck: iscck@18 {
 213                                                 #clock-cells = <0>;
 214                                                 reg = <18>;
 215                                                 clocks = <&mck>;
 216                                         };
 217                                 };
 218
 219                                 periph32ck {
 220                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 221                                         #address-cells = <1>;
 222                                         #size-cells = <0>;
 223                                         clocks = <&h32ck>;
 224
 225                                         macb0_clk: macb0_clk@5 {
 226                                                 #clock-cells = <0>;
 227                                                 reg = <5>;
 228                                                 atmel,clk-output-range = <0 83000000>;
 229                                         };
 230
 231                                         tdes_clk: tdes_clk@11 {
 232                                                 #clock-cells = <0>;
 233                                                 reg = <11>;
 234                                                 atmel,clk-output-range = <0 83000000>;
 235                                         };
 236
 237                                         matrix1_clk: matrix1_clk@14 {
 238                                                 #clock-cells = <0>;
 239                                                 reg = <14>;
 240                                         };
 241
 242                                         hsmc_clk: hsmc_clk@17 {
 243                                                 #clock-cells = <0>;
 244                                                 reg = <17>;
 245                                         };
 246
 247                                         pioA_clk: pioA_clk@18 {
 248                                                 #clock-cells = <0>;
 249                                                 reg = <18>;
 250                                                 atmel,clk-output-range = <0 83000000>;
 251                                         };
 252
 253                                         flx0_clk: flx0_clk@19 {
 254                                                 #clock-cells = <0>;
 255                                                 reg = <19>;
 256                                                 atmel,clk-output-range = <0 83000000>;
 257                                         };
 258
 259                                         flx1_clk: flx1_clk@20 {
 260                                                 #clock-cells = <0>;
 261                                                 reg = <20>;
 262                                                 atmel,clk-output-range = <0 83000000>;
 263                                         };
 264
 265                                         flx2_clk: flx2_clk@21 {
 266                                                 #clock-cells = <0>;
 267                                                 reg = <21>;
 268                                                 atmel,clk-output-range = <0 83000000>;
 269                                         };
 270
 271                                         flx3_clk: flx3_clk@22 {
 272                                                 #clock-cells = <0>;
 273                                                 reg = <22>;
 274                                                 atmel,clk-output-range = <0 83000000>;
 275                                         };
 276
 277                                         flx4_clk: flx4_clk@23 {
 278                                                 #clock-cells = <0>;
 279                                                 reg = <23>;
 280                                                 atmel,clk-output-range = <0 83000000>;
 281                                         };
 282
 283                                         uart0_clk: uart0_clk@24 {
 284                                                 #clock-cells = <0>;
 285                                                 reg = <24>;
 286                                                 atmel,clk-output-range = <0 83000000>;
 287                                         };
 288
 289                                         uart1_clk: uart1_clk@25 {
 290                                                 #clock-cells = <0>;
 291                                                 reg = <25>;
 292                                                 atmel,clk-output-range = <0 83000000>;
 293                                         };
 294
 295                                         uart2_clk: uart2_clk@26 {
 296                                                 #clock-cells = <0>;
 297                                                 reg = <26>;
 298                                                 atmel,clk-output-range = <0 83000000>;
 299                                         };
 300
 301                                         uart3_clk: uart3_clk@27 {
 302                                                 #clock-cells = <0>;
 303                                                 reg = <27>;
 304                                                 atmel,clk-output-range = <0 83000000>;
 305                                         };
 306
 307                                         uart4_clk: uart4_clk@28 {
 308                                                 #clock-cells = <0>;
 309                                                 reg = <28>;
 310                                                 atmel,clk-output-range = <0 83000000>;
 311                                         };
 312
 313                                         twi0_clk: twi0_clk@29 {
 314                                                 reg = <29>;
 315                                                 #clock-cells = <0>;
 316                                                 atmel,clk-output-range = <0 83000000>;
 317                                         };
 318
 319                                         twi1_clk: twi1_clk@30 {
 320                                                 #clock-cells = <0>;
 321                                                 reg = <30>;
 322                                                 atmel,clk-output-range = <0 83000000>;
 323                                         };
 324
 325                                         spi0_clk: spi0_clk@33 {
 326                                                 #clock-cells = <0>;
 327                                                 reg = <33>;
 328                                                 atmel,clk-output-range = <0 83000000>;
 329                                         };
 330
 331                                         spi1_clk: spi1_clk@34 {
 332                                                 #clock-cells = <0>;
 333                                                 reg = <34>;
 334                                                 atmel,clk-output-range = <0 83000000>;
 335                                         };
 336
 337                                         tcb0_clk: tcb0_clk@35 {
 338                                                 #clock-cells = <0>;
 339                                                 reg = <35>;
 340                                                 atmel,clk-output-range = <0 83000000>;
 341                                         };
 342
 343                                         tcb1_clk: tcb1_clk@36 {
 344                                                 #clock-cells = <0>;
 345                                                 reg = <36>;
 346                                                 atmel,clk-output-range = <0 83000000>;
 347                                         };
 348
 349                                         pwm_clk: pwm_clk@38 {
 350                                                 #clock-cells = <0>;
 351                                                 reg = <38>;
 352                                                 atmel,clk-output-range = <0 83000000>;
 353                                         };
 354
 355                                         adc_clk: adc_clk@40 {
 356                                                 #clock-cells = <0>;
 357                                                 reg = <40>;
 358                                                 atmel,clk-output-range = <0 83000000>;
 359                                         };
 360
 361                                         uhphs_clk: uhphs_clk@41 {
 362                                                 #clock-cells = <0>;
 363                                                 reg = <41>;
 364                                                 atmel,clk-output-range = <0 83000000>;
 365                                         };
 366
 367                                         udphs_clk: udphs_clk@42 {
 368                                                 #clock-cells = <0>;
 369                                                 reg = <42>;
 370                                                 atmel,clk-output-range = <0 83000000>;
 371                                         };
 372
 373                                         ssc0_clk: ssc0_clk@43 {
 374                                                 #clock-cells = <0>;
 375                                                 reg = <43>;
 376                                                 atmel,clk-output-range = <0 83000000>;
 377                                         };
 378
 379                                         ssc1_clk: ssc1_clk@44 {
 380                                                 #clock-cells = <0>;
 381                                                 reg = <44>;
 382                                                 atmel,clk-output-range = <0 83000000>;
 383                                         };
 384
 385                                         trng_clk: trng_clk@47 {
 386                                                 #clock-cells = <0>;
 387                                                 reg = <47>;
 388                                                 atmel,clk-output-range = <0 83000000>;
 389                                         };
 390
 391                                         pdmic_clk: pdmic_clk@48 {
 392                                                 #clock-cells = <0>;
 393                                                 reg = <48>;
 394                                                 atmel,clk-output-range = <0 83000000>;
 395                                         };
 396
 397                                         i2s0_clk: i2s0_clk@54 {
 398                                                 #clock-cells = <0>;
 399                                                 reg = <54>;
 400                                                 atmel,clk-output-range = <0 83000000>;
 401                                         };
 402
 403                                         i2s1_clk: i2s1_clk@55 {
 404                                                 #clock-cells = <0>;
 405                                                 reg = <55>;
 406                                                 atmel,clk-output-range = <0 83000000>;
 407                                         };
 408
 409                                         can0_clk: can0_clk@56 {
 410                                                 #clock-cells = <0>;
 411                                                 reg = <56>;
 412                                                 atmel,clk-output-range = <0 83000000>;
 413                                         };
 414
 415                                         can1_clk: can1_clk@57 {
 416                                                 #clock-cells = <0>;
 417                                                 reg = <57>;
 418                                                 atmel,clk-output-range = <0 83000000>;
 419                                         };
 420
 421                                         classd_clk: classd_clk@59 {
 422                                                 #clock-cells = <0>;
 423                                                 reg = <59>;
 424                                                 atmel,clk-output-range = <0 83000000>;
 425                                         };
 426                                 };
 427
 428                                 periph64ck {
 429                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 430                                         #address-cells = <1>;
 431                                         #size-cells = <0>;
 432                                         clocks = <&mck>;
 433
 434                                         dma0_clk: dma0_clk@6 {
 435                                                 #clock-cells = <0>;
 436                                                 reg = <6>;
 437                                         };
 438
 439                                         dma1_clk: dma1_clk@7 {
 440                                                 #clock-cells = <0>;
 441                                                 reg = <7>;
 442                                         };
 443
 444                                         aes_clk: aes_clk@9 {
 445                                                 #clock-cells = <0>;
 446                                                 reg = <9>;
 447                                         };
 448
 449                                         aesb_clk: aesb_clk@10 {
 450                                                 #clock-cells = <0>;
 451                                                 reg = <10>;
 452                                         };
 453
 454                                         sha_clk: sha_clk@12 {
 455                                                 #clock-cells = <0>;
 456                                                 reg = <12>;
 457                                         };
 458
 459                                         mpddr_clk: mpddr_clk@13 {
 460                                                 #clock-cells = <0>;
 461                                                 reg = <13>;
 462                                         };
 463
 464                                         matrix0_clk: matrix0_clk@15 {
 465                                                 #clock-cells = <0>;
 466                                                 reg = <15>;
 467                                         };
 468
 469                                         sdmmc0_hclk: sdmmc0_hclk@31 {
 470                                                 #clock-cells = <0>;
 471                                                 reg = <31>;
 472                                         };
 473
 474                                         sdmmc1_hclk: sdmmc1_hclk@32 {
 475                                                 #clock-cells = <0>;
 476                                                 reg = <32>;
 477                                         };
 478
 479                                         lcdc_clk: lcdc_clk@45 {
 480                                                 #clock-cells = <0>;
 481                                                 reg = <45>;
 482                                         };
 483
 484                                         isc_clk: isc_clk@46 {
 485                                                 #clock-cells = <0>;
 486                                                 reg = <46>;
 487                                         };
 488
 489                                         qspi0_clk: qspi0_clk@52 {
 490                                                 #clock-cells = <0>;
 491                                                 reg = <52>;
 492                                         };
 493
 494                                         qspi1_clk: qspi1_clk@53 {
 495                                                 #clock-cells = <0>;
 496                                                 reg = <53>;
 497                                         };
 498                                 };
 499
 500                                 gck {
 501                                         compatible = "atmel,sama5d2-clk-generated";
 502                                         #address-cells = <1>;
 503                                         #size-cells = <0>;
 504                                         interrupt-parent = <&pmc>;
 505                                         clocks = <&main>, <&plla>, <&utmi>, <&mck>;
 506
 507                                         sdmmc0_gclk: sdmmc0_gclk@31 {
 508                                                 #clock-cells = <0>;
 509                                                 reg = <31>;
 510                                         };
 511
 512                                         sdmmc1_gclk: sdmmc1_gclk@32 {
 513                                                 #clock-cells = <0>;
 514                                                 reg = <32>;
 515                                         };
 516
 517                                         tcb0_gclk: tcb0_gclk@35 {
 518                                                 #clock-cells = <0>;
 519                                                 reg = <35>;
 520                                                 atmel,clk-output-range = <0 83000000>;
 521                                         };
 522
 523                                         tcb1_gclk: tcb1_gclk@36 {
 524                                                 #clock-cells = <0>;
 525                                                 reg = <36>;
 526                                                 atmel,clk-output-range = <0 83000000>;
 527                                         };
 528
 529                                         pwm_gclk: pwm_gclk@38 {
 530                                                 #clock-cells = <0>;
 531                                                 reg = <38>;
 532                                                 atmel,clk-output-range = <0 83000000>;
 533                                         };
 534
 535                                         pdmic_gclk: pdmic_gclk@48 {
 536                                                 #clock-cells = <0>;
 537                                                 reg = <48>;
 538                                         };
 539
 540                                         i2s0_gclk: i2s0_gclk@54 {
 541                                                 #clock-cells = <0>;
 542                                                 reg = <54>;
 543                                         };
 544
 545                                         i2s1_gclk: i2s1_gclk@55 {
 546                                                 #clock-cells = <0>;
 547                                                 reg = <55>;
 548                                         };
 549
 550                                         can0_gclk: can0_gclk@56 {
 551                                                 #clock-cells = <0>;
 552                                                 reg = <56>;
 553                                                 atmel,clk-output-range = <0 80000000>;
 554                                         };
 555
 556                                         can1_gclk: can1_gclk@57 {
 557                                                 #clock-cells = <0>;
 558                                                 reg = <57>;
 559                                                 atmel,clk-output-range = <0 80000000>;
 560                                         };
 561
 562                                         classd_gclk: classd_gclk@59 {
 563                                                 #clock-cells = <0>;
 564                                                 reg = <59>;
 565                                                 atmel,clk-output-range = <0 100000000>;
 566                                         };
 567                                 };
 568                         };
 569
 570                         qspi0: spi@f0020000 {
 571                                 compatible = "atmel,sama5d2-qspi";
 572                                 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
 573                                 reg-names = "qspi_base", "qspi_mmap";
 574                                 #address-cells = <1>;
 575                                 #size-cells = <0>;
 576                                 clocks = <&qspi0_clk>;
 577                                 status = "disabled";
 578                         };
 579
 580                         spi0: spi@f8000000 {
 581                                 compatible = "atmel,at91rm9200-spi";
 582                                 reg = <0xf8000000 0x100>;
 583                                 clocks = <&spi0_clk>;
 584                                 clock-names = "spi_clk";
 585                                 #address-cells = <1>;
 586                                 #size-cells = <0>;
 587                                 status = "disabled";
 588                         };
 589
 590                         macb0: ethernet@f8008000 {
 591                                 compatible = "cdns,macb";
 592                                 reg = <0xf8008000 0x1000>;
 593                                 #address-cells = <1>;
 594                                 #size-cells = <0>;
 595                                 clocks = <&macb0_clk>, <&macb0_clk>;
 596                                 clock-names = "hclk", "pclk";
 597                                 status = "disabled";
 598                         };
 599
 600                         uart1: serial@f8020000 {
 601                                 compatible = "atmel,at91sam9260-usart";
 602                                 reg = <0xf8020000 0x100>;
 603                                 status = "disabled";
 604                         };
 605
 606                         i2c0: i2c@f8028000 {
 607                                 compatible = "atmel,sama5d2-i2c";
 608                                 reg = <0xf8028000 0x100>;
 609                                 #address-cells = <1>;
 610                                 #size-cells = <0>;
 611                                 clocks = <&twi0_clk>;
 612                                 status = "disabled";
 613                         };
 614
 615                         sckc@f8048050 {
 616                                 compatible = "atmel,at91sam9x5-sckc";
 617                                 reg = <0xf8048050 0x4>;
 618
 619                                 slow_rc_osc: slow_rc_osc {
 620                                         compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
 621                                         #clock-cells = <0>;
 622                                         clock-frequency = <32768>;
 623                                         clock-accuracy = <250000000>;
 624                                         atmel,startup-time-usec = <75>;
 625                                 };
 626
 627                                 slow_osc: slow_osc {
 628                                         compatible = "atmel,at91sam9x5-clk-slow-osc";
 629                                         #clock-cells = <0>;
 630                                         clocks = <&slow_xtal>;
 631                                         atmel,startup-time-usec = <1200000>;
 632                                 };
 633
 634                                 clk32k: slowck {
 635                                         compatible = "atmel,at91sam9x5-clk-slow";
 636                                         #clock-cells = <0>;
 637                                         clocks = <&slow_rc_osc &slow_osc>;
 638                                 };
 639                         };
 640
 641                         spi1: spi@fc000000 {
 642                                 compatible = "atmel,at91rm9200-spi";
 643                                 reg = <0xfc000000 0x100>;
 644                                 #address-cells = <1>;
 645                                 #size-cells = <0>;
 646                                 status = "disabled";
 647                         };
 648
 649                         i2c1: i2c@fc028000 {
 650                                 compatible = "atmel,sama5d2-i2c";
 651                                 reg = <0xfc028000 0x100>;
 652                                 #address-cells = <1>;
 653                                 #size-cells = <0>;
 654                                 clocks = <&twi1_clk>;
 655                                 status = "disabled";
 656                         };
 657
 658                         pioA: gpio@fc038000 {
 659                                 compatible = "atmel,sama5d2-gpio";
 660                                 reg = <0xfc038000 0x600>;
 661                                 clocks = <&pioA_clk>;
 662                                 gpio-controller;
 663                                 #gpio-cells = <2>;
 664
 665                                 pinctrl {
 666                                         compatible = "atmel,sama5d2-pinctrl";
 667                                 };
 668                         };
 669                 };
 670         };
 671 };