2 * Copyright (C) 2012 Altera <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
7 #include "skeleton.dtsi"
8 #include <dt-bindings/reset/altr,rst-mgr.h>
33 compatible = "arm,cortex-a9";
36 next-level-cache = <&L2>;
39 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
47 compatible = "arm,cortex-a9-gic";
48 #interrupt-cells = <3>;
50 reg = <0xfffed000 0x1000>,
57 compatible = "simple-bus";
59 interrupt-parent = <&intc>;
63 compatible = "arm,amba-bus";
69 compatible = "arm,pl330", "arm,primecell";
70 reg = <0xffe01000 0x1000>;
71 interrupts = <0 104 4>,
82 clocks = <&l4_main_clk>;
83 clock-names = "apb_pclk";
88 compatible = "bosch,d_can";
89 reg = <0xffc00000 0x1000>;
90 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
96 compatible = "bosch,d_can";
97 reg = <0xffc01000 0x1000>;
98 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
104 compatible = "altr,clk-mgr";
105 reg = <0xffd04000 0x1000>;
108 #address-cells = <1>;
113 compatible = "fixed-clock";
118 compatible = "fixed-clock";
121 f2s_periph_ref_clk: f2s_periph_ref_clk {
123 compatible = "fixed-clock";
126 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
128 compatible = "fixed-clock";
132 #address-cells = <1>;
135 compatible = "altr,socfpga-pll-clock";
141 compatible = "altr,socfpga-perip-clk";
142 clocks = <&main_pll>;
143 div-reg = <0xe0 0 9>;
149 compatible = "altr,socfpga-perip-clk";
150 clocks = <&main_pll>;
151 div-reg = <0xe4 0 9>;
155 dbg_base_clk: dbg_base_clk {
157 compatible = "altr,socfpga-perip-clk";
158 clocks = <&main_pll>;
159 div-reg = <0xe8 0 9>;
163 main_qspi_clk: main_qspi_clk {
165 compatible = "altr,socfpga-perip-clk";
166 clocks = <&main_pll>;
170 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
172 compatible = "altr,socfpga-perip-clk";
173 clocks = <&main_pll>;
177 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
179 compatible = "altr,socfpga-perip-clk";
180 clocks = <&main_pll>;
185 periph_pll: periph_pll {
186 #address-cells = <1>;
189 compatible = "altr,socfpga-pll-clock";
190 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
193 emac0_clk: emac0_clk {
195 compatible = "altr,socfpga-perip-clk";
196 clocks = <&periph_pll>;
200 emac1_clk: emac1_clk {
202 compatible = "altr,socfpga-perip-clk";
203 clocks = <&periph_pll>;
207 per_qspi_clk: per_qsi_clk {
209 compatible = "altr,socfpga-perip-clk";
210 clocks = <&periph_pll>;
214 per_nand_mmc_clk: per_nand_mmc_clk {
216 compatible = "altr,socfpga-perip-clk";
217 clocks = <&periph_pll>;
221 per_base_clk: per_base_clk {
223 compatible = "altr,socfpga-perip-clk";
224 clocks = <&periph_pll>;
228 h2f_usr1_clk: h2f_usr1_clk {
230 compatible = "altr,socfpga-perip-clk";
231 clocks = <&periph_pll>;
236 sdram_pll: sdram_pll {
237 #address-cells = <1>;
240 compatible = "altr,socfpga-pll-clock";
241 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
244 ddr_dqs_clk: ddr_dqs_clk {
246 compatible = "altr,socfpga-perip-clk";
247 clocks = <&sdram_pll>;
251 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
253 compatible = "altr,socfpga-perip-clk";
254 clocks = <&sdram_pll>;
258 ddr_dq_clk: ddr_dq_clk {
260 compatible = "altr,socfpga-perip-clk";
261 clocks = <&sdram_pll>;
265 h2f_usr2_clk: h2f_usr2_clk {
267 compatible = "altr,socfpga-perip-clk";
268 clocks = <&sdram_pll>;
273 mpu_periph_clk: mpu_periph_clk {
275 compatible = "altr,socfpga-perip-clk";
280 mpu_l2_ram_clk: mpu_l2_ram_clk {
282 compatible = "altr,socfpga-perip-clk";
287 l4_main_clk: l4_main_clk {
289 compatible = "altr,socfpga-gate-clk";
294 l3_main_clk: l3_main_clk {
296 compatible = "altr,socfpga-perip-clk";
301 l3_mp_clk: l3_mp_clk {
303 compatible = "altr,socfpga-gate-clk";
305 div-reg = <0x64 0 2>;
309 l3_sp_clk: l3_sp_clk {
311 compatible = "altr,socfpga-gate-clk";
313 div-reg = <0x64 2 2>;
316 l4_mp_clk: l4_mp_clk {
318 compatible = "altr,socfpga-gate-clk";
319 clocks = <&mainclk>, <&per_base_clk>;
320 div-reg = <0x64 4 3>;
324 l4_sp_clk: l4_sp_clk {
326 compatible = "altr,socfpga-gate-clk";
327 clocks = <&mainclk>, <&per_base_clk>;
328 div-reg = <0x64 7 3>;
332 dbg_at_clk: dbg_at_clk {
334 compatible = "altr,socfpga-gate-clk";
335 clocks = <&dbg_base_clk>;
336 div-reg = <0x68 0 2>;
342 compatible = "altr,socfpga-gate-clk";
343 clocks = <&dbg_base_clk>;
344 div-reg = <0x68 2 2>;
348 dbg_trace_clk: dbg_trace_clk {
350 compatible = "altr,socfpga-gate-clk";
351 clocks = <&dbg_base_clk>;
352 div-reg = <0x6C 0 3>;
356 dbg_timer_clk: dbg_timer_clk {
358 compatible = "altr,socfpga-gate-clk";
359 clocks = <&dbg_base_clk>;
365 compatible = "altr,socfpga-gate-clk";
366 clocks = <&cfg_h2f_usr0_clk>;
370 h2f_user0_clk: h2f_user0_clk {
372 compatible = "altr,socfpga-gate-clk";
373 clocks = <&cfg_h2f_usr0_clk>;
377 emac_0_clk: emac_0_clk {
379 compatible = "altr,socfpga-gate-clk";
380 clocks = <&emac0_clk>;
384 emac_1_clk: emac_1_clk {
386 compatible = "altr,socfpga-gate-clk";
387 clocks = <&emac1_clk>;
391 usb_mp_clk: usb_mp_clk {
393 compatible = "altr,socfpga-gate-clk";
394 clocks = <&per_base_clk>;
396 div-reg = <0xa4 0 3>;
399 spi_m_clk: spi_m_clk {
401 compatible = "altr,socfpga-gate-clk";
402 clocks = <&per_base_clk>;
404 div-reg = <0xa4 3 3>;
409 compatible = "altr,socfpga-gate-clk";
410 clocks = <&per_base_clk>;
412 div-reg = <0xa4 6 3>;
417 compatible = "altr,socfpga-gate-clk";
418 clocks = <&per_base_clk>;
420 div-reg = <0xa4 9 3>;
423 gpio_db_clk: gpio_db_clk {
425 compatible = "altr,socfpga-gate-clk";
426 clocks = <&per_base_clk>;
428 div-reg = <0xa8 0 24>;
431 h2f_user1_clk: h2f_user1_clk {
433 compatible = "altr,socfpga-gate-clk";
434 clocks = <&h2f_usr1_clk>;
438 sdmmc_clk: sdmmc_clk {
440 compatible = "altr,socfpga-gate-clk";
441 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
446 nand_x_clk: nand_x_clk {
448 compatible = "altr,socfpga-gate-clk";
449 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
455 compatible = "altr,socfpga-gate-clk";
456 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
457 clk-gate = <0xa0 10>;
463 compatible = "altr,socfpga-gate-clk";
464 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
465 clk-gate = <0xa0 11>;
470 gmac0: ethernet@ff700000 {
471 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
472 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
473 reg = <0xff700000 0x2000>;
474 interrupts = <0 115 4>;
475 interrupt-names = "macirq";
476 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
477 clocks = <&emac0_clk>;
478 clock-names = "stmmaceth";
479 resets = <&rst EMAC0_RESET>;
480 reset-names = "stmmaceth";
481 snps,multicast-filter-bins = <256>;
482 snps,perfect-filter-entries = <128>;
486 gmac1: ethernet@ff702000 {
487 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
488 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
489 reg = <0xff702000 0x2000>;
490 interrupts = <0 120 4>;
491 interrupt-names = "macirq";
492 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
493 clocks = <&emac1_clk>;
494 clock-names = "stmmaceth";
495 resets = <&rst EMAC1_RESET>;
496 reset-names = "stmmaceth";
497 snps,multicast-filter-bins = <256>;
498 snps,perfect-filter-entries = <128>;
503 #address-cells = <1>;
505 compatible = "snps,designware-i2c";
506 reg = <0xffc04000 0x1000>;
507 clocks = <&l4_sp_clk>;
508 interrupts = <0 158 0x4>;
513 #address-cells = <1>;
515 compatible = "snps,designware-i2c";
516 reg = <0xffc05000 0x1000>;
517 clocks = <&l4_sp_clk>;
518 interrupts = <0 159 0x4>;
523 #address-cells = <1>;
525 compatible = "snps,designware-i2c";
526 reg = <0xffc06000 0x1000>;
527 clocks = <&l4_sp_clk>;
528 interrupts = <0 160 0x4>;
533 #address-cells = <1>;
535 compatible = "snps,designware-i2c";
536 reg = <0xffc07000 0x1000>;
537 clocks = <&l4_sp_clk>;
538 interrupts = <0 161 0x4>;
542 gpio0: gpio@ff708000 {
543 #address-cells = <1>;
545 compatible = "snps,dw-apb-gpio";
546 reg = <0xff708000 0x1000>;
547 clocks = <&per_base_clk>;
550 porta: gpio-controller@0 {
551 compatible = "snps,dw-apb-gpio-port";
555 snps,nr-gpios = <29>;
557 interrupt-controller;
558 #interrupt-cells = <2>;
559 interrupts = <0 164 4>;
563 gpio1: gpio@ff709000 {
564 #address-cells = <1>;
566 compatible = "snps,dw-apb-gpio";
567 reg = <0xff709000 0x1000>;
568 clocks = <&per_base_clk>;
571 portb: gpio-controller@0 {
572 compatible = "snps,dw-apb-gpio-port";
576 snps,nr-gpios = <29>;
578 interrupt-controller;
579 #interrupt-cells = <2>;
580 interrupts = <0 165 4>;
584 gpio2: gpio@ff70a000 {
585 #address-cells = <1>;
587 compatible = "snps,dw-apb-gpio";
588 reg = <0xff70a000 0x1000>;
589 clocks = <&per_base_clk>;
592 portc: gpio-controller@0 {
593 compatible = "snps,dw-apb-gpio-port";
597 snps,nr-gpios = <27>;
599 interrupt-controller;
600 #interrupt-cells = <2>;
601 interrupts = <0 166 4>;
606 compatible = "syscon";
607 reg = <0xffc25000 0x1000>;
611 compatible = "altr,sdram-edac";
612 altr,sdr-syscon = <&sdr>;
613 interrupts = <0 39 4>;
616 L2: l2-cache@fffef000 {
617 compatible = "arm,pl310-cache";
618 reg = <0xfffef000 0x1000>;
619 interrupts = <0 38 0x04>;
622 arm,tag-latency = <1 1 1>;
623 arm,data-latency = <2 1 1>;
626 mmc0: dwmmc0@ff704000 {
627 compatible = "altr,socfpga-dw-mshc";
628 reg = <0xff704000 0x1000>;
629 interrupts = <0 139 4>;
630 fifo-depth = <0x400>;
631 #address-cells = <1>;
633 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
634 clock-names = "biu", "ciu";
638 compatible = "cadence,qspi";
639 #address-cells = <1>;
641 reg = <0xff705000 0x1000>,
643 interrupts = <0 151 4>;
644 clocks = <&qspi_clk>;
645 ext-decoder = <0>; /* external decoder */
647 cdns,fifo-depth = <128>;
648 cdns,fifo-width = <4>;
649 cdns,trigger-address = <0x00000000>;
655 compatible = "snps,dw-apb-ssi";
656 #address-cells = <1>;
658 reg = <0xfff00000 0x1000>;
659 interrupts = <0 154 4>;
662 tx-dma-channel = <&pdma 16>;
663 rx-dma-channel = <&pdma 17>;
664 clocks = <&per_base_clk>;
669 compatible = "snps,dw-apb-ssi";
670 #address-cells = <1>;
672 reg = <0xfff01000 0x1000>;
673 interrupts = <0 156 4>;
676 tx-dma-channel = <&pdma 20>;
677 rx-dma-channel = <&pdma 21>;
678 clocks = <&per_base_clk>;
684 compatible = "arm,cortex-a9-twd-timer";
685 reg = <0xfffec600 0x100>;
686 interrupts = <1 13 0xf04>;
687 clocks = <&mpu_periph_clk>;
690 timer0: timer0@ffc08000 {
691 compatible = "snps,dw-apb-timer";
692 interrupts = <0 167 4>;
693 reg = <0xffc08000 0x1000>;
694 clocks = <&l4_sp_clk>;
695 clock-names = "timer";
698 timer1: timer1@ffc09000 {
699 compatible = "snps,dw-apb-timer";
700 interrupts = <0 168 4>;
701 reg = <0xffc09000 0x1000>;
702 clocks = <&l4_sp_clk>;
703 clock-names = "timer";
706 timer2: timer2@ffd00000 {
707 compatible = "snps,dw-apb-timer";
708 interrupts = <0 169 4>;
709 reg = <0xffd00000 0x1000>;
711 clock-names = "timer";
714 timer3: timer3@ffd01000 {
715 compatible = "snps,dw-apb-timer";
716 interrupts = <0 170 4>;
717 reg = <0xffd01000 0x1000>;
719 clock-names = "timer";
722 uart0: serial0@ffc02000 {
723 compatible = "snps,dw-apb-uart";
724 reg = <0xffc02000 0x1000>;
725 interrupts = <0 162 4>;
728 clocks = <&l4_sp_clk>;
731 uart1: serial1@ffc03000 {
732 compatible = "snps,dw-apb-uart";
733 reg = <0xffc03000 0x1000>;
734 interrupts = <0 163 4>;
737 clocks = <&l4_sp_clk>;
740 rst: rstmgr@ffd05000 {
742 compatible = "altr,rst-mgr";
743 reg = <0xffd05000 0x1000>;
748 compatible = "usb-nop-xceiv";
753 compatible = "snps,dwc2";
754 reg = <0xffb00000 0xffff>;
755 interrupts = <0 125 4>;
756 clocks = <&usb_mp_clk>;
759 phy-names = "usb2-phy";
764 compatible = "snps,dwc2";
765 reg = <0xffb40000 0xffff>;
766 interrupts = <0 128 4>;
767 clocks = <&usb_mp_clk>;
770 phy-names = "usb2-phy";
774 watchdog0: watchdog@ffd02000 {
775 compatible = "snps,dw-wdt";
776 reg = <0xffd02000 0x1000>;
777 interrupts = <0 171 4>;
782 watchdog1: watchdog@ffd03000 {
783 compatible = "snps,dw-wdt";
784 reg = <0xffd03000 0x1000>;
785 interrupts = <0 172 4>;
790 sysmgr: sysmgr@ffd08000 {
791 compatible = "altr,sys-mgr", "syscon";
792 reg = <0xffd08000 0x4000>;