2 * Copyright (C) 2012 Altera <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
7 #include "skeleton.dtsi"
8 #include <dt-bindings/reset/altr,rst-mgr.h>
34 compatible = "arm,cortex-a9";
37 next-level-cache = <&L2>;
40 compatible = "arm,cortex-a9";
43 next-level-cache = <&L2>;
48 compatible = "arm,cortex-a9-gic";
49 #interrupt-cells = <3>;
51 reg = <0xfffed000 0x1000>,
58 compatible = "simple-bus";
60 interrupt-parent = <&intc>;
64 compatible = "arm,amba-bus";
70 compatible = "arm,pl330", "arm,primecell";
71 reg = <0xffe01000 0x1000>;
72 interrupts = <0 104 4>,
83 clocks = <&l4_main_clk>;
84 clock-names = "apb_pclk";
89 compatible = "bosch,d_can";
90 reg = <0xffc00000 0x1000>;
91 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
97 compatible = "bosch,d_can";
98 reg = <0xffc01000 0x1000>;
99 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
100 clocks = <&can1_clk>;
105 compatible = "altr,clk-mgr";
106 reg = <0xffd04000 0x1000>;
109 #address-cells = <1>;
114 compatible = "fixed-clock";
119 compatible = "fixed-clock";
122 f2s_periph_ref_clk: f2s_periph_ref_clk {
124 compatible = "fixed-clock";
127 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
129 compatible = "fixed-clock";
133 #address-cells = <1>;
136 compatible = "altr,socfpga-pll-clock";
142 compatible = "altr,socfpga-perip-clk";
143 clocks = <&main_pll>;
144 div-reg = <0xe0 0 9>;
150 compatible = "altr,socfpga-perip-clk";
151 clocks = <&main_pll>;
152 div-reg = <0xe4 0 9>;
156 dbg_base_clk: dbg_base_clk {
158 compatible = "altr,socfpga-perip-clk";
159 clocks = <&main_pll>;
160 div-reg = <0xe8 0 9>;
164 main_qspi_clk: main_qspi_clk {
166 compatible = "altr,socfpga-perip-clk";
167 clocks = <&main_pll>;
171 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
173 compatible = "altr,socfpga-perip-clk";
174 clocks = <&main_pll>;
178 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
180 compatible = "altr,socfpga-perip-clk";
181 clocks = <&main_pll>;
186 periph_pll: periph_pll {
187 #address-cells = <1>;
190 compatible = "altr,socfpga-pll-clock";
191 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
194 emac0_clk: emac0_clk {
196 compatible = "altr,socfpga-perip-clk";
197 clocks = <&periph_pll>;
201 emac1_clk: emac1_clk {
203 compatible = "altr,socfpga-perip-clk";
204 clocks = <&periph_pll>;
208 per_qspi_clk: per_qsi_clk {
210 compatible = "altr,socfpga-perip-clk";
211 clocks = <&periph_pll>;
215 per_nand_mmc_clk: per_nand_mmc_clk {
217 compatible = "altr,socfpga-perip-clk";
218 clocks = <&periph_pll>;
222 per_base_clk: per_base_clk {
224 compatible = "altr,socfpga-perip-clk";
225 clocks = <&periph_pll>;
229 h2f_usr1_clk: h2f_usr1_clk {
231 compatible = "altr,socfpga-perip-clk";
232 clocks = <&periph_pll>;
237 sdram_pll: sdram_pll {
238 #address-cells = <1>;
241 compatible = "altr,socfpga-pll-clock";
242 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
245 ddr_dqs_clk: ddr_dqs_clk {
247 compatible = "altr,socfpga-perip-clk";
248 clocks = <&sdram_pll>;
252 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
254 compatible = "altr,socfpga-perip-clk";
255 clocks = <&sdram_pll>;
259 ddr_dq_clk: ddr_dq_clk {
261 compatible = "altr,socfpga-perip-clk";
262 clocks = <&sdram_pll>;
266 h2f_usr2_clk: h2f_usr2_clk {
268 compatible = "altr,socfpga-perip-clk";
269 clocks = <&sdram_pll>;
274 mpu_periph_clk: mpu_periph_clk {
276 compatible = "altr,socfpga-perip-clk";
281 mpu_l2_ram_clk: mpu_l2_ram_clk {
283 compatible = "altr,socfpga-perip-clk";
288 l4_main_clk: l4_main_clk {
290 compatible = "altr,socfpga-gate-clk";
295 l3_main_clk: l3_main_clk {
297 compatible = "altr,socfpga-perip-clk";
302 l3_mp_clk: l3_mp_clk {
304 compatible = "altr,socfpga-gate-clk";
306 div-reg = <0x64 0 2>;
310 l3_sp_clk: l3_sp_clk {
312 compatible = "altr,socfpga-gate-clk";
314 div-reg = <0x64 2 2>;
317 l4_mp_clk: l4_mp_clk {
319 compatible = "altr,socfpga-gate-clk";
320 clocks = <&mainclk>, <&per_base_clk>;
321 div-reg = <0x64 4 3>;
325 l4_sp_clk: l4_sp_clk {
327 compatible = "altr,socfpga-gate-clk";
328 clocks = <&mainclk>, <&per_base_clk>;
329 div-reg = <0x64 7 3>;
333 dbg_at_clk: dbg_at_clk {
335 compatible = "altr,socfpga-gate-clk";
336 clocks = <&dbg_base_clk>;
337 div-reg = <0x68 0 2>;
343 compatible = "altr,socfpga-gate-clk";
344 clocks = <&dbg_base_clk>;
345 div-reg = <0x68 2 2>;
349 dbg_trace_clk: dbg_trace_clk {
351 compatible = "altr,socfpga-gate-clk";
352 clocks = <&dbg_base_clk>;
353 div-reg = <0x6C 0 3>;
357 dbg_timer_clk: dbg_timer_clk {
359 compatible = "altr,socfpga-gate-clk";
360 clocks = <&dbg_base_clk>;
366 compatible = "altr,socfpga-gate-clk";
367 clocks = <&cfg_h2f_usr0_clk>;
371 h2f_user0_clk: h2f_user0_clk {
373 compatible = "altr,socfpga-gate-clk";
374 clocks = <&cfg_h2f_usr0_clk>;
378 emac_0_clk: emac_0_clk {
380 compatible = "altr,socfpga-gate-clk";
381 clocks = <&emac0_clk>;
385 emac_1_clk: emac_1_clk {
387 compatible = "altr,socfpga-gate-clk";
388 clocks = <&emac1_clk>;
392 usb_mp_clk: usb_mp_clk {
394 compatible = "altr,socfpga-gate-clk";
395 clocks = <&per_base_clk>;
397 div-reg = <0xa4 0 3>;
400 spi_m_clk: spi_m_clk {
402 compatible = "altr,socfpga-gate-clk";
403 clocks = <&per_base_clk>;
405 div-reg = <0xa4 3 3>;
410 compatible = "altr,socfpga-gate-clk";
411 clocks = <&per_base_clk>;
413 div-reg = <0xa4 6 3>;
418 compatible = "altr,socfpga-gate-clk";
419 clocks = <&per_base_clk>;
421 div-reg = <0xa4 9 3>;
424 gpio_db_clk: gpio_db_clk {
426 compatible = "altr,socfpga-gate-clk";
427 clocks = <&per_base_clk>;
429 div-reg = <0xa8 0 24>;
432 h2f_user1_clk: h2f_user1_clk {
434 compatible = "altr,socfpga-gate-clk";
435 clocks = <&h2f_usr1_clk>;
439 sdmmc_clk: sdmmc_clk {
441 compatible = "altr,socfpga-gate-clk";
442 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
447 nand_x_clk: nand_x_clk {
449 compatible = "altr,socfpga-gate-clk";
450 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
456 compatible = "altr,socfpga-gate-clk";
457 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
458 clk-gate = <0xa0 10>;
464 compatible = "altr,socfpga-gate-clk";
465 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
466 clk-gate = <0xa0 11>;
471 gmac0: ethernet@ff700000 {
472 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
473 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
474 reg = <0xff700000 0x2000>;
475 interrupts = <0 115 4>;
476 interrupt-names = "macirq";
477 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
478 clocks = <&emac0_clk>;
479 clock-names = "stmmaceth";
480 resets = <&rst EMAC0_RESET>;
481 reset-names = "stmmaceth";
482 snps,multicast-filter-bins = <256>;
483 snps,perfect-filter-entries = <128>;
487 gmac1: ethernet@ff702000 {
488 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
489 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
490 reg = <0xff702000 0x2000>;
491 interrupts = <0 120 4>;
492 interrupt-names = "macirq";
493 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
494 clocks = <&emac1_clk>;
495 clock-names = "stmmaceth";
496 resets = <&rst EMAC1_RESET>;
497 reset-names = "stmmaceth";
498 snps,multicast-filter-bins = <256>;
499 snps,perfect-filter-entries = <128>;
504 #address-cells = <1>;
506 compatible = "snps,designware-i2c";
507 reg = <0xffc04000 0x1000>;
508 clocks = <&l4_sp_clk>;
509 interrupts = <0 158 0x4>;
514 #address-cells = <1>;
516 compatible = "snps,designware-i2c";
517 reg = <0xffc05000 0x1000>;
518 clocks = <&l4_sp_clk>;
519 interrupts = <0 159 0x4>;
524 #address-cells = <1>;
526 compatible = "snps,designware-i2c";
527 reg = <0xffc06000 0x1000>;
528 clocks = <&l4_sp_clk>;
529 interrupts = <0 160 0x4>;
534 #address-cells = <1>;
536 compatible = "snps,designware-i2c";
537 reg = <0xffc07000 0x1000>;
538 clocks = <&l4_sp_clk>;
539 interrupts = <0 161 0x4>;
543 gpio0: gpio@ff708000 {
544 #address-cells = <1>;
546 compatible = "snps,dw-apb-gpio";
547 reg = <0xff708000 0x1000>;
548 clocks = <&per_base_clk>;
551 porta: gpio-controller@0 {
552 compatible = "snps,dw-apb-gpio-port";
555 snps,nr-gpios = <29>;
557 interrupt-controller;
558 #interrupt-cells = <2>;
559 interrupts = <0 164 4>;
563 gpio1: gpio@ff709000 {
564 #address-cells = <1>;
566 compatible = "snps,dw-apb-gpio";
567 reg = <0xff709000 0x1000>;
568 clocks = <&per_base_clk>;
571 portb: gpio-controller@0 {
572 compatible = "snps,dw-apb-gpio-port";
575 snps,nr-gpios = <29>;
577 interrupt-controller;
578 #interrupt-cells = <2>;
579 interrupts = <0 165 4>;
583 gpio2: gpio@ff70a000 {
584 #address-cells = <1>;
586 compatible = "snps,dw-apb-gpio";
587 reg = <0xff70a000 0x1000>;
588 clocks = <&per_base_clk>;
591 portc: gpio-controller@0 {
592 compatible = "snps,dw-apb-gpio-port";
595 snps,nr-gpios = <27>;
597 interrupt-controller;
598 #interrupt-cells = <2>;
599 interrupts = <0 166 4>;
604 compatible = "syscon";
605 reg = <0xffc25000 0x1000>;
609 compatible = "altr,sdram-edac";
610 altr,sdr-syscon = <&sdr>;
611 interrupts = <0 39 4>;
614 L2: l2-cache@fffef000 {
615 compatible = "arm,pl310-cache";
616 reg = <0xfffef000 0x1000>;
617 interrupts = <0 38 0x04>;
620 arm,tag-latency = <1 1 1>;
621 arm,data-latency = <2 1 1>;
624 mmc: dwmmc0@ff704000 {
625 compatible = "altr,socfpga-dw-mshc";
626 reg = <0xff704000 0x1000>;
627 interrupts = <0 139 4>;
628 fifo-depth = <0x400>;
629 #address-cells = <1>;
631 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
632 clock-names = "biu", "ciu";
636 compatible = "cadence,qspi";
637 #address-cells = <1>;
639 reg = <0xff705000 0x1000>,
641 interrupts = <0 151 4>;
642 clocks = <&qspi_clk>;
643 ext-decoder = <0>; /* external decoder */
652 compatible = "snps,dw-apb-ssi";
653 #address-cells = <1>;
655 reg = <0xfff00000 0x1000>;
656 interrupts = <0 154 4>;
659 tx-dma-channel = <&pdma 16>;
660 rx-dma-channel = <&pdma 17>;
661 clocks = <&per_base_clk>;
666 compatible = "snps,dw-apb-ssi";
667 #address-cells = <1>;
669 reg = <0xfff01000 0x1000>;
670 interrupts = <0 156 4>;
673 tx-dma-channel = <&pdma 20>;
674 rx-dma-channel = <&pdma 21>;
675 clocks = <&per_base_clk>;
681 compatible = "arm,cortex-a9-twd-timer";
682 reg = <0xfffec600 0x100>;
683 interrupts = <1 13 0xf04>;
684 clocks = <&mpu_periph_clk>;
687 timer0: timer0@ffc08000 {
688 compatible = "snps,dw-apb-timer";
689 interrupts = <0 167 4>;
690 reg = <0xffc08000 0x1000>;
691 clocks = <&l4_sp_clk>;
692 clock-names = "timer";
695 timer1: timer1@ffc09000 {
696 compatible = "snps,dw-apb-timer";
697 interrupts = <0 168 4>;
698 reg = <0xffc09000 0x1000>;
699 clocks = <&l4_sp_clk>;
700 clock-names = "timer";
703 timer2: timer2@ffd00000 {
704 compatible = "snps,dw-apb-timer";
705 interrupts = <0 169 4>;
706 reg = <0xffd00000 0x1000>;
708 clock-names = "timer";
711 timer3: timer3@ffd01000 {
712 compatible = "snps,dw-apb-timer";
713 interrupts = <0 170 4>;
714 reg = <0xffd01000 0x1000>;
716 clock-names = "timer";
719 uart0: serial0@ffc02000 {
720 compatible = "snps,dw-apb-uart";
721 reg = <0xffc02000 0x1000>;
722 interrupts = <0 162 4>;
725 clocks = <&l4_sp_clk>;
728 uart1: serial1@ffc03000 {
729 compatible = "snps,dw-apb-uart";
730 reg = <0xffc03000 0x1000>;
731 interrupts = <0 163 4>;
734 clocks = <&l4_sp_clk>;
737 rst: rstmgr@ffd05000 {
739 compatible = "altr,rst-mgr";
740 reg = <0xffd05000 0x1000>;
745 compatible = "usb-nop-xceiv";
750 compatible = "snps,dwc2";
751 reg = <0xffb00000 0xffff>;
752 interrupts = <0 125 4>;
753 clocks = <&usb_mp_clk>;
756 phy-names = "usb2-phy";
761 compatible = "snps,dwc2";
762 reg = <0xffb40000 0xffff>;
763 interrupts = <0 128 4>;
764 clocks = <&usb_mp_clk>;
767 phy-names = "usb2-phy";
771 watchdog0: watchdog@ffd02000 {
772 compatible = "snps,dw-wdt";
773 reg = <0xffd02000 0x1000>;
774 interrupts = <0 171 4>;
779 watchdog1: watchdog@ffd03000 {
780 compatible = "snps,dw-wdt";
781 reg = <0xffd03000 0x1000>;
782 interrupts = <0 172 4>;
787 sysmgr: sysmgr@ffd08000 {
788 compatible = "altr,sys-mgr", "syscon";
789 reg = <0xffd08000 0x4000>;