2 * Copyright (C) 2012 Altera <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
7 #include "skeleton.dtsi"
8 #include <dt-bindings/reset/altr,rst-mgr.h>
37 compatible = "arm,cortex-a9";
40 next-level-cache = <&L2>;
43 compatible = "arm,cortex-a9";
46 next-level-cache = <&L2>;
51 compatible = "arm,cortex-a9-gic";
52 #interrupt-cells = <3>;
54 reg = <0xfffed000 0x1000>,
61 compatible = "simple-bus";
63 interrupt-parent = <&intc>;
67 compatible = "arm,amba-bus";
73 compatible = "arm,pl330", "arm,primecell";
74 reg = <0xffe01000 0x1000>;
75 interrupts = <0 104 4>,
86 clocks = <&l4_main_clk>;
87 clock-names = "apb_pclk";
92 compatible = "bosch,d_can";
93 reg = <0xffc00000 0x1000>;
94 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
100 compatible = "bosch,d_can";
101 reg = <0xffc01000 0x1000>;
102 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
103 clocks = <&can1_clk>;
108 compatible = "altr,clk-mgr";
109 reg = <0xffd04000 0x1000>;
112 #address-cells = <1>;
117 compatible = "fixed-clock";
122 compatible = "fixed-clock";
125 f2s_periph_ref_clk: f2s_periph_ref_clk {
127 compatible = "fixed-clock";
130 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
132 compatible = "fixed-clock";
136 #address-cells = <1>;
139 compatible = "altr,socfpga-pll-clock";
145 compatible = "altr,socfpga-perip-clk";
146 clocks = <&main_pll>;
147 div-reg = <0xe0 0 9>;
153 compatible = "altr,socfpga-perip-clk";
154 clocks = <&main_pll>;
155 div-reg = <0xe4 0 9>;
159 dbg_base_clk: dbg_base_clk {
161 compatible = "altr,socfpga-perip-clk";
162 clocks = <&main_pll>;
163 div-reg = <0xe8 0 9>;
167 main_qspi_clk: main_qspi_clk {
169 compatible = "altr,socfpga-perip-clk";
170 clocks = <&main_pll>;
174 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
176 compatible = "altr,socfpga-perip-clk";
177 clocks = <&main_pll>;
181 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
183 compatible = "altr,socfpga-perip-clk";
184 clocks = <&main_pll>;
189 periph_pll: periph_pll {
190 #address-cells = <1>;
193 compatible = "altr,socfpga-pll-clock";
194 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
197 emac0_clk: emac0_clk {
199 compatible = "altr,socfpga-perip-clk";
200 clocks = <&periph_pll>;
204 emac1_clk: emac1_clk {
206 compatible = "altr,socfpga-perip-clk";
207 clocks = <&periph_pll>;
211 per_qspi_clk: per_qsi_clk {
213 compatible = "altr,socfpga-perip-clk";
214 clocks = <&periph_pll>;
218 per_nand_mmc_clk: per_nand_mmc_clk {
220 compatible = "altr,socfpga-perip-clk";
221 clocks = <&periph_pll>;
225 per_base_clk: per_base_clk {
227 compatible = "altr,socfpga-perip-clk";
228 clocks = <&periph_pll>;
232 h2f_usr1_clk: h2f_usr1_clk {
234 compatible = "altr,socfpga-perip-clk";
235 clocks = <&periph_pll>;
240 sdram_pll: sdram_pll {
241 #address-cells = <1>;
244 compatible = "altr,socfpga-pll-clock";
245 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
248 ddr_dqs_clk: ddr_dqs_clk {
250 compatible = "altr,socfpga-perip-clk";
251 clocks = <&sdram_pll>;
255 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
257 compatible = "altr,socfpga-perip-clk";
258 clocks = <&sdram_pll>;
262 ddr_dq_clk: ddr_dq_clk {
264 compatible = "altr,socfpga-perip-clk";
265 clocks = <&sdram_pll>;
269 h2f_usr2_clk: h2f_usr2_clk {
271 compatible = "altr,socfpga-perip-clk";
272 clocks = <&sdram_pll>;
277 mpu_periph_clk: mpu_periph_clk {
279 compatible = "altr,socfpga-perip-clk";
284 mpu_l2_ram_clk: mpu_l2_ram_clk {
286 compatible = "altr,socfpga-perip-clk";
291 l4_main_clk: l4_main_clk {
293 compatible = "altr,socfpga-gate-clk";
298 l3_main_clk: l3_main_clk {
300 compatible = "altr,socfpga-perip-clk";
305 l3_mp_clk: l3_mp_clk {
307 compatible = "altr,socfpga-gate-clk";
309 div-reg = <0x64 0 2>;
313 l3_sp_clk: l3_sp_clk {
315 compatible = "altr,socfpga-gate-clk";
317 div-reg = <0x64 2 2>;
320 l4_mp_clk: l4_mp_clk {
322 compatible = "altr,socfpga-gate-clk";
323 clocks = <&mainclk>, <&per_base_clk>;
324 div-reg = <0x64 4 3>;
328 l4_sp_clk: l4_sp_clk {
330 compatible = "altr,socfpga-gate-clk";
331 clocks = <&mainclk>, <&per_base_clk>;
332 div-reg = <0x64 7 3>;
336 dbg_at_clk: dbg_at_clk {
338 compatible = "altr,socfpga-gate-clk";
339 clocks = <&dbg_base_clk>;
340 div-reg = <0x68 0 2>;
346 compatible = "altr,socfpga-gate-clk";
347 clocks = <&dbg_base_clk>;
348 div-reg = <0x68 2 2>;
352 dbg_trace_clk: dbg_trace_clk {
354 compatible = "altr,socfpga-gate-clk";
355 clocks = <&dbg_base_clk>;
356 div-reg = <0x6C 0 3>;
360 dbg_timer_clk: dbg_timer_clk {
362 compatible = "altr,socfpga-gate-clk";
363 clocks = <&dbg_base_clk>;
369 compatible = "altr,socfpga-gate-clk";
370 clocks = <&cfg_h2f_usr0_clk>;
374 h2f_user0_clk: h2f_user0_clk {
376 compatible = "altr,socfpga-gate-clk";
377 clocks = <&cfg_h2f_usr0_clk>;
381 emac_0_clk: emac_0_clk {
383 compatible = "altr,socfpga-gate-clk";
384 clocks = <&emac0_clk>;
388 emac_1_clk: emac_1_clk {
390 compatible = "altr,socfpga-gate-clk";
391 clocks = <&emac1_clk>;
395 usb_mp_clk: usb_mp_clk {
397 compatible = "altr,socfpga-gate-clk";
398 clocks = <&per_base_clk>;
400 div-reg = <0xa4 0 3>;
403 spi_m_clk: spi_m_clk {
405 compatible = "altr,socfpga-gate-clk";
406 clocks = <&per_base_clk>;
408 div-reg = <0xa4 3 3>;
413 compatible = "altr,socfpga-gate-clk";
414 clocks = <&per_base_clk>;
416 div-reg = <0xa4 6 3>;
421 compatible = "altr,socfpga-gate-clk";
422 clocks = <&per_base_clk>;
424 div-reg = <0xa4 9 3>;
427 gpio_db_clk: gpio_db_clk {
429 compatible = "altr,socfpga-gate-clk";
430 clocks = <&per_base_clk>;
432 div-reg = <0xa8 0 24>;
435 h2f_user1_clk: h2f_user1_clk {
437 compatible = "altr,socfpga-gate-clk";
438 clocks = <&h2f_usr1_clk>;
442 sdmmc_clk: sdmmc_clk {
444 compatible = "altr,socfpga-gate-clk";
445 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
450 nand_x_clk: nand_x_clk {
452 compatible = "altr,socfpga-gate-clk";
453 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
459 compatible = "altr,socfpga-gate-clk";
460 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
461 clk-gate = <0xa0 10>;
467 compatible = "altr,socfpga-gate-clk";
468 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
469 clk-gate = <0xa0 11>;
474 gmac0: ethernet@ff700000 {
475 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
476 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
477 reg = <0xff700000 0x2000>;
478 interrupts = <0 115 4>;
479 interrupt-names = "macirq";
480 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
481 clocks = <&emac0_clk>;
482 clock-names = "stmmaceth";
483 resets = <&rst EMAC0_RESET>;
484 reset-names = "stmmaceth";
485 snps,multicast-filter-bins = <256>;
486 snps,perfect-filter-entries = <128>;
490 gmac1: ethernet@ff702000 {
491 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
492 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
493 reg = <0xff702000 0x2000>;
494 interrupts = <0 120 4>;
495 interrupt-names = "macirq";
496 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
497 clocks = <&emac1_clk>;
498 clock-names = "stmmaceth";
499 resets = <&rst EMAC1_RESET>;
500 reset-names = "stmmaceth";
501 snps,multicast-filter-bins = <256>;
502 snps,perfect-filter-entries = <128>;
507 #address-cells = <1>;
509 compatible = "snps,designware-i2c";
510 reg = <0xffc04000 0x1000>;
511 clocks = <&l4_sp_clk>;
512 resets = <&rst I2C0_RESET>;
514 interrupts = <0 158 0x4>;
519 #address-cells = <1>;
521 compatible = "snps,designware-i2c";
522 reg = <0xffc05000 0x1000>;
523 clocks = <&l4_sp_clk>;
524 resets = <&rst I2C1_RESET>;
526 interrupts = <0 159 0x4>;
531 #address-cells = <1>;
533 compatible = "snps,designware-i2c";
534 reg = <0xffc06000 0x1000>;
535 clocks = <&l4_sp_clk>;
536 resets = <&rst I2C2_RESET>;
538 interrupts = <0 160 0x4>;
543 #address-cells = <1>;
545 compatible = "snps,designware-i2c";
546 reg = <0xffc07000 0x1000>;
547 clocks = <&l4_sp_clk>;
548 resets = <&rst I2C3_RESET>;
550 interrupts = <0 161 0x4>;
554 gpio0: gpio@ff708000 {
555 #address-cells = <1>;
557 compatible = "snps,dw-apb-gpio";
558 reg = <0xff708000 0x1000>;
559 clocks = <&per_base_clk>;
562 porta: gpio-controller@0 {
563 compatible = "snps,dw-apb-gpio-port";
567 snps,nr-gpios = <29>;
569 interrupt-controller;
570 #interrupt-cells = <2>;
571 interrupts = <0 164 4>;
575 gpio1: gpio@ff709000 {
576 #address-cells = <1>;
578 compatible = "snps,dw-apb-gpio";
579 reg = <0xff709000 0x1000>;
580 clocks = <&per_base_clk>;
583 portb: gpio-controller@0 {
584 compatible = "snps,dw-apb-gpio-port";
588 snps,nr-gpios = <29>;
590 interrupt-controller;
591 #interrupt-cells = <2>;
592 interrupts = <0 165 4>;
596 gpio2: gpio@ff70a000 {
597 #address-cells = <1>;
599 compatible = "snps,dw-apb-gpio";
600 reg = <0xff70a000 0x1000>;
601 clocks = <&per_base_clk>;
604 portc: gpio-controller@0 {
605 compatible = "snps,dw-apb-gpio-port";
609 snps,nr-gpios = <27>;
611 interrupt-controller;
612 #interrupt-cells = <2>;
613 interrupts = <0 166 4>;
618 compatible = "syscon";
619 reg = <0xffc25000 0x1000>;
623 compatible = "altr,sdram-edac";
624 altr,sdr-syscon = <&sdr>;
625 interrupts = <0 39 4>;
628 L2: l2-cache@fffef000 {
629 compatible = "arm,pl310-cache";
630 reg = <0xfffef000 0x1000>;
631 interrupts = <0 38 0x04>;
634 arm,tag-latency = <1 1 1>;
635 arm,data-latency = <2 1 1>;
638 mmc0: dwmmc0@ff704000 {
639 compatible = "altr,socfpga-dw-mshc";
640 reg = <0xff704000 0x1000>;
641 interrupts = <0 139 4>;
642 fifo-depth = <0x400>;
643 #address-cells = <1>;
645 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
646 clock-names = "biu", "ciu";
650 compatible = "cadence,qspi";
651 #address-cells = <1>;
653 reg = <0xff705000 0x1000>,
655 interrupts = <0 151 4>;
656 clocks = <&qspi_clk>;
657 ext-decoder = <0>; /* external decoder */
659 cdns,fifo-depth = <128>;
660 cdns,fifo-width = <4>;
661 cdns,trigger-address = <0x00000000>;
667 compatible = "snps,dw-apb-ssi";
668 #address-cells = <1>;
670 reg = <0xfff00000 0x1000>;
671 interrupts = <0 154 4>;
674 tx-dma-channel = <&pdma 16>;
675 rx-dma-channel = <&pdma 17>;
676 clocks = <&per_base_clk>;
681 compatible = "snps,dw-apb-ssi";
682 #address-cells = <1>;
684 reg = <0xfff01000 0x1000>;
685 interrupts = <0 156 4>;
688 tx-dma-channel = <&pdma 20>;
689 rx-dma-channel = <&pdma 21>;
690 clocks = <&per_base_clk>;
696 compatible = "arm,cortex-a9-twd-timer";
697 reg = <0xfffec600 0x100>;
698 interrupts = <1 13 0xf04>;
699 clocks = <&mpu_periph_clk>;
702 timer0: timer0@ffc08000 {
703 compatible = "snps,dw-apb-timer";
704 interrupts = <0 167 4>;
705 reg = <0xffc08000 0x1000>;
706 clocks = <&l4_sp_clk>;
707 clock-names = "timer";
710 timer1: timer1@ffc09000 {
711 compatible = "snps,dw-apb-timer";
712 interrupts = <0 168 4>;
713 reg = <0xffc09000 0x1000>;
714 clocks = <&l4_sp_clk>;
715 clock-names = "timer";
718 timer2: timer2@ffd00000 {
719 compatible = "snps,dw-apb-timer";
720 interrupts = <0 169 4>;
721 reg = <0xffd00000 0x1000>;
723 clock-names = "timer";
726 timer3: timer3@ffd01000 {
727 compatible = "snps,dw-apb-timer";
728 interrupts = <0 170 4>;
729 reg = <0xffd01000 0x1000>;
731 clock-names = "timer";
734 uart0: serial0@ffc02000 {
735 compatible = "snps,dw-apb-uart";
736 reg = <0xffc02000 0x1000>;
737 interrupts = <0 162 4>;
740 clocks = <&l4_sp_clk>;
743 uart1: serial1@ffc03000 {
744 compatible = "snps,dw-apb-uart";
745 reg = <0xffc03000 0x1000>;
746 interrupts = <0 163 4>;
749 clocks = <&l4_sp_clk>;
752 rst: rstmgr@ffd05000 {
754 compatible = "altr,rst-mgr";
755 reg = <0xffd05000 0x1000>;
760 compatible = "usb-nop-xceiv";
765 compatible = "snps,dwc2";
766 reg = <0xffb00000 0xffff>;
767 interrupts = <0 125 4>;
768 clocks = <&usb_mp_clk>;
771 phy-names = "usb2-phy";
776 compatible = "snps,dwc2";
777 reg = <0xffb40000 0xffff>;
778 interrupts = <0 128 4>;
779 clocks = <&usb_mp_clk>;
782 phy-names = "usb2-phy";
786 watchdog0: watchdog@ffd02000 {
787 compatible = "snps,dw-wdt";
788 reg = <0xffd02000 0x1000>;
789 interrupts = <0 171 4>;
794 watchdog1: watchdog@ffd03000 {
795 compatible = "snps,dw-wdt";
796 reg = <0xffd03000 0x1000>;
797 interrupts = <0 172 4>;
802 sysmgr: sysmgr@ffd08000 {
803 compatible = "altr,sys-mgr", "syscon";
804 reg = <0xffd08000 0x4000>;