git.sur5r.net Git - u-boot/blob - arch/arm/dts/socfpga.dtsi

   1 /*
   2  *  Copyright (C) 2012 Altera <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include "skeleton.dtsi"
   8 #include <dt-bindings/reset/altr,rst-mgr.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         aliases {
  15                 ethernet0 = &gmac0;
  16                 ethernet1 = &gmac1;
  17                 i2c0 = &i2c0;
  18                 i2c1 = &i2c1;
  19                 i2c2 = &i2c2;
  20                 i2c3 = &i2c3;
  21                 serial0 = &uart0;
  22                 serial1 = &uart1;
  23                 timer0 = &timer0;
  24                 timer1 = &timer1;
  25                 timer2 = &timer2;
  26                 timer3 = &timer3;
  27                 spi0 = &qspi;
  28                 spi1 = &spi0;
  29                 spi2 = &spi1;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 cpu@0 {
  37                         compatible = "arm,cortex-a9";
  38                         device_type = "cpu";
  39                         reg = <0>;
  40                         next-level-cache = <&L2>;
  41                 };
  42                 cpu@1 {
  43                         compatible = "arm,cortex-a9";
  44                         device_type = "cpu";
  45                         reg = <1>;
  46                         next-level-cache = <&L2>;
  47                 };
  48         };
  49
  50         intc: intc@fffed000 {
  51                 compatible = "arm,cortex-a9-gic";
  52                 #interrupt-cells = <3>;
  53                 interrupt-controller;
  54                 reg = <0xfffed000 0x1000>,
  55                       <0xfffec100 0x100>;
  56         };
  57
  58         soc {
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61                 compatible = "simple-bus";
  62                 device_type = "soc";
  63                 interrupt-parent = <&intc>;
  64                 ranges;
  65
  66                 amba {
  67                         compatible = "arm,amba-bus";
  68                         #address-cells = <1>;
  69                         #size-cells = <1>;
  70                         ranges;
  71
  72                         pdma: pdma@ffe01000 {
  73                                 compatible = "arm,pl330", "arm,primecell";
  74                                 reg = <0xffe01000 0x1000>;
  75                                 interrupts = <0 104 4>,
  76                                              <0 105 4>,
  77                                              <0 106 4>,
  78                                              <0 107 4>,
  79                                              <0 108 4>,
  80                                              <0 109 4>,
  81                                              <0 110 4>,
  82                                              <0 111 4>;
  83                                 #dma-cells = <1>;
  84                                 #dma-channels = <8>;
  85                                 #dma-requests = <32>;
  86                                 clocks = <&l4_main_clk>;
  87                                 clock-names = "apb_pclk";
  88                         };
  89                 };
  90
  91                 can0: can@ffc00000 {
  92                         compatible = "bosch,d_can";
  93                         reg = <0xffc00000 0x1000>;
  94                         interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
  95                         clocks = <&can0_clk>;
  96                         status = "disabled";
  97                 };
  98
  99                 can1: can@ffc01000 {
 100                         compatible = "bosch,d_can";
 101                         reg = <0xffc01000 0x1000>;
 102                         interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
 103                         clocks = <&can1_clk>;
 104                         status = "disabled";
 105                 };
 106
 107                 clkmgr@ffd04000 {
 108                                 compatible = "altr,clk-mgr";
 109                                 reg = <0xffd04000 0x1000>;
 110
 111                                 clocks {
 112                                         #address-cells = <1>;
 113                                         #size-cells = <0>;
 114
 115                                         osc1: osc1 {
 116                                                 #clock-cells = <0>;
 117                                                 compatible = "fixed-clock";
 118                                         };
 119
 120                                         osc2: osc2 {
 121                                                 #clock-cells = <0>;
 122                                                 compatible = "fixed-clock";
 123                                         };
 124
 125                                         f2s_periph_ref_clk: f2s_periph_ref_clk {
 126                                                 #clock-cells = <0>;
 127                                                 compatible = "fixed-clock";
 128                                         };
 129
 130                                         f2s_sdram_ref_clk: f2s_sdram_ref_clk {
 131                                                 #clock-cells = <0>;
 132                                                 compatible = "fixed-clock";
 133                                         };
 134
 135                                         main_pll: main_pll {
 136                                                 #address-cells = <1>;
 137                                                 #size-cells = <0>;
 138                                                 #clock-cells = <0>;
 139                                                 compatible = "altr,socfpga-pll-clock";
 140                                                 clocks = <&osc1>;
 141                                                 reg = <0x40>;
 142
 143                                                 mpuclk: mpuclk {
 144                                                         #clock-cells = <0>;
 145                                                         compatible = "altr,socfpga-perip-clk";
 146                                                         clocks = <&main_pll>;
 147                                                         div-reg = <0xe0 0 9>;
 148                                                         reg = <0x48>;
 149                                                 };
 150
 151                                                 mainclk: mainclk {
 152                                                         #clock-cells = <0>;
 153                                                         compatible = "altr,socfpga-perip-clk";
 154                                                         clocks = <&main_pll>;
 155                                                         div-reg = <0xe4 0 9>;
 156                                                         reg = <0x4C>;
 157                                                 };
 158
 159                                                 dbg_base_clk: dbg_base_clk {
 160                                                         #clock-cells = <0>;
 161                                                         compatible = "altr,socfpga-perip-clk";
 162                                                         clocks = <&main_pll>;
 163                                                         div-reg = <0xe8 0 9>;
 164                                                         reg = <0x50>;
 165                                                 };
 166
 167                                                 main_qspi_clk: main_qspi_clk {
 168                                                         #clock-cells = <0>;
 169                                                         compatible = "altr,socfpga-perip-clk";
 170                                                         clocks = <&main_pll>;
 171                                                         reg = <0x54>;
 172                                                 };
 173
 174                                                 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
 175                                                         #clock-cells = <0>;
 176                                                         compatible = "altr,socfpga-perip-clk";
 177                                                         clocks = <&main_pll>;
 178                                                         reg = <0x58>;
 179                                                 };
 180
 181                                                 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
 182                                                         #clock-cells = <0>;
 183                                                         compatible = "altr,socfpga-perip-clk";
 184                                                         clocks = <&main_pll>;
 185                                                         reg = <0x5C>;
 186                                                 };
 187                                         };
 188
 189                                         periph_pll: periph_pll {
 190                                                 #address-cells = <1>;
 191                                                 #size-cells = <0>;
 192                                                 #clock-cells = <0>;
 193                                                 compatible = "altr,socfpga-pll-clock";
 194                                                 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
 195                                                 reg = <0x80>;
 196
 197                                                 emac0_clk: emac0_clk {
 198                                                         #clock-cells = <0>;
 199                                                         compatible = "altr,socfpga-perip-clk";
 200                                                         clocks = <&periph_pll>;
 201                                                         reg = <0x88>;
 202                                                 };
 203
 204                                                 emac1_clk: emac1_clk {
 205                                                         #clock-cells = <0>;
 206                                                         compatible = "altr,socfpga-perip-clk";
 207                                                         clocks = <&periph_pll>;
 208                                                         reg = <0x8C>;
 209                                                 };
 210
 211                                                 per_qspi_clk: per_qsi_clk {
 212                                                         #clock-cells = <0>;
 213                                                         compatible = "altr,socfpga-perip-clk";
 214                                                         clocks = <&periph_pll>;
 215                                                         reg = <0x90>;
 216                                                 };
 217
 218                                                 per_nand_mmc_clk: per_nand_mmc_clk {
 219                                                         #clock-cells = <0>;
 220                                                         compatible = "altr,socfpga-perip-clk";
 221                                                         clocks = <&periph_pll>;
 222                                                         reg = <0x94>;
 223                                                 };
 224
 225                                                 per_base_clk: per_base_clk {
 226                                                         #clock-cells = <0>;
 227                                                         compatible = "altr,socfpga-perip-clk";
 228                                                         clocks = <&periph_pll>;
 229                                                         reg = <0x98>;
 230                                                 };
 231
 232                                                 h2f_usr1_clk: h2f_usr1_clk {
 233                                                         #clock-cells = <0>;
 234                                                         compatible = "altr,socfpga-perip-clk";
 235                                                         clocks = <&periph_pll>;
 236                                                         reg = <0x9C>;
 237                                                 };
 238                                         };
 239
 240                                         sdram_pll: sdram_pll {
 241                                                 #address-cells = <1>;
 242                                                 #size-cells = <0>;
 243                                                 #clock-cells = <0>;
 244                                                 compatible = "altr,socfpga-pll-clock";
 245                                                 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
 246                                                 reg = <0xC0>;
 247
 248                                                 ddr_dqs_clk: ddr_dqs_clk {
 249                                                         #clock-cells = <0>;
 250                                                         compatible = "altr,socfpga-perip-clk";
 251                                                         clocks = <&sdram_pll>;
 252                                                         reg = <0xC8>;
 253                                                 };
 254
 255                                                 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
 256                                                         #clock-cells = <0>;
 257                                                         compatible = "altr,socfpga-perip-clk";
 258                                                         clocks = <&sdram_pll>;
 259                                                         reg = <0xCC>;
 260                                                 };
 261
 262                                                 ddr_dq_clk: ddr_dq_clk {
 263                                                         #clock-cells = <0>;
 264                                                         compatible = "altr,socfpga-perip-clk";
 265                                                         clocks = <&sdram_pll>;
 266                                                         reg = <0xD0>;
 267                                                 };
 268
 269                                                 h2f_usr2_clk: h2f_usr2_clk {
 270                                                         #clock-cells = <0>;
 271                                                         compatible = "altr,socfpga-perip-clk";
 272                                                         clocks = <&sdram_pll>;
 273                                                         reg = <0xD4>;
 274                                                 };
 275                                         };
 276
 277                                         mpu_periph_clk: mpu_periph_clk {
 278                                                 #clock-cells = <0>;
 279                                                 compatible = "altr,socfpga-perip-clk";
 280                                                 clocks = <&mpuclk>;
 281                                                 fixed-divider = <4>;
 282                                         };
 283
 284                                         mpu_l2_ram_clk: mpu_l2_ram_clk {
 285                                                 #clock-cells = <0>;
 286                                                 compatible = "altr,socfpga-perip-clk";
 287                                                 clocks = <&mpuclk>;
 288                                                 fixed-divider = <2>;
 289                                         };
 290
 291                                         l4_main_clk: l4_main_clk {
 292                                                 #clock-cells = <0>;
 293                                                 compatible = "altr,socfpga-gate-clk";
 294                                                 clocks = <&mainclk>;
 295                                                 clk-gate = <0x60 0>;
 296                                         };
 297
 298                                         l3_main_clk: l3_main_clk {
 299                                                 #clock-cells = <0>;
 300                                                 compatible = "altr,socfpga-perip-clk";
 301                                                 clocks = <&mainclk>;
 302                                                 fixed-divider = <1>;
 303                                         };
 304
 305                                         l3_mp_clk: l3_mp_clk {
 306                                                 #clock-cells = <0>;
 307                                                 compatible = "altr,socfpga-gate-clk";
 308                                                 clocks = <&mainclk>;
 309                                                 div-reg = <0x64 0 2>;
 310                                                 clk-gate = <0x60 1>;
 311                                         };
 312
 313                                         l3_sp_clk: l3_sp_clk {
 314                                                 #clock-cells = <0>;
 315                                                 compatible = "altr,socfpga-gate-clk";
 316                                                 clocks = <&mainclk>;
 317                                                 div-reg = <0x64 2 2>;
 318                                         };
 319
 320                                         l4_mp_clk: l4_mp_clk {
 321                                                 #clock-cells = <0>;
 322                                                 compatible = "altr,socfpga-gate-clk";
 323                                                 clocks = <&mainclk>, <&per_base_clk>;
 324                                                 div-reg = <0x64 4 3>;
 325                                                 clk-gate = <0x60 2>;
 326                                         };
 327
 328                                         l4_sp_clk: l4_sp_clk {
 329                                                 #clock-cells = <0>;
 330                                                 compatible = "altr,socfpga-gate-clk";
 331                                                 clocks = <&mainclk>, <&per_base_clk>;
 332                                                 div-reg = <0x64 7 3>;
 333                                                 clk-gate = <0x60 3>;
 334                                         };
 335
 336                                         dbg_at_clk: dbg_at_clk {
 337                                                 #clock-cells = <0>;
 338                                                 compatible = "altr,socfpga-gate-clk";
 339                                                 clocks = <&dbg_base_clk>;
 340                                                 div-reg = <0x68 0 2>;
 341                                                 clk-gate = <0x60 4>;
 342                                         };
 343
 344                                         dbg_clk: dbg_clk {
 345                                                 #clock-cells = <0>;
 346                                                 compatible = "altr,socfpga-gate-clk";
 347                                                 clocks = <&dbg_base_clk>;
 348                                                 div-reg = <0x68 2 2>;
 349                                                 clk-gate = <0x60 5>;
 350                                         };
 351
 352                                         dbg_trace_clk: dbg_trace_clk {
 353                                                 #clock-cells = <0>;
 354                                                 compatible = "altr,socfpga-gate-clk";
 355                                                 clocks = <&dbg_base_clk>;
 356                                                 div-reg = <0x6C 0 3>;
 357                                                 clk-gate = <0x60 6>;
 358                                         };
 359
 360                                         dbg_timer_clk: dbg_timer_clk {
 361                                                 #clock-cells = <0>;
 362                                                 compatible = "altr,socfpga-gate-clk";
 363                                                 clocks = <&dbg_base_clk>;
 364                                                 clk-gate = <0x60 7>;
 365                                         };
 366
 367                                         cfg_clk: cfg_clk {
 368                                                 #clock-cells = <0>;
 369                                                 compatible = "altr,socfpga-gate-clk";
 370                                                 clocks = <&cfg_h2f_usr0_clk>;
 371                                                 clk-gate = <0x60 8>;
 372                                         };
 373
 374                                         h2f_user0_clk: h2f_user0_clk {
 375                                                 #clock-cells = <0>;
 376                                                 compatible = "altr,socfpga-gate-clk";
 377                                                 clocks = <&cfg_h2f_usr0_clk>;
 378                                                 clk-gate = <0x60 9>;
 379                                         };
 380
 381                                         emac_0_clk: emac_0_clk {
 382                                                 #clock-cells = <0>;
 383                                                 compatible = "altr,socfpga-gate-clk";
 384                                                 clocks = <&emac0_clk>;
 385                                                 clk-gate = <0xa0 0>;
 386                                         };
 387
 388                                         emac_1_clk: emac_1_clk {
 389                                                 #clock-cells = <0>;
 390                                                 compatible = "altr,socfpga-gate-clk";
 391                                                 clocks = <&emac1_clk>;
 392                                                 clk-gate = <0xa0 1>;
 393                                         };
 394
 395                                         usb_mp_clk: usb_mp_clk {
 396                                                 #clock-cells = <0>;
 397                                                 compatible = "altr,socfpga-gate-clk";
 398                                                 clocks = <&per_base_clk>;
 399                                                 clk-gate = <0xa0 2>;
 400                                                 div-reg = <0xa4 0 3>;
 401                                         };
 402
 403                                         spi_m_clk: spi_m_clk {
 404                                                 #clock-cells = <0>;
 405                                                 compatible = "altr,socfpga-gate-clk";
 406                                                 clocks = <&per_base_clk>;
 407                                                 clk-gate = <0xa0 3>;
 408                                                 div-reg = <0xa4 3 3>;
 409                                         };
 410
 411                                         can0_clk: can0_clk {
 412                                                 #clock-cells = <0>;
 413                                                 compatible = "altr,socfpga-gate-clk";
 414                                                 clocks = <&per_base_clk>;
 415                                                 clk-gate = <0xa0 4>;
 416                                                 div-reg = <0xa4 6 3>;
 417                                         };
 418
 419                                         can1_clk: can1_clk {
 420                                                 #clock-cells = <0>;
 421                                                 compatible = "altr,socfpga-gate-clk";
 422                                                 clocks = <&per_base_clk>;
 423                                                 clk-gate = <0xa0 5>;
 424                                                 div-reg = <0xa4 9 3>;
 425                                         };
 426
 427                                         gpio_db_clk: gpio_db_clk {
 428                                                 #clock-cells = <0>;
 429                                                 compatible = "altr,socfpga-gate-clk";
 430                                                 clocks = <&per_base_clk>;
 431                                                 clk-gate = <0xa0 6>;
 432                                                 div-reg = <0xa8 0 24>;
 433                                         };
 434
 435                                         h2f_user1_clk: h2f_user1_clk {
 436                                                 #clock-cells = <0>;
 437                                                 compatible = "altr,socfpga-gate-clk";
 438                                                 clocks = <&h2f_usr1_clk>;
 439                                                 clk-gate = <0xa0 7>;
 440                                         };
 441
 442                                         sdmmc_clk: sdmmc_clk {
 443                                                 #clock-cells = <0>;
 444                                                 compatible = "altr,socfpga-gate-clk";
 445                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 446                                                 clk-gate = <0xa0 8>;
 447                                                 clk-phase = <0 135>;
 448                                         };
 449
 450                                         nand_x_clk: nand_x_clk {
 451                                                 #clock-cells = <0>;
 452                                                 compatible = "altr,socfpga-gate-clk";
 453                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 454                                                 clk-gate = <0xa0 9>;
 455                                         };
 456
 457                                         nand_clk: nand_clk {
 458                                                 #clock-cells = <0>;
 459                                                 compatible = "altr,socfpga-gate-clk";
 460                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 461                                                 clk-gate = <0xa0 10>;
 462                                                 fixed-divider = <4>;
 463                                         };
 464
 465                                         qspi_clk: qspi_clk {
 466                                                 #clock-cells = <0>;
 467                                                 compatible = "altr,socfpga-gate-clk";
 468                                                 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
 469                                                 clk-gate = <0xa0 11>;
 470                                         };
 471                                 };
 472                         };
 473
 474                 gmac0: ethernet@ff700000 {
 475                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 476                         altr,sysmgr-syscon = <&sysmgr 0x60 0>;
 477                         reg = <0xff700000 0x2000>;
 478                         interrupts = <0 115 4>;
 479                         interrupt-names = "macirq";
 480                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
 481                         clocks = <&emac0_clk>;
 482                         clock-names = "stmmaceth";
 483                         resets = <&rst EMAC0_RESET>;
 484                         reset-names = "stmmaceth";
 485                         snps,multicast-filter-bins = <256>;
 486                         snps,perfect-filter-entries = <128>;
 487                         status = "disabled";
 488                 };
 489
 490                 gmac1: ethernet@ff702000 {
 491                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 492                         altr,sysmgr-syscon = <&sysmgr 0x60 2>;
 493                         reg = <0xff702000 0x2000>;
 494                         interrupts = <0 120 4>;
 495                         interrupt-names = "macirq";
 496                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
 497                         clocks = <&emac1_clk>;
 498                         clock-names = "stmmaceth";
 499                         resets = <&rst EMAC1_RESET>;
 500                         reset-names = "stmmaceth";
 501                         snps,multicast-filter-bins = <256>;
 502                         snps,perfect-filter-entries = <128>;
 503                         status = "disabled";
 504                 };
 505
 506                 i2c0: i2c@ffc04000 {
 507                         #address-cells = <1>;
 508                         #size-cells = <0>;
 509                         compatible = "snps,designware-i2c";
 510                         reg = <0xffc04000 0x1000>;
 511                         clocks = <&l4_sp_clk>;
 512                         interrupts = <0 158 0x4>;
 513                         status = "disabled";
 514                 };
 515
 516                 i2c1: i2c@ffc05000 {
 517                         #address-cells = <1>;
 518                         #size-cells = <0>;
 519                         compatible = "snps,designware-i2c";
 520                         reg = <0xffc05000 0x1000>;
 521                         clocks = <&l4_sp_clk>;
 522                         interrupts = <0 159 0x4>;
 523                         status = "disabled";
 524                 };
 525
 526                 i2c2: i2c@ffc06000 {
 527                         #address-cells = <1>;
 528                         #size-cells = <0>;
 529                         compatible = "snps,designware-i2c";
 530                         reg = <0xffc06000 0x1000>;
 531                         clocks = <&l4_sp_clk>;
 532                         interrupts = <0 160 0x4>;
 533                         status = "disabled";
 534                 };
 535
 536                 i2c3: i2c@ffc07000 {
 537                         #address-cells = <1>;
 538                         #size-cells = <0>;
 539                         compatible = "snps,designware-i2c";
 540                         reg = <0xffc07000 0x1000>;
 541                         clocks = <&l4_sp_clk>;
 542                         interrupts = <0 161 0x4>;
 543                         status = "disabled";
 544                 };
 545
 546                 gpio0: gpio@ff708000 {
 547                         #address-cells = <1>;
 548                         #size-cells = <0>;
 549                         compatible = "snps,dw-apb-gpio";
 550                         reg = <0xff708000 0x1000>;
 551                         clocks = <&per_base_clk>;
 552                         status = "disabled";
 553
 554                         porta: gpio-controller@0 {
 555                                 compatible = "snps,dw-apb-gpio-port";
 556                                 bank-name = "porta";
 557                                 gpio-controller;
 558                                 #gpio-cells = <2>;
 559                                 snps,nr-gpios = <29>;
 560                                 reg = <0>;
 561                                 interrupt-controller;
 562                                 #interrupt-cells = <2>;
 563                                 interrupts = <0 164 4>;
 564                         };
 565                 };
 566
 567                 gpio1: gpio@ff709000 {
 568                         #address-cells = <1>;
 569                         #size-cells = <0>;
 570                         compatible = "snps,dw-apb-gpio";
 571                         reg = <0xff709000 0x1000>;
 572                         clocks = <&per_base_clk>;
 573                         status = "disabled";
 574
 575                         portb: gpio-controller@0 {
 576                                 compatible = "snps,dw-apb-gpio-port";
 577                                 bank-name = "portb";
 578                                 gpio-controller;
 579                                 #gpio-cells = <2>;
 580                                 snps,nr-gpios = <29>;
 581                                 reg = <0>;
 582                                 interrupt-controller;
 583                                 #interrupt-cells = <2>;
 584                                 interrupts = <0 165 4>;
 585                         };
 586                 };
 587
 588                 gpio2: gpio@ff70a000 {
 589                         #address-cells = <1>;
 590                         #size-cells = <0>;
 591                         compatible = "snps,dw-apb-gpio";
 592                         reg = <0xff70a000 0x1000>;
 593                         clocks = <&per_base_clk>;
 594                         status = "disabled";
 595
 596                         portc: gpio-controller@0 {
 597                                 compatible = "snps,dw-apb-gpio-port";
 598                                 bank-name = "portc";
 599                                 gpio-controller;
 600                                 #gpio-cells = <2>;
 601                                 snps,nr-gpios = <27>;
 602                                 reg = <0>;
 603                                 interrupt-controller;
 604                                 #interrupt-cells = <2>;
 605                                 interrupts = <0 166 4>;
 606                         };
 607                 };
 608
 609                 sdr: sdr@ffc25000 {
 610                         compatible = "syscon";
 611                         reg = <0xffc25000 0x1000>;
 612                 };
 613
 614                 sdramedac {
 615                         compatible = "altr,sdram-edac";
 616                         altr,sdr-syscon = <&sdr>;
 617                         interrupts = <0 39 4>;
 618                 };
 619
 620                 L2: l2-cache@fffef000 {
 621                         compatible = "arm,pl310-cache";
 622                         reg = <0xfffef000 0x1000>;
 623                         interrupts = <0 38 0x04>;
 624                         cache-unified;
 625                         cache-level = <2>;
 626                         arm,tag-latency = <1 1 1>;
 627                         arm,data-latency = <2 1 1>;
 628                 };
 629
 630                 mmc0: dwmmc0@ff704000 {
 631                         compatible = "altr,socfpga-dw-mshc";
 632                         reg = <0xff704000 0x1000>;
 633                         interrupts = <0 139 4>;
 634                         fifo-depth = <0x400>;
 635                         #address-cells = <1>;
 636                         #size-cells = <0>;
 637                         clocks = <&l4_mp_clk>, <&sdmmc_clk>;
 638                         clock-names = "biu", "ciu";
 639                 };
 640
 641                 qspi: spi@ff705000 {
 642                         compatible = "cadence,qspi";
 643                         #address-cells = <1>;
 644                         #size-cells = <0>;
 645                         reg = <0xff705000 0x1000>,
 646                                 <0xffa00000 0x1000>;
 647                         interrupts = <0 151 4>;
 648                         clocks = <&qspi_clk>;
 649                         ext-decoder = <0>;  /* external decoder */
 650                         num-cs = <4>;
 651                         cdns,fifo-depth = <128>;
 652                         cdns,fifo-width = <4>;
 653                         cdns,trigger-address = <0x00000000>;
 654                         bus-num = <2>;
 655                         status = "disabled";
 656                 };
 657
 658                 spi0: spi@fff00000 {
 659                         compatible = "snps,dw-apb-ssi";
 660                         #address-cells = <1>;
 661                         #size-cells = <0>;
 662                         reg = <0xfff00000 0x1000>;
 663                         interrupts = <0 154 4>;
 664                         num-cs = <4>;
 665                         bus-num = <0>;
 666                         tx-dma-channel = <&pdma 16>;
 667                         rx-dma-channel = <&pdma 17>;
 668                         clocks = <&per_base_clk>;
 669                         status = "disabled";
 670                 };
 671
 672                 spi1: spi@fff01000 {
 673                         compatible = "snps,dw-apb-ssi";
 674                         #address-cells = <1>;
 675                         #size-cells = <0>;
 676                         reg = <0xfff01000 0x1000>;
 677                         interrupts = <0 156 4>;
 678                         num-cs = <4>;
 679                         bus-num = <1>;
 680                         tx-dma-channel = <&pdma 20>;
 681                         rx-dma-channel = <&pdma 21>;
 682                         clocks = <&per_base_clk>;
 683                         status = "disabled";
 684                 };
 685
 686                 /* Local timer */
 687                 timer@fffec600 {
 688                         compatible = "arm,cortex-a9-twd-timer";
 689                         reg = <0xfffec600 0x100>;
 690                         interrupts = <1 13 0xf04>;
 691                         clocks = <&mpu_periph_clk>;
 692                 };
 693
 694                 timer0: timer0@ffc08000 {
 695                         compatible = "snps,dw-apb-timer";
 696                         interrupts = <0 167 4>;
 697                         reg = <0xffc08000 0x1000>;
 698                         clocks = <&l4_sp_clk>;
 699                         clock-names = "timer";
 700                 };
 701
 702                 timer1: timer1@ffc09000 {
 703                         compatible = "snps,dw-apb-timer";
 704                         interrupts = <0 168 4>;
 705                         reg = <0xffc09000 0x1000>;
 706                         clocks = <&l4_sp_clk>;
 707                         clock-names = "timer";
 708                 };
 709
 710                 timer2: timer2@ffd00000 {
 711                         compatible = "snps,dw-apb-timer";
 712                         interrupts = <0 169 4>;
 713                         reg = <0xffd00000 0x1000>;
 714                         clocks = <&osc1>;
 715                         clock-names = "timer";
 716                 };
 717
 718                 timer3: timer3@ffd01000 {
 719                         compatible = "snps,dw-apb-timer";
 720                         interrupts = <0 170 4>;
 721                         reg = <0xffd01000 0x1000>;
 722                         clocks = <&osc1>;
 723                         clock-names = "timer";
 724                 };
 725
 726                 uart0: serial0@ffc02000 {
 727                         compatible = "snps,dw-apb-uart";
 728                         reg = <0xffc02000 0x1000>;
 729                         interrupts = <0 162 4>;
 730                         reg-shift = <2>;
 731                         reg-io-width = <4>;
 732                         clocks = <&l4_sp_clk>;
 733                 };
 734
 735                 uart1: serial1@ffc03000 {
 736                         compatible = "snps,dw-apb-uart";
 737                         reg = <0xffc03000 0x1000>;
 738                         interrupts = <0 163 4>;
 739                         reg-shift = <2>;
 740                         reg-io-width = <4>;
 741                         clocks = <&l4_sp_clk>;
 742                 };
 743
 744                 rst: rstmgr@ffd05000 {
 745                         #reset-cells = <1>;
 746                         compatible = "altr,rst-mgr";
 747                         reg = <0xffd05000 0x1000>;
 748                 };
 749
 750                 usbphy0: usbphy@0 {
 751                         #phy-cells = <0>;
 752                         compatible = "usb-nop-xceiv";
 753                         status = "okay";
 754                 };
 755
 756                 usb0: usb@ffb00000 {
 757                         compatible = "snps,dwc2";
 758                         reg = <0xffb00000 0xffff>;
 759                         interrupts = <0 125 4>;
 760                         clocks = <&usb_mp_clk>;
 761                         clock-names = "otg";
 762                         phys = <&usbphy0>;
 763                         phy-names = "usb2-phy";
 764                         status = "disabled";
 765                 };
 766
 767                 usb1: usb@ffb40000 {
 768                         compatible = "snps,dwc2";
 769                         reg = <0xffb40000 0xffff>;
 770                         interrupts = <0 128 4>;
 771                         clocks = <&usb_mp_clk>;
 772                         clock-names = "otg";
 773                         phys = <&usbphy0>;
 774                         phy-names = "usb2-phy";
 775                         status = "disabled";
 776                 };
 777
 778                 watchdog0: watchdog@ffd02000 {
 779                         compatible = "snps,dw-wdt";
 780                         reg = <0xffd02000 0x1000>;
 781                         interrupts = <0 171 4>;
 782                         clocks = <&osc1>;
 783                         status = "disabled";
 784                 };
 785
 786                 watchdog1: watchdog@ffd03000 {
 787                         compatible = "snps,dw-wdt";
 788                         reg = <0xffd03000 0x1000>;
 789                         interrupts = <0 172 4>;
 790                         clocks = <&osc1>;
 791                         status = "disabled";
 792                 };
 793
 794                 sysmgr: sysmgr@ffd08000 {
 795                         compatible = "altr,sys-mgr", "syscon";
 796                         reg = <0xffd08000 0x4000>;
 797                 };
 798         };
 799 };