1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Intel Corporation
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "altr,socfpga-stratix10";
20 compatible = "arm,cortex-a53", "arm,armv8";
22 enable-method = "psci";
27 compatible = "arm,cortex-a53", "arm,armv8";
29 enable-method = "psci";
34 compatible = "arm,cortex-a53", "arm,armv8";
36 enable-method = "psci";
41 compatible = "arm,cortex-a53", "arm,armv8";
43 enable-method = "psci";
49 compatible = "arm,armv8-pmuv3";
50 interrupts = <0 120 8>,
54 interrupt-affinity = <&cpu0>,
58 interrupt-parent = <&intc>;
62 compatible = "arm,psci-0.2";
67 compatible = "arm,gic-400", "arm,cortex-a15-gic";
68 #interrupt-cells = <3>;
70 reg = <0x0 0xfffc1000 0x0 0x1000>,
71 <0x0 0xfffc2000 0x0 0x2000>,
72 <0x0 0xfffc4000 0x0 0x2000>,
73 <0x0 0xfffc6000 0x0 0x2000>;
79 compatible = "simple-bus";
81 interrupt-parent = <&intc>;
82 ranges = <0 0 0 0xffffffff>;
86 compatible = "altr,clk-mgr";
87 reg = <0xffd10000 0x1000>;
90 gmac0: ethernet@ff800000 {
91 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
92 reg = <0xff800000 0x2000>;
93 interrupts = <0 90 4>;
94 interrupt-names = "macirq";
95 mac-address = [00 00 00 00 00 00];
96 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
97 reset-names = "stmmaceth";
101 gmac1: ethernet@ff802000 {
102 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
103 reg = <0xff802000 0x2000>;
104 interrupts = <0 91 4>;
105 interrupt-names = "macirq";
106 mac-address = [00 00 00 00 00 00];
107 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
108 reset-names = "stmmaceth";
112 gmac2: ethernet@ff804000 {
113 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
114 reg = <0xff804000 0x2000>;
115 interrupts = <0 92 4>;
116 interrupt-names = "macirq";
117 mac-address = [00 00 00 00 00 00];
118 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
119 reset-names = "stmmaceth";
123 gpio0: gpio@ffc03200 {
124 #address-cells = <1>;
126 compatible = "snps,dw-apb-gpio";
127 reg = <0xffc03200 0x100>;
128 resets = <&rst GPIO0_RESET>;
131 porta: gpio-controller@0 {
132 compatible = "snps,dw-apb-gpio-port";
135 snps,nr-gpios = <24>;
137 interrupt-controller;
138 #interrupt-cells = <2>;
139 interrupts = <0 110 4>;
144 gpio1: gpio@ffc03300 {
145 #address-cells = <1>;
147 compatible = "snps,dw-apb-gpio";
148 reg = <0xffc03300 0x100>;
149 resets = <&rst GPIO1_RESET>;
152 portb: gpio-controller@0 {
153 compatible = "snps,dw-apb-gpio-port";
156 snps,nr-gpios = <24>;
158 interrupt-controller;
159 #interrupt-cells = <2>;
160 interrupts = <0 111 4>;
166 #address-cells = <1>;
168 compatible = "snps,designware-i2c";
169 reg = <0xffc02800 0x100>;
170 interrupts = <0 103 4>;
171 resets = <&rst I2C0_RESET>;
177 #address-cells = <1>;
179 compatible = "snps,designware-i2c";
180 reg = <0xffc02900 0x100>;
181 interrupts = <0 104 4>;
182 resets = <&rst I2C1_RESET>;
188 #address-cells = <1>;
190 compatible = "snps,designware-i2c";
191 reg = <0xffc02a00 0x100>;
192 interrupts = <0 105 4>;
193 resets = <&rst I2C2_RESET>;
199 #address-cells = <1>;
201 compatible = "snps,designware-i2c";
202 reg = <0xffc02b00 0x100>;
203 interrupts = <0 106 4>;
204 resets = <&rst I2C3_RESET>;
210 #address-cells = <1>;
212 compatible = "snps,designware-i2c";
213 reg = <0xffc02c00 0x100>;
214 interrupts = <0 107 4>;
215 resets = <&rst I2C4_RESET>;
220 mmc: dwmmc0@ff808000 {
221 #address-cells = <1>;
223 compatible = "altr,socfpga-dw-mshc";
224 reg = <0xff808000 0x1000>;
225 interrupts = <0 96 4>;
226 fifo-depth = <0x400>;
227 resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
232 ocram: sram@ffe00000 {
233 compatible = "mmio-sram";
234 reg = <0xffe00000 0x100000>;
237 rst: rstmgr@ffd11000 {
239 compatible = "altr,rst-mgr";
240 reg = <0xffd11000 0x1000>;
241 altr,modrst-offset = <0x20>;
246 compatible = "snps,dw-apb-ssi";
247 #address-cells = <1>;
249 reg = <0xffda4000 0x1000>;
250 interrupts = <0 99 4>;
251 resets = <&rst SPIM0_RESET>;
253 num-chipselect = <4>;
259 compatible = "snps,dw-apb-ssi";
260 #address-cells = <1>;
262 reg = <0xffda5000 0x1000>;
263 interrupts = <0 100 4>;
264 resets = <&rst SPIM1_RESET>;
266 num-chipselect = <4>;
271 sysmgr: sysmgr@ffd12000 {
272 compatible = "altr,sys-mgr", "syscon";
273 reg = <0xffd12000 0x1000>;
278 compatible = "arm,armv8-timer";
279 interrupts = <1 13 0xf08>,
285 timer0: timer0@ffc03000 {
286 compatible = "snps,dw-apb-timer";
287 interrupts = <0 113 4>;
288 reg = <0xffc03000 0x100>;
291 timer1: timer1@ffc03100 {
292 compatible = "snps,dw-apb-timer";
293 interrupts = <0 114 4>;
294 reg = <0xffc03100 0x100>;
297 timer2: timer2@ffd00000 {
298 compatible = "snps,dw-apb-timer";
299 interrupts = <0 115 4>;
300 reg = <0xffd00000 0x100>;
303 timer3: timer3@ffd00100 {
304 compatible = "snps,dw-apb-timer";
305 interrupts = <0 116 4>;
306 reg = <0xffd00100 0x100>;
309 uart0: serial0@ffc02000 {
310 compatible = "snps,dw-apb-uart";
311 reg = <0xffc02000 0x100>;
312 interrupts = <0 108 4>;
315 resets = <&rst UART0_RESET>;
316 clock-frequency = <100000000>;
321 uart1: serial1@ffc02100 {
322 compatible = "snps,dw-apb-uart";
323 reg = <0xffc02100 0x100>;
324 interrupts = <0 109 4>;
327 resets = <&rst UART1_RESET>;
333 compatible = "usb-nop-xceiv";
338 compatible = "snps,dwc2";
339 reg = <0xffb00000 0x40000>;
340 interrupts = <0 93 4>;
342 phy-names = "usb2-phy";
343 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
344 reset-names = "dwc2", "dwc2-ecc";
349 compatible = "snps,dwc2";
350 reg = <0xffb40000 0x40000>;
351 interrupts = <0 94 4>;
353 phy-names = "usb2-phy";
354 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
355 reset-names = "dwc2", "dwc2-ecc";
359 watchdog0: watchdog@ffd00200 {
360 compatible = "snps,dw-wdt";
361 reg = <0xffd00200 0x100>;
362 interrupts = <0 117 4>;
363 resets = <&rst WATCHDOG0_RESET>;
368 watchdog1: watchdog@ffd00300 {
369 compatible = "snps,dw-wdt";
370 reg = <0xffd00300 0x100>;
371 interrupts = <0 118 4>;
372 resets = <&rst WATCHDOG1_RESET>;
376 watchdog2: watchdog@ffd00400 {
377 compatible = "snps,dw-wdt";
378 reg = <0xffd00400 0x100>;
379 interrupts = <0 125 4>;
380 resets = <&rst WATCHDOG2_RESET>;
384 watchdog3: watchdog@ffd00500 {
385 compatible = "snps,dw-wdt";
386 reg = <0xffd00500 0x100>;
387 interrupts = <0 126 4>;
388 resets = <&rst WATCHDOG3_RESET>;