git.sur5r.net Git - u-boot/blob - arch/arm/dts/socfpga_stratix10.dtsi

   1 /*
   2  * Copyright (C) 2018 Intel Corporation
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 /dts-v1/;
   8 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10
  11 / {
  12         compatible = "altr,socfpga-stratix10";
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu0: cpu@0 {
  21                         compatible = "arm,cortex-a53", "arm,armv8";
  22                         device_type = "cpu";
  23                         enable-method = "psci";
  24                         reg = <0x0>;
  25                 };
  26
  27                 cpu1: cpu@1 {
  28                         compatible = "arm,cortex-a53", "arm,armv8";
  29                         device_type = "cpu";
  30                         enable-method = "psci";
  31                         reg = <0x1>;
  32                 };
  33
  34                 cpu2: cpu@2 {
  35                         compatible = "arm,cortex-a53", "arm,armv8";
  36                         device_type = "cpu";
  37                         enable-method = "psci";
  38                         reg = <0x2>;
  39                 };
  40
  41                 cpu3: cpu@3 {
  42                         compatible = "arm,cortex-a53", "arm,armv8";
  43                         device_type = "cpu";
  44                         enable-method = "psci";
  45                         reg = <0x3>;
  46                 };
  47         };
  48
  49         pmu {
  50                 compatible = "arm,armv8-pmuv3";
  51                 interrupts = <0 120 8>,
  52                              <0 121 8>,
  53                              <0 122 8>,
  54                              <0 123 8>;
  55                 interrupt-affinity = <&cpu0>,
  56                                      <&cpu1>,
  57                                      <&cpu2>,
  58                                      <&cpu3>;
  59                 interrupt-parent = <&intc>;
  60         };
  61
  62         psci {
  63                 compatible = "arm,psci-0.2";
  64                 method = "smc";
  65         };
  66
  67         intc: intc@fffc1000 {
  68                 compatible = "arm,gic-400", "arm,cortex-a15-gic";
  69                 #interrupt-cells = <3>;
  70                 interrupt-controller;
  71                 reg = <0x0 0xfffc1000 0x0 0x1000>,
  72                       <0x0 0xfffc2000 0x0 0x2000>,
  73                       <0x0 0xfffc4000 0x0 0x2000>,
  74                       <0x0 0xfffc6000 0x0 0x2000>;
  75         };
  76
  77         soc {
  78                 #address-cells = <1>;
  79                 #size-cells = <1>;
  80                 compatible = "simple-bus";
  81                 device_type = "soc";
  82                 interrupt-parent = <&intc>;
  83                 ranges = <0 0 0 0xffffffff>;
  84
  85                 clkmgr@ffd1000 {
  86                         compatible = "altr,clk-mgr";
  87                         reg = <0xffd10000 0x1000>;
  88                 };
  89
  90                 gmac0: ethernet@ff800000 {
  91                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
  92                         reg = <0xff800000 0x2000>;
  93                         interrupts = <0 90 4>;
  94                         interrupt-names = "macirq";
  95                         mac-address = [00 00 00 00 00 00];
  96                         resets = <&rst EMAC0_RESET>;
  97                         reset-names = "stmmaceth";
  98                         status = "disabled";
  99                 };
 100
 101                 gmac1: ethernet@ff802000 {
 102                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
 103                         reg = <0xff802000 0x2000>;
 104                         interrupts = <0 91 4>;
 105                         interrupt-names = "macirq";
 106                         mac-address = [00 00 00 00 00 00];
 107                         resets = <&rst EMAC1_RESET>;
 108                         reset-names = "stmmaceth";
 109                         status = "disabled";
 110                 };
 111
 112                 gmac2: ethernet@ff804000 {
 113                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
 114                         reg = <0xff804000 0x2000>;
 115                         interrupts = <0 92 4>;
 116                         interrupt-names = "macirq";
 117                         mac-address = [00 00 00 00 00 00];
 118                         resets = <&rst EMAC2_RESET>;
 119                         reset-names = "stmmaceth";
 120                         status = "disabled";
 121                 };
 122
 123                 gpio0: gpio@ffc03200 {
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                         compatible = "snps,dw-apb-gpio";
 127                         reg = <0xffc03200 0x100>;
 128                         resets = <&rst GPIO0_RESET>;
 129                         status = "disabled";
 130
 131                         porta: gpio-controller@0 {
 132                                 compatible = "snps,dw-apb-gpio-port";
 133                                 gpio-controller;
 134                                 #gpio-cells = <2>;
 135                                 snps,nr-gpios = <24>;
 136                                 reg = <0>;
 137                                 interrupt-controller;
 138                                 #interrupt-cells = <2>;
 139                                 interrupts = <0 110 4>;
 140                         };
 141                 };
 142
 143                 gpio1: gpio@ffc03300 {
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         compatible = "snps,dw-apb-gpio";
 147                         reg = <0xffc03300 0x100>;
 148                         resets = <&rst GPIO1_RESET>;
 149                         status = "disabled";
 150
 151                         portb: gpio-controller@0 {
 152                                 compatible = "snps,dw-apb-gpio-port";
 153                                 gpio-controller;
 154                                 #gpio-cells = <2>;
 155                                 snps,nr-gpios = <24>;
 156                                 reg = <0>;
 157                                 interrupt-controller;
 158                                 #interrupt-cells = <2>;
 159                                 interrupts = <0 111 4>;
 160                         };
 161                 };
 162
 163                 i2c0: i2c@ffc02800 {
 164                         #address-cells = <1>;
 165                         #size-cells = <0>;
 166                         compatible = "snps,designware-i2c";
 167                         reg = <0xffc02800 0x100>;
 168                         interrupts = <0 103 4>;
 169                         resets = <&rst I2C0_RESET>;
 170                         status = "disabled";
 171                 };
 172
 173                 i2c1: i2c@ffc02900 {
 174                         #address-cells = <1>;
 175                         #size-cells = <0>;
 176                         compatible = "snps,designware-i2c";
 177                         reg = <0xffc02900 0x100>;
 178                         interrupts = <0 104 4>;
 179                         resets = <&rst I2C1_RESET>;
 180                         status = "disabled";
 181                 };
 182
 183                 i2c2: i2c@ffc02a00 {
 184                         #address-cells = <1>;
 185                         #size-cells = <0>;
 186                         compatible = "snps,designware-i2c";
 187                         reg = <0xffc02a00 0x100>;
 188                         interrupts = <0 105 4>;
 189                         resets = <&rst I2C2_RESET>;
 190                         status = "disabled";
 191                 };
 192
 193                 i2c3: i2c@ffc02b00 {
 194                         #address-cells = <1>;
 195                         #size-cells = <0>;
 196                         compatible = "snps,designware-i2c";
 197                         reg = <0xffc02b00 0x100>;
 198                         interrupts = <0 106 4>;
 199                         resets = <&rst I2C3_RESET>;
 200                         status = "disabled";
 201                 };
 202
 203                 i2c4: i2c@ffc02c00 {
 204                         #address-cells = <1>;
 205                         #size-cells = <0>;
 206                         compatible = "snps,designware-i2c";
 207                         reg = <0xffc02c00 0x100>;
 208                         interrupts = <0 107 4>;
 209                         resets = <&rst I2C4_RESET>;
 210                         status = "disabled";
 211                 };
 212
 213                 mmc: dwmmc0@ff808000 {
 214                         #address-cells = <1>;
 215                         #size-cells = <0>;
 216                         compatible = "altr,socfpga-dw-mshc";
 217                         reg = <0xff808000 0x1000>;
 218                         interrupts = <0 96 4>;
 219                         fifo-depth = <0x400>;
 220                         resets = <&rst SDMMC_RESET>;
 221                         reset-names = "reset";
 222                         status = "disabled";
 223                 };
 224
 225                 ocram: sram@ffe00000 {
 226                         compatible = "mmio-sram";
 227                         reg = <0xffe00000 0x100000>;
 228                 };
 229
 230                 rst: rstmgr@ffd11000 {
 231                         #reset-cells = <1>;
 232                         compatible = "altr,rst-mgr";
 233                         reg = <0xffd11000 0x1000>;
 234                         altr,modrst-offset = <0x20>;
 235                 };
 236
 237                 spi0: spi@ffda4000 {
 238                         compatible = "snps,dw-apb-ssi";
 239                         #address-cells = <1>;
 240                         #size-cells = <0>;
 241                         reg = <0xffda4000 0x1000>;
 242                         interrupts = <0 99 4>;
 243                         resets = <&rst SPIM0_RESET>;
 244                         reg-io-width = <4>;
 245                         num-chipselect = <4>;
 246                         bus-num = <0>;
 247                         status = "disabled";
 248                 };
 249
 250                 spi1: spi@ffda5000 {
 251                         compatible = "snps,dw-apb-ssi";
 252                         #address-cells = <1>;
 253                         #size-cells = <0>;
 254                         reg = <0xffda5000 0x1000>;
 255                         interrupts = <0 100 4>;
 256                         resets = <&rst SPIM1_RESET>;
 257                         reg-io-width = <4>;
 258                         num-chipselect = <4>;
 259                         bus-num = <0>;
 260                         status = "disabled";
 261                 };
 262
 263                 sysmgr: sysmgr@ffd12000 {
 264                         compatible = "altr,sys-mgr", "syscon";
 265                         reg = <0xffd12000 0x1000>;
 266                 };
 267
 268                 /* Local timer */
 269                 timer {
 270                         compatible = "arm,armv8-timer";
 271                         interrupts = <1 13 0xf08>,
 272                                      <1 14 0xf08>,
 273                                      <1 11 0xf08>,
 274                                      <1 10 0xf08>;
 275                 };
 276
 277                 timer0: timer0@ffc03000 {
 278                         compatible = "snps,dw-apb-timer";
 279                         interrupts = <0 113 4>;
 280                         reg = <0xffc03000 0x100>;
 281                 };
 282
 283                 timer1: timer1@ffc03100 {
 284                         compatible = "snps,dw-apb-timer";
 285                         interrupts = <0 114 4>;
 286                         reg = <0xffc03100 0x100>;
 287                 };
 288
 289                 timer2: timer2@ffd00000 {
 290                         compatible = "snps,dw-apb-timer";
 291                         interrupts = <0 115 4>;
 292                         reg = <0xffd00000 0x100>;
 293                 };
 294
 295                 timer3: timer3@ffd00100 {
 296                         compatible = "snps,dw-apb-timer";
 297                         interrupts = <0 116 4>;
 298                         reg = <0xffd00100 0x100>;
 299                 };
 300
 301                 uart0: serial0@ffc02000 {
 302                         compatible = "snps,dw-apb-uart";
 303                         reg = <0xffc02000 0x100>;
 304                         interrupts = <0 108 4>;
 305                         reg-shift = <2>;
 306                         reg-io-width = <4>;
 307                         resets = <&rst UART0_RESET>;
 308                         status = "disabled";
 309                 };
 310
 311                 uart1: serial1@ffc02100 {
 312                         compatible = "snps,dw-apb-uart";
 313                         reg = <0xffc02100 0x100>;
 314                         interrupts = <0 109 4>;
 315                         reg-shift = <2>;
 316                         reg-io-width = <4>;
 317                         resets = <&rst UART1_RESET>;
 318                         status = "disabled";
 319                 };
 320
 321                 usbphy0: usbphy@0 {
 322                         #phy-cells = <0>;
 323                         compatible = "usb-nop-xceiv";
 324                         status = "okay";
 325                 };
 326
 327                 usb0: usb@ffb00000 {
 328                         compatible = "snps,dwc2";
 329                         reg = <0xffb00000 0x40000>;
 330                         interrupts = <0 93 4>;
 331                         phys = <&usbphy0>;
 332                         phy-names = "usb2-phy";
 333                         resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
 334                         reset-names = "dwc2", "dwc2-ecc";
 335                         status = "disabled";
 336                 };
 337
 338                 usb1: usb@ffb40000 {
 339                         compatible = "snps,dwc2";
 340                         reg = <0xffb40000 0x40000>;
 341                         interrupts = <0 94 4>;
 342                         phys = <&usbphy0>;
 343                         phy-names = "usb2-phy";
 344                         resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
 345                         reset-names = "dwc2", "dwc2-ecc";
 346                         status = "disabled";
 347                 };
 348
 349                 watchdog0: watchdog@ffd00200 {
 350                         compatible = "snps,dw-wdt";
 351                         reg = <0xffd00200 0x100>;
 352                         interrupts = <0 117 4>;
 353                         resets = <&rst WATCHDOG0_RESET>;
 354                         status = "disabled";
 355                 };
 356
 357                 watchdog1: watchdog@ffd00300 {
 358                         compatible = "snps,dw-wdt";
 359                         reg = <0xffd00300 0x100>;
 360                         interrupts = <0 118 4>;
 361                         resets = <&rst WATCHDOG1_RESET>;
 362                         status = "disabled";
 363                 };
 364
 365                 watchdog2: watchdog@ffd00400 {
 366                         compatible = "snps,dw-wdt";
 367                         reg = <0xffd00400 0x100>;
 368                         interrupts = <0 125 4>;
 369                         resets = <&rst WATCHDOG2_RESET>;
 370                         status = "disabled";
 371                 };
 372
 373                 watchdog3: watchdog@ffd00500 {
 374                         compatible = "snps,dw-wdt";
 375                         reg = <0xffd00500 0x100>;
 376                         interrupts = <0 126 4>;
 377                         resets = <&rst WATCHDOG3_RESET>;
 378                         status = "disabled";
 379                 };
 380         };
 381 };