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1 /*
2  * Copyright (C) 2014 STMicroelectronics Limited.
3  * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * publishhed by the Free Software Foundation.
8  */
9 #include "stih407-pinctrl.dtsi"
10 #include <dt-bindings/mfd/st-lpc.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/reset/stih407-resets.h>
13 #include <dt-bindings/interrupt-controller/irq-st.h>
14 / {
15         #address-cells = <1>;
16         #size-cells = <1>;
17
18         reserved-memory {
19                 #address-cells = <1>;
20                 #size-cells = <1>;
21                 ranges;
22
23                 dmu_reserved: rproc@44000000 {
24                         compatible = "shared-dma-pool";
25                         reg = <0x44000000 0x01000000>;
26                         no-map;
27                 };
28         };
29
30         cpus {
31                 #address-cells = <1>;
32                 #size-cells = <0>;
33                 cpu@0 {
34                         device_type = "cpu";
35                         compatible = "arm,cortex-a9";
36                         reg = <0>;
37
38                         /* u-boot puts hpen in SBC dmem at 0xa4 offset */
39                         cpu-release-addr = <0x94100A4>;
40
41                                          /* kHz     uV   */
42                         operating-points = <1500000 0
43                                             1200000 0
44                                             800000  0
45                                             500000  0>;
46
47                         clocks = <&clk_m_a9>;
48                         clock-names = "cpu";
49                         clock-latency = <100000>;
50                         st,syscfg = <&syscfg_core 0x8e0>;
51                 };
52                 cpu@1 {
53                         device_type = "cpu";
54                         compatible = "arm,cortex-a9";
55                         reg = <1>;
56
57                         /* u-boot puts hpen in SBC dmem at 0xa4 offset */
58                         cpu-release-addr = <0x94100A4>;
59
60                                          /* kHz     uV   */
61                         operating-points = <1500000 0
62                                             1200000 0
63                                             800000  0
64                                             500000  0>;
65                 };
66         };
67
68         intc: interrupt-controller@08761000 {
69                 compatible = "arm,cortex-a9-gic";
70                 #interrupt-cells = <3>;
71                 interrupt-controller;
72                 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
73         };
74
75         scu@08760000 {
76                 compatible = "arm,cortex-a9-scu";
77                 reg = <0x08760000 0x1000>;
78         };
79
80         timer@08760200 {
81                 interrupt-parent = <&intc>;
82                 compatible = "arm,cortex-a9-global-timer";
83                 reg = <0x08760200 0x100>;
84                 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
85                 clocks = <&arm_periph_clk>;
86         };
87
88         l2: cache-controller {
89                 compatible = "arm,pl310-cache";
90                 reg = <0x08762000 0x1000>;
91                 arm,data-latency = <3 3 3>;
92                 arm,tag-latency = <2 2 2>;
93                 cache-unified;
94                 cache-level = <2>;
95         };
96
97         arm-pmu {
98                 interrupt-parent = <&intc>;
99                 compatible = "arm,cortex-a9-pmu";
100                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
101         };
102
103         pwm_regulator: pwm-regulator {
104                 compatible = "pwm-regulator";
105                 pwms = <&pwm1 3 8448>;
106                 regulator-name = "CPU_1V0_AVS";
107                 regulator-min-microvolt = <784000>;
108                 regulator-max-microvolt = <1299000>;
109                 regulator-always-on;
110                 max-duty-cycle = <255>;
111                 status = "okay";
112         };
113
114         soc {
115                 #address-cells = <1>;
116                 #size-cells = <1>;
117                 interrupt-parent = <&intc>;
118                 ranges;
119                 compatible = "simple-bus";
120
121                 restart {
122                         compatible = "st,stih407-restart";
123                         st,syscfg = <&syscfg_sbc_reg>;
124                         status = "okay";
125                 };
126
127                 powerdown: powerdown-controller {
128                         compatible = "st,stih407-powerdown";
129                         #reset-cells = <1>;
130                 };
131
132                 softreset: softreset-controller {
133                         compatible = "st,stih407-softreset";
134                         #reset-cells = <1>;
135                 };
136
137                 picophyreset: picophyreset-controller {
138                         compatible = "st,stih407-picophyreset";
139                         #reset-cells = <1>;
140                 };
141
142                 syscfg_sbc: sbc-syscfg@9620000 {
143                         compatible = "st,stih407-sbc-syscfg", "syscon";
144                         reg = <0x9620000 0x1000>;
145                 };
146
147                 syscfg_front: front-syscfg@9280000 {
148                         compatible = "st,stih407-front-syscfg", "syscon";
149                         reg = <0x9280000 0x1000>;
150                 };
151
152                 syscfg_rear: rear-syscfg@9290000 {
153                         compatible = "st,stih407-rear-syscfg", "syscon";
154                         reg = <0x9290000 0x1000>;
155                 };
156
157                 syscfg_flash: flash-syscfg@92a0000 {
158                         compatible = "st,stih407-flash-syscfg", "syscon";
159                         reg = <0x92a0000 0x1000>;
160                 };
161
162                 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
163                         compatible = "st,stih407-sbc-reg-syscfg", "syscon";
164                         reg = <0x9600000 0x1000>;
165                 };
166
167                 syscfg_core: core-syscfg@92b0000 {
168                         compatible = "st,stih407-core-syscfg", "syscon";
169                         reg = <0x92b0000 0x1000>;
170                 };
171
172                 syscfg_lpm: lpm-syscfg@94b5100 {
173                         compatible = "st,stih407-lpm-syscfg", "syscon";
174                         reg = <0x94b5100 0x1000>;
175                 };
176
177                 irq-syscfg {
178                         compatible    = "st,stih407-irq-syscfg";
179                         st,syscfg     = <&syscfg_core>;
180                         st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
181                                         <ST_IRQ_SYSCFG_PMU_1>;
182                         st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
183                                         <ST_IRQ_SYSCFG_DISABLED>;
184                 };
185
186                 /* Display */
187                 vtg_main: sti-vtg-main@8d02800 {
188                         compatible = "st,vtg";
189                         reg = <0x8d02800 0x200>;
190                         interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
191                 };
192
193                 vtg_aux: sti-vtg-aux@8d00200 {
194                         compatible = "st,vtg";
195                         reg = <0x8d00200 0x100>;
196                         interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
197                 };
198
199                 serial@9830000 {
200                         compatible = "st,asc";
201                         reg = <0x9830000 0x2c>;
202                         interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
203                         pinctrl-names = "default";
204                         pinctrl-0 = <&pinctrl_serial0>;
205                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
206
207                         status = "disabled";
208                 };
209
210                 serial@9831000 {
211                         compatible = "st,asc";
212                         reg = <0x9831000 0x2c>;
213                         interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
214                         pinctrl-names = "default";
215                         pinctrl-0 = <&pinctrl_serial1>;
216                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
217
218                         status = "disabled";
219                 };
220
221                 serial@9832000 {
222                         compatible = "st,asc";
223                         reg = <0x9832000 0x2c>;
224                         interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
225                         pinctrl-names = "default";
226                         pinctrl-0 = <&pinctrl_serial2>;
227                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
228
229                         status = "disabled";
230                 };
231
232                 /* SBC_ASC0 - UART10 */
233                 sbc_serial0: serial@9530000 {
234                         compatible = "st,asc";
235                         reg = <0x9530000 0x2c>;
236                         interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
237                         pinctrl-names = "default";
238                         pinctrl-0 = <&pinctrl_sbc_serial0>;
239                         clocks = <&clk_sysin>;
240
241                         status = "disabled";
242                 };
243
244                 serial@9531000 {
245                         compatible = "st,asc";
246                         reg = <0x9531000 0x2c>;
247                         interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
248                         pinctrl-names = "default";
249                         pinctrl-0 = <&pinctrl_sbc_serial1>;
250                         clocks = <&clk_sysin>;
251
252                         status = "disabled";
253                 };
254
255                 i2c@9840000 {
256                         compatible = "st,comms-ssc4-i2c";
257                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
258                         reg = <0x9840000 0x110>;
259                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
260                         clock-names = "ssc";
261                         clock-frequency = <400000>;
262                         pinctrl-names = "default";
263                         pinctrl-0 = <&pinctrl_i2c0_default>;
264                         #address-cells = <1>;
265                         #size-cells = <0>;
266
267                         status = "disabled";
268                 };
269
270                 i2c@9841000 {
271                         compatible = "st,comms-ssc4-i2c";
272                         reg = <0x9841000 0x110>;
273                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
274                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
275                         clock-names = "ssc";
276                         clock-frequency = <400000>;
277                         pinctrl-names = "default";
278                         pinctrl-0 = <&pinctrl_i2c1_default>;
279                         #address-cells = <1>;
280                         #size-cells = <0>;
281
282                         status = "disabled";
283                 };
284
285                 i2c@9842000 {
286                         compatible = "st,comms-ssc4-i2c";
287                         reg = <0x9842000 0x110>;
288                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
289                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
290                         clock-names = "ssc";
291                         clock-frequency = <400000>;
292                         pinctrl-names = "default";
293                         pinctrl-0 = <&pinctrl_i2c2_default>;
294                         #address-cells = <1>;
295                         #size-cells = <0>;
296
297                         status = "disabled";
298                 };
299
300                 i2c@9843000 {
301                         compatible = "st,comms-ssc4-i2c";
302                         reg = <0x9843000 0x110>;
303                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
304                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
305                         clock-names = "ssc";
306                         clock-frequency = <400000>;
307                         pinctrl-names = "default";
308                         pinctrl-0 = <&pinctrl_i2c3_default>;
309                         #address-cells = <1>;
310                         #size-cells = <0>;
311
312                         status = "disabled";
313                 };
314
315                 i2c@9844000 {
316                         compatible = "st,comms-ssc4-i2c";
317                         reg = <0x9844000 0x110>;
318                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
319                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
320                         clock-names = "ssc";
321                         clock-frequency = <400000>;
322                         pinctrl-names = "default";
323                         pinctrl-0 = <&pinctrl_i2c4_default>;
324                         #address-cells = <1>;
325                         #size-cells = <0>;
326
327                         status = "disabled";
328                 };
329
330                 i2c@9845000 {
331                         compatible = "st,comms-ssc4-i2c";
332                         reg = <0x9845000 0x110>;
333                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
334                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
335                         clock-names = "ssc";
336                         clock-frequency = <400000>;
337                         pinctrl-names = "default";
338                         pinctrl-0 = <&pinctrl_i2c5_default>;
339                         #address-cells = <1>;
340                         #size-cells = <0>;
341
342                         status = "disabled";
343                 };
344
345
346                 /* SSCs on SBC */
347                 i2c@9540000 {
348                         compatible = "st,comms-ssc4-i2c";
349                         reg = <0x9540000 0x110>;
350                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
351                         clocks = <&clk_sysin>;
352                         clock-names = "ssc";
353                         clock-frequency = <400000>;
354                         pinctrl-names = "default";
355                         pinctrl-0 = <&pinctrl_i2c10_default>;
356                         #address-cells = <1>;
357                         #size-cells = <0>;
358
359                         status = "disabled";
360                 };
361
362                 i2c@9541000 {
363                         compatible = "st,comms-ssc4-i2c";
364                         reg = <0x9541000 0x110>;
365                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
366                         clocks = <&clk_sysin>;
367                         clock-names = "ssc";
368                         clock-frequency = <400000>;
369                         pinctrl-names = "default";
370                         pinctrl-0 = <&pinctrl_i2c11_default>;
371                         #address-cells = <1>;
372                         #size-cells = <0>;
373
374                         status = "disabled";
375                 };
376
377                 usb2_picophy0: phy1 {
378                         compatible = "st,stih407-usb2-phy";
379                         #phy-cells = <0>;
380                         st,syscfg = <&syscfg_core 0x100 0xf4>;
381                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
382                                  <&picophyreset STIH407_PICOPHY2_RESET>;
383                         reset-names = "global", "port";
384                 };
385
386                 miphy28lp_phy: miphy28lp@9b22000 {
387                         compatible = "st,miphy28lp-phy";
388                         st,syscfg = <&syscfg_core>;
389                         #address-cells  = <1>;
390                         #size-cells     = <1>;
391                         ranges;
392
393                         phy_port0: port@9b22000 {
394                                 reg = <0x9b22000 0xff>,
395                                       <0x9b09000 0xff>,
396                                       <0x9b04000 0xff>;
397                                 reg-names = "sata-up",
398                                             "pcie-up",
399                                             "pipew";
400
401                                 st,syscfg = <0x114 0x818 0xe0 0xec>;
402                                 #phy-cells = <1>;
403
404                                 reset-names = "miphy-sw-rst";
405                                 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
406                         };
407
408                         phy_port1: port@9b2a000 {
409                                 reg = <0x9b2a000 0xff>,
410                                       <0x9b19000 0xff>,
411                                       <0x9b14000 0xff>;
412                                 reg-names = "sata-up",
413                                             "pcie-up",
414                                             "pipew";
415
416                                 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
417
418                                 #phy-cells = <1>;
419
420                                 reset-names = "miphy-sw-rst";
421                                 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
422                         };
423
424                         phy_port2: port@8f95000 {
425                                 reg = <0x8f95000 0xff>,
426                                       <0x8f90000 0xff>;
427                                 reg-names = "pipew",
428                                             "usb3-up";
429
430                                 st,syscfg = <0x11c 0x820>;
431
432                                 #phy-cells = <1>;
433
434                                 reset-names = "miphy-sw-rst";
435                                 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
436                         };
437                 };
438
439                 spi@9840000 {
440                         compatible = "st,comms-ssc4-spi";
441                         reg = <0x9840000 0x110>;
442                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
443                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
444                         clock-names = "ssc";
445                         pinctrl-0 = <&pinctrl_spi0_default>;
446                         pinctrl-names = "default";
447                         #address-cells = <1>;
448                         #size-cells = <0>;
449
450                         status = "disabled";
451                 };
452
453                 spi@9841000 {
454                         compatible = "st,comms-ssc4-spi";
455                         reg = <0x9841000 0x110>;
456                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
457                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
458                         clock-names = "ssc";
459                         pinctrl-names = "default";
460                         pinctrl-0 = <&pinctrl_spi1_default>;
461
462                         status = "disabled";
463                 };
464
465                 spi@9842000 {
466                         compatible = "st,comms-ssc4-spi";
467                         reg = <0x9842000 0x110>;
468                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
469                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
470                         clock-names = "ssc";
471                         pinctrl-names = "default";
472                         pinctrl-0 = <&pinctrl_spi2_default>;
473
474                         status = "disabled";
475                 };
476
477                 spi@9843000 {
478                         compatible = "st,comms-ssc4-spi";
479                         reg = <0x9843000 0x110>;
480                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
481                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
482                         clock-names = "ssc";
483                         pinctrl-names = "default";
484                         pinctrl-0 = <&pinctrl_spi3_default>;
485
486                         status = "disabled";
487                 };
488
489                 spi@9844000 {
490                         compatible = "st,comms-ssc4-spi";
491                         reg = <0x9844000 0x110>;
492                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
493                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
494                         clock-names = "ssc";
495                         pinctrl-names = "default";
496                         pinctrl-0 = <&pinctrl_spi4_default>;
497
498                         status = "disabled";
499                 };
500
501                 /* SBC SSC */
502                 spi@9540000 {
503                         compatible = "st,comms-ssc4-spi";
504                         reg = <0x9540000 0x110>;
505                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
506                         clocks = <&clk_sysin>;
507                         clock-names = "ssc";
508                         pinctrl-names = "default";
509                         pinctrl-0 = <&pinctrl_spi10_default>;
510
511                         status = "disabled";
512                 };
513
514                 spi@9541000 {
515                         compatible = "st,comms-ssc4-spi";
516                         reg = <0x9541000 0x110>;
517                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
518                         clocks = <&clk_sysin>;
519                         clock-names = "ssc";
520                         pinctrl-names = "default";
521                         pinctrl-0 = <&pinctrl_spi11_default>;
522
523                         status = "disabled";
524                 };
525
526                 spi@9542000 {
527                         compatible = "st,comms-ssc4-spi";
528                         reg = <0x9542000 0x110>;
529                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
530                         clocks = <&clk_sysin>;
531                         clock-names = "ssc";
532                         pinctrl-names = "default";
533                         pinctrl-0 = <&pinctrl_spi12_default>;
534
535                         status = "disabled";
536                 };
537
538                 mmc0: sdhci@09060000 {
539                         compatible = "st,sdhci-stih407", "st,sdhci";
540                         status = "disabled";
541                         reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
542                         reg-names = "mmc", "top-mmc-delay";
543                         interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
544                         interrupt-names = "mmcirq";
545                         pinctrl-names = "default";
546                         pinctrl-0 = <&pinctrl_mmc0>;
547                         clock-names = "mmc", "icn";
548                         clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
549                                  <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
550                         bus-width = <8>;
551                 };
552
553                 mmc1: sdhci@09080000 {
554                         compatible = "st,sdhci-stih407", "st,sdhci";
555                         status = "disabled";
556                         reg = <0x09080000 0x7ff>;
557                         reg-names = "mmc";
558                         interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
559                         interrupt-names = "mmcirq";
560                         pinctrl-names = "default";
561                         pinctrl-0 = <&pinctrl_sd1>;
562                         clock-names = "mmc", "icn";
563                         clocks = <&clk_s_c0_flexgen CLK_MMC_1>,
564                                  <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
565                         resets = <&softreset STIH407_MMC1_SOFTRESET>;
566                         bus-width = <4>;
567                 };
568
569                 /* Watchdog and Real-Time Clock */
570                 lpc@8787000 {
571                         compatible = "st,stih407-lpc";
572                         reg = <0x8787000 0x1000>;
573                         interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
574                         clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
575                         timeout-sec = <120>;
576                         st,syscfg = <&syscfg_core>;
577                         st,lpc-mode = <ST_LPC_MODE_WDT>;
578                 };
579
580                 lpc@8788000 {
581                         compatible = "st,stih407-lpc";
582                         reg = <0x8788000 0x1000>;
583                         interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
584                         clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
585                         st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
586                 };
587
588                 sata0: sata@9b20000 {
589                         compatible = "st,ahci";
590                         reg = <0x9b20000 0x1000>;
591
592                         interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
593                         interrupt-names = "hostc";
594
595                         phys = <&phy_port0 PHY_TYPE_SATA>;
596                         phy-names = "ahci_phy";
597
598                         resets = <&powerdown STIH407_SATA0_POWERDOWN>,
599                                  <&softreset STIH407_SATA0_SOFTRESET>,
600                                  <&softreset STIH407_SATA0_PWR_SOFTRESET>;
601                         reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
602
603                         clock-names = "ahci_clk";
604                         clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
605
606                         ports-implemented = <0x1>;
607
608                         status = "disabled";
609                 };
610
611                 sata1: sata@9b28000 {
612                         compatible = "st,ahci";
613                         reg = <0x9b28000 0x1000>;
614
615                         interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
616                         interrupt-names = "hostc";
617
618                         phys = <&phy_port1 PHY_TYPE_SATA>;
619                         phy-names = "ahci_phy";
620
621                         resets = <&powerdown STIH407_SATA1_POWERDOWN>,
622                                  <&softreset STIH407_SATA1_SOFTRESET>,
623                                  <&softreset STIH407_SATA1_PWR_SOFTRESET>;
624                         reset-names = "pwr-dwn",
625                                       "sw-rst",
626                                       "pwr-rst";
627
628                         clock-names = "ahci_clk";
629                         clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
630
631                         ports-implemented = <0x1>;
632
633                         status = "disabled";
634                 };
635
636
637                 st_dwc3: dwc3@8f94000 {
638                         compatible      = "st,stih407-dwc3";
639                         reg             = <0x08f94000 0x1000>, <0x110 0x4>;
640                         reg-names       = "reg-glue", "syscfg-reg";
641                         st,syscfg       = <&syscfg_core>;
642                         resets          = <&powerdown STIH407_USB3_POWERDOWN>,
643                                           <&softreset STIH407_MIPHY2_SOFTRESET>;
644                         reset-names     = "powerdown", "softreset";
645                         #address-cells  = <1>;
646                         #size-cells     = <1>;
647                         pinctrl-names   = "default";
648                         pinctrl-0       = <&pinctrl_usb3>;
649                         ranges;
650
651                         status = "disabled";
652
653                         dwc3: dwc3@9900000 {
654                                 compatible      = "snps,dwc3";
655                                 reg             = <0x09900000 0x100000>;
656                                 interrupts      = <GIC_SPI 155 IRQ_TYPE_NONE>;
657                                 dr_mode         = "host";
658                                 phy-names       = "usb2-phy", "usb3-phy";
659                                 phys            = <&usb2_picophy0>,
660                                                   <&phy_port2 PHY_TYPE_USB3>;
661                         };
662                 };
663
664                 /* COMMS PWM Module */
665                 pwm0: pwm@9810000 {
666                         compatible      = "st,sti-pwm";
667                         #pwm-cells      = <2>;
668                         reg             = <0x9810000 0x68>;
669                         interrupts      = <GIC_SPI 128 IRQ_TYPE_NONE>;
670                         pinctrl-names   = "default";
671                         pinctrl-0       = <&pinctrl_pwm0_chan0_default>;
672                         clock-names     = "pwm";
673                         clocks          = <&clk_sysin>;
674                         st,pwm-num-chan = <1>;
675
676                         status          = "disabled";
677                 };
678
679                 /* SBC PWM Module */
680                 pwm1: pwm@9510000 {
681                         compatible      = "st,sti-pwm";
682                         #pwm-cells      = <2>;
683                         reg             = <0x9510000 0x68>;
684                         pinctrl-names   = "default";
685                         pinctrl-0       = <&pinctrl_pwm1_chan0_default
686                                         &pinctrl_pwm1_chan1_default
687                                         &pinctrl_pwm1_chan2_default
688                                         &pinctrl_pwm1_chan3_default>;
689                         clock-names     = "pwm";
690                         clocks          = <&clk_sysin>;
691                         st,pwm-num-chan = <4>;
692
693                         status          = "disabled";
694                 };
695
696                 rng10: rng@08a89000 {
697                         compatible      = "st,rng";
698                         reg             = <0x08a89000 0x1000>;
699                         clocks          = <&clk_sysin>;
700                         status          = "okay";
701                 };
702
703                 rng11: rng@08a8a000 {
704                         compatible      = "st,rng";
705                         reg             = <0x08a8a000 0x1000>;
706                         clocks          = <&clk_sysin>;
707                         status          = "okay";
708                 };
709
710                 ethernet0: dwmac@9630000 {
711                         device_type = "network";
712                         status = "disabled";
713                         compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
714                         reg = <0x9630000 0x8000>, <0x80 0x4>;
715                         reg-names = "stmmaceth", "sti-ethconf";
716
717                         st,syscon = <&syscfg_sbc_reg 0x80>;
718                         st,gmac_en;
719                         resets = <&softreset STIH407_ETH1_SOFTRESET>;
720                         reset-names = "stmmaceth";
721
722                         interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
723                                      <GIC_SPI 99 IRQ_TYPE_NONE>;
724                         interrupt-names = "macirq", "eth_wake_irq";
725
726                         /* DMA Bus Mode */
727                         snps,pbl = <8>;
728
729                         pinctrl-names = "default";
730                         pinctrl-0 = <&pinctrl_rgmii1>;
731
732                         clock-names = "stmmaceth", "sti-ethclk";
733                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
734                                  <&clk_s_c0_flexgen CLK_ETH_PHY>;
735                 };
736
737                 cec: sti-cec@094a087c {
738                         compatible = "st,stih-cec";
739                         reg = <0x94a087c 0x64>;
740                         clocks = <&clk_sysin>;
741                         clock-names = "cec-clk";
742                         interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>;
743                         interrupt-names = "cec-irq";
744                         pinctrl-names = "default";
745                         pinctrl-0 = <&pinctrl_cec0_default>;
746                         resets = <&softreset STIH407_LPM_SOFTRESET>;
747                 };
748
749                 rng10: rng@08a89000 {
750                         compatible      = "st,rng";
751                         reg             = <0x08a89000 0x1000>;
752                         clocks          = <&clk_sysin>;
753                         status          = "okay";
754                 };
755
756                 rng11: rng@08a8a000 {
757                         compatible      = "st,rng";
758                         reg             = <0x08a8a000 0x1000>;
759                         clocks          = <&clk_sysin>;
760                         status          = "okay";
761                 };
762
763                 mailbox0: mailbox@8f00000  {
764                         compatible      = "st,stih407-mailbox";
765                         reg             = <0x8f00000 0x1000>;
766                         interrupts      = <GIC_SPI 1 IRQ_TYPE_NONE>;
767                         #mbox-cells     = <2>;
768                         mbox-name       = "a9";
769                         status          = "okay";
770                 };
771
772                 mailbox1: mailbox@8f01000 {
773                         compatible      = "st,stih407-mailbox";
774                         reg             = <0x8f01000 0x1000>;
775                         #mbox-cells     = <2>;
776                         mbox-name       = "st231_gp_1";
777                         status          = "okay";
778                 };
779
780                 mailbox2: mailbox@8f02000 {
781                         compatible      = "st,stih407-mailbox";
782                         reg             = <0x8f02000 0x1000>;
783                         #mbox-cells     = <2>;
784                         mbox-name       = "st231_gp_0";
785                         status          = "okay";
786                 };
787
788                 mailbox3: mailbox@8f03000 {
789                         compatible      = "st,stih407-mailbox";
790                         reg             = <0x8f03000 0x1000>;
791                         #mbox-cells     = <2>;
792                         mbox-name       = "st231_audio_video";
793                         status          = "okay";
794                 };
795
796                 st231_delta: st231-delta@44000000 {
797                         compatible      = "st,st231-rproc";
798                         memory-region   = <&dmu_reserved>;
799                         resets          = <&softreset STIH407_ST231_DMU_SOFTRESET>;
800                         reset-names     = "sw_reset";
801                         clocks          = <&clk_s_c0_flexgen CLK_ST231_DMU>;
802                         clock-frequency = <600000000>;
803                         st,syscfg       = <&syscfg_core 0x224>;
804                         #mbox-cells = <1>;
805                         mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
806                         mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
807                 };
808
809                 /* fdma audio */
810                 fdma0: dma-controller@8e20000 {
811                         compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
812                         reg = <0x8e20000 0x8000>,
813                               <0x8e30000 0x3000>,
814                               <0x8e37000 0x1000>,
815                               <0x8e38000 0x8000>;
816                         reg-names = "slimcore", "dmem", "peripherals", "imem";
817                         clocks = <&clk_s_c0_flexgen CLK_FDMA>,
818                                  <&clk_s_c0_flexgen CLK_EXT2F_A9>,
819                                  <&clk_s_c0_flexgen CLK_EXT2F_A9>,
820                                  <&clk_s_c0_flexgen CLK_EXT2F_A9>;
821                         interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>;
822                         dma-channels = <16>;
823                         #dma-cells = <3>;
824                 };
825
826                 /* fdma app */
827                 fdma1: dma-controller@8e40000 {
828                         compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc";
829                         reg = <0x8e40000 0x8000>,
830                               <0x8e50000 0x3000>,
831                               <0x8e57000 0x1000>,
832                               <0x8e58000 0x8000>;
833                         reg-names = "slimcore", "dmem", "peripherals", "imem";
834                         clocks = <&clk_s_c0_flexgen CLK_FDMA>,
835                                 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
836                                 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
837                                 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
838
839                         interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>;
840                         dma-channels = <16>;
841                         #dma-cells = <3>;
842                 };
843
844                 /* fdma free running */
845                 fdma2: dma-controller@8e60000 {
846                         compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc";
847                         reg = <0x8e60000 0x8000>,
848                               <0x8e70000 0x3000>,
849                               <0x8e77000 0x1000>,
850                               <0x8e78000 0x8000>;
851                         reg-names = "slimcore", "dmem", "peripherals", "imem";
852                         interrupts = <GIC_SPI 9 IRQ_TYPE_NONE>;
853                         dma-channels = <16>;
854                         #dma-cells = <3>;
855                         clocks = <&clk_s_c0_flexgen CLK_FDMA>,
856                                 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
857                                 <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
858                                 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
859                 };
860
861                 sti_sasg_codec: sti-sasg-codec {
862                         compatible = "st,stih407-sas-codec";
863                         #sound-dai-cells = <1>;
864                         status = "disabled";
865                         st,syscfg = <&syscfg_core>;
866                 };
867
868                 sti_uni_player0: sti-uni-player@8d80000 {
869                         compatible = "st,stih407-uni-player-hdmi";
870                         #sound-dai-cells = <0>;
871                         st,syscfg = <&syscfg_core>;
872                         clocks = <&clk_s_d0_flexgen CLK_PCM_0>;
873                         assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>;
874                         assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>;
875                         assigned-clock-rates = <50000000>;
876                         reg = <0x8d80000 0x158>;
877                         interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>;
878                         dmas = <&fdma0 2 0 1>;
879                         dma-names = "tx";
880
881                         status          = "disabled";
882                 };
883
884                 sti_uni_player1: sti-uni-player@8d81000 {
885                         compatible = "st,stih407-uni-player-pcm-out";
886                         #sound-dai-cells = <0>;
887                         st,syscfg = <&syscfg_core>;
888                         clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
889                         assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>;
890                         assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
891                         assigned-clock-rates = <50000000>;
892                         reg = <0x8d81000 0x158>;
893                         interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
894                         dmas = <&fdma0 3 0 1>;
895                         dma-names = "tx";
896
897                         status = "disabled";
898                 };
899
900                 sti_uni_player2: sti-uni-player@8d82000 {
901                         compatible = "st,stih407-uni-player-dac";
902                         #sound-dai-cells = <0>;
903                         st,syscfg = <&syscfg_core>;
904                         clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
905                         assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>;
906                         assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>;
907                         assigned-clock-rates = <50000000>;
908                         reg = <0x8d82000 0x158>;
909                         interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
910                         dmas = <&fdma0 4 0 1>;
911                         dma-names = "tx";
912
913                         status = "disabled";
914                 };
915
916                 sti_uni_player3: sti-uni-player@8d85000 {
917                         compatible = "st,stih407-uni-player-spdif";
918                         #sound-dai-cells = <0>;
919                         st,syscfg = <&syscfg_core>;
920                         clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
921                         assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>;
922                         assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>;
923                         assigned-clock-rates = <50000000>;
924                         reg = <0x8d85000 0x158>;
925                         interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
926                         dmas = <&fdma0 7 0 1>;
927                         dma-names = "tx";
928
929                         status = "disabled";
930                 };
931
932                 sti_uni_reader0: sti-uni-reader@8d83000 {
933                         compatible = "st,stih407-uni-reader-pcm_in";
934                         #sound-dai-cells = <0>;
935                         st,syscfg = <&syscfg_core>;
936                         reg = <0x8d83000 0x158>;
937                         interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>;
938                         dmas = <&fdma0 5 0 1>;
939                         dma-names = "rx";
940
941                         status = "disabled";
942                 };
943
944                 sti_uni_reader1: sti-uni-reader@8d84000 {
945                         compatible = "st,stih407-uni-reader-hdmi";
946                         #sound-dai-cells = <0>;
947                         st,syscfg = <&syscfg_core>;
948                         reg = <0x8d84000 0x158>;
949                         interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>;
950                         dmas = <&fdma0 6 0 1>;
951                         dma-names = "rx";
952
953                         status = "disabled";
954                 };
955
956                 rc: rc@09518000 {
957                         compatible = "st,comms-irb";
958                         reg = <0x09518000 0x234>;
959                         interrupts = <GIC_SPI 132 IRQ_TYPE_NONE>;
960                         rx-mode = "infrared";
961                         pinctrl-names = "default";
962                         pinctrl-0 = <&pinctrl_ir
963                                      &pinctrl_uhf
964                                      &pinctrl_tx
965                                      &pinctrl_tx_od>;
966                         clocks = <&clk_sysin>;
967                         resets = <&softreset STIH407_IRB_SOFTRESET>;
968
969                         status = "disabled";
970                 };
971
972                 socinfo {
973                         compatible = "st,stih407-socinfo";
974                         st,syscfg = <&syscfg_core>;
975                 };
976         };
977 };