2 * Copyright 2018 - Christophe Priouzeau <christophe.priouzeau@st.com>
5 * stm32f746-disco.dts from U-boot 2018.01
6 * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This file is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
48 #include "stm32f746.dtsi"
49 #include <dt-bindings/memory/stm32-sdram.h>
52 model = "STMicroelectronics STM32F746G-EVAL board";
53 compatible = "st,stm32f746g-eval", "st,stm32f746";
56 bootargs = "root=/dev/mmcblk0p1 rw rootwait";
57 stdout-path = "serial0:115200n8";
61 reg = <0xC0000000 0x2000000>;
68 /* Aliases for gpios so as to use sequence */
83 compatible = "st,led1";
84 led-gpio = <&gpiof 10 0>;
88 compatible = "st,button1";
89 button-gpio = <&gpioc 13 0>;
94 clock-frequency = <25000000>;
98 usart1_pins_a: usart1@0 {
100 pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
106 pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
111 ethernet_mii: mii@0 {
113 pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
114 <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
115 <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
116 <STM32F746_PA2_FUNC_ETH_MDIO>,
117 <STM32F746_PC1_FUNC_ETH_MDC>,
118 <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
119 <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
120 <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
121 <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
128 pinmux = <STM32F746_PI10_FUNC_FMC_D31>, /* FMC_D31 */
129 <STM32F746_PI9_FUNC_FMC_D30>, /* FMC_D30*/
130 <STM32F746_PI7_FUNC_FMC_D29>, /* FMC_D29 */
131 <STM32F746_PI6_FUNC_FMC_D28>, /* FMC_D28 */
132 <STM32F746_PI3_FUNC_FMC_D27>, /* FMC_D27 */
133 <STM32F746_PI2_FUNC_FMC_D26>, /* FMC_D26 */
134 <STM32F746_PI1_FUNC_FMC_D25>, /* FMC_D25 */
135 <STM32F746_PI0_FUNC_FMC_D24>, /* FMC_D24 */
136 <STM32F746_PH15_FUNC_FMC_D23>, /* FMC_D23 */
137 <STM32F746_PH14_FUNC_FMC_D22>, /* FMC_D22 */
138 <STM32F746_PH13_FUNC_FMC_D21>, /* FMC_D21 */
139 <STM32F746_PH12_FUNC_FMC_D20>, /* FMC_D20 */
140 <STM32F746_PH11_FUNC_FMC_D19>, /* FMC_D19 */
141 <STM32F746_PH10_FUNC_FMC_D18>, /* FMC_D18 */
142 <STM32F746_PH9_FUNC_FMC_D17>, /* FMC_D17 */
143 <STM32F746_PH8_FUNC_FMC_D16>, /* FMC_D16 */
145 <STM32F746_PD10_FUNC_FMC_D15>, /* FMC_D15 */
146 <STM32F746_PD9_FUNC_FMC_D14>, /* FMC_D14*/
147 <STM32F746_PD8_FUNC_FMC_D13>, /* FMC_D13 */
148 <STM32F746_PE15_FUNC_FMC_D12>,/* FMC_D12 */
149 <STM32F746_PE14_FUNC_FMC_D11>,/* FMC_D11 */
150 <STM32F746_PE13_FUNC_FMC_D10>,/* FMC_D10 */
151 <STM32F746_PE12_FUNC_FMC_D9>, /* FMC_D9 */
152 <STM32F746_PE11_FUNC_FMC_D8>, /* FMC_D8 */
153 <STM32F746_PE10_FUNC_FMC_D7>, /* FMC_D7 */
154 <STM32F746_PE9_FUNC_FMC_D6>, /* FMC_D6 */
155 <STM32F746_PE8_FUNC_FMC_D5>, /* FMC_D5*/
156 <STM32F746_PE7_FUNC_FMC_D4>, /* FMC_D4 */
157 <STM32F746_PD1_FUNC_FMC_D3>, /* FMC_D3 */
158 <STM32F746_PD0_FUNC_FMC_D2>, /* FMC_D2 */
159 <STM32F746_PD15_FUNC_FMC_D1>, /* FMC_D1 */
160 <STM32F746_PD14_FUNC_FMC_D0>, /* FMC_D0 */
162 <STM32F746_PI5_FUNC_FMC_NBL3>, /* FMC_NBL3 */
163 <STM32F746_PI4_FUNC_FMC_NBL2>, /* FMC_NBL2 */
164 <STM32F746_PE1_FUNC_FMC_NBL1>, /* FMC_NBL1 */
165 <STM32F746_PE0_FUNC_FMC_NBL0>, /* FMC_NBL0 */
167 <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, /* FMC_A15 FMC_BA1 */
168 <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, /* FMC_A14 FMC_BA0*/
170 <STM32F746_PG1_FUNC_FMC_A11>, /* FMC_A11 */
171 <STM32F746_PG0_FUNC_FMC_A10>, /* FMC_A10 */
172 <STM32F746_PF15_FUNC_FMC_A9>, /* FMC_A9 */
173 <STM32F746_PF14_FUNC_FMC_A8>, /* FMC_A8 */
174 <STM32F746_PF13_FUNC_FMC_A7>, /* FMC_A7 */
175 <STM32F746_PF12_FUNC_FMC_A6>, /* FMC_A6 */
176 <STM32F746_PF5_FUNC_FMC_A5>, /* FUNC_FMC_A5 */
177 <STM32F746_PF4_FUNC_FMC_A4>, /* FMC_A4 */
178 <STM32F746_PF3_FUNC_FMC_A3>, /* FMC_A3 */
179 <STM32F746_PF2_FUNC_FMC_A2>, /* FMC_A2 */
180 <STM32F746_PF1_FUNC_FMC_A1>, /* FMC_A1 */
181 <STM32F746_PF0_FUNC_FMC_A0>, /* FMC_A0 */
183 <STM32F746_PH3_FUNC_FMC_SDNE0>,/* FMC_SDNE0 */
184 <STM32F746_PH5_FUNC_FMC_SDNWE>, /* FMC_SDNWE */
185 <STM32F746_PF11_FUNC_FMC_SDNRAS>, /* FMC_SDNRAS */
186 <STM32F746_PG15_FUNC_FMC_SDNCAS>, /* FMC_SDNCAS */
187 <STM32F746_PH2_FUNC_FMC_SDCKE0>, /* FMC_SDCKE0 */
188 <STM32F746_PG8_FUNC_FMC_SDCLK>; /* FMC_SDCLK */
195 pinctrl-0 = <&usart1_pins_a>;
196 pinctrl-names = "default";
202 pinctrl-0 = <ðernet_mii>;
204 phy-handle = <&phy0>;
207 #address-cells = <1>;
209 compatible = "snps,dwmac-mdio";
210 phy0: ethernet-phy@0 {
217 pinctrl-0 = <&fmc_pins>;
218 pinctrl-names = "default";
222 * Memory configuration from sdram datasheet IS42S32800G-6BLI
225 st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
226 CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
227 st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
229 st,sdram-refcount = <1539>;
235 pinctrl-names = "default", "opendrain";
236 pinctrl-0 = <&sdio_pins>;
237 pinctrl-1 = <&sdio_pins_od>;
239 max-frequency = <25000000>;