git.sur5r.net Git - u-boot/blob - arch/arm/dts/stm32f429.dtsi

   1 /*
   2  * Copyright (C) 2015, STMicroelectronics - All Rights Reserved
   3  * Author(s):  Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include "skeleton.dtsi"
  45 #include "armv7-m.dtsi"
  46 #include <dt-bindings/clock/stm32fx-clock.h>
  47 #include <dt-bindings/mfd/stm32f4-rcc.h>
  48
  49 / {
  50         clocks {
  51                 clk_hse: clk-hse {
  52                         #clock-cells = <0>;
  53                         compatible = "fixed-clock";
  54                         clock-frequency = <0>;
  55                 };
  56
  57                 clk_lse: clk-lse {
  58                         #clock-cells = <0>;
  59                         compatible = "fixed-clock";
  60                         clock-frequency = <32768>;
  61                 };
  62
  63                 clk_lsi: clk-lsi {
  64                         #clock-cells = <0>;
  65                         compatible = "fixed-clock";
  66                         clock-frequency = <32000>;
  67                 };
  68
  69                 clk_i2s_ckin: i2s-ckin {
  70                         #clock-cells = <0>;
  71                         compatible = "fixed-clock";
  72                         clock-frequency = <0>;
  73                 };
  74         };
  75
  76         soc {
  77                 timer2: timer@40000000 {
  78                         compatible = "st,stm32-timer";
  79                         reg = <0x40000000 0x400>;
  80                         interrupts = <28>;
  81                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
  82                         status = "disabled";
  83                 };
  84
  85                 timers2: timers@40000000 {
  86                         #address-cells = <1>;
  87                         #size-cells = <0>;
  88                         compatible = "st,stm32-timers";
  89                         reg = <0x40000000 0x400>;
  90                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
  91                         clock-names = "int";
  92                         status = "disabled";
  93
  94                         pwm {
  95                                 compatible = "st,stm32-pwm";
  96                                 status = "disabled";
  97                         };
  98
  99                         timer@1 {
 100                                 compatible = "st,stm32-timer-trigger";
 101                                 reg = <1>;
 102                                 status = "disabled";
 103                         };
 104                 };
 105
 106                 timer3: timer@40000400 {
 107                         compatible = "st,stm32-timer";
 108                         reg = <0x40000400 0x400>;
 109                         interrupts = <29>;
 110                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
 111                         status = "disabled";
 112                 };
 113
 114                 timers3: timers@40000400 {
 115                         #address-cells = <1>;
 116                         #size-cells = <0>;
 117                         compatible = "st,stm32-timers";
 118                         reg = <0x40000400 0x400>;
 119                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
 120                         clock-names = "int";
 121                         status = "disabled";
 122
 123                         pwm {
 124                                 compatible = "st,stm32-pwm";
 125                                 status = "disabled";
 126                         };
 127
 128                         timer@2 {
 129                                 compatible = "st,stm32-timer-trigger";
 130                                 reg = <2>;
 131                                 status = "disabled";
 132                         };
 133                 };
 134
 135                 timer4: timer@40000800 {
 136                         compatible = "st,stm32-timer";
 137                         reg = <0x40000800 0x400>;
 138                         interrupts = <30>;
 139                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 140                         status = "disabled";
 141                 };
 142
 143                 timers4: timers@40000800 {
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         compatible = "st,stm32-timers";
 147                         reg = <0x40000800 0x400>;
 148                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 149                         clock-names = "int";
 150                         status = "disabled";
 151
 152                         pwm {
 153                                 compatible = "st,stm32-pwm";
 154                                 status = "disabled";
 155                         };
 156
 157                         timer@3 {
 158                                 compatible = "st,stm32-timer-trigger";
 159                                 reg = <3>;
 160                                 status = "disabled";
 161                         };
 162                 };
 163
 164                 timer5: timer@40000c00 {
 165                         compatible = "st,stm32-timer";
 166                         reg = <0x40000c00 0x400>;
 167                         interrupts = <50>;
 168                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 169                 };
 170
 171                 timers5: timers@40000c00 {
 172                         #address-cells = <1>;
 173                         #size-cells = <0>;
 174                         compatible = "st,stm32-timers";
 175                         reg = <0x40000C00 0x400>;
 176                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 177                         clock-names = "int";
 178                         status = "disabled";
 179
 180                         pwm {
 181                                 compatible = "st,stm32-pwm";
 182                                 status = "disabled";
 183                         };
 184
 185                         timer@4 {
 186                                 compatible = "st,stm32-timer-trigger";
 187                                 reg = <4>;
 188                                 status = "disabled";
 189                         };
 190                 };
 191
 192                 timer6: timer@40001000 {
 193                         compatible = "st,stm32-timer";
 194                         reg = <0x40001000 0x400>;
 195                         interrupts = <54>;
 196                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 197                         status = "disabled";
 198                 };
 199
 200                 timers6: timers@40001000 {
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203                         compatible = "st,stm32-timers";
 204                         reg = <0x40001000 0x400>;
 205                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 206                         clock-names = "int";
 207                         status = "disabled";
 208
 209                         timer@5 {
 210                                 compatible = "st,stm32-timer-trigger";
 211                                 reg = <5>;
 212                                 status = "disabled";
 213                         };
 214                 };
 215
 216                 timer7: timer@40001400 {
 217                         compatible = "st,stm32-timer";
 218                         reg = <0x40001400 0x400>;
 219                         interrupts = <55>;
 220                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 221                         status = "disabled";
 222                 };
 223
 224                 timers7: timers@40001400 {
 225                         #address-cells = <1>;
 226                         #size-cells = <0>;
 227                         compatible = "st,stm32-timers";
 228                         reg = <0x40001400 0x400>;
 229                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 230                         clock-names = "int";
 231                         status = "disabled";
 232
 233                         timer@6 {
 234                                 compatible = "st,stm32-timer-trigger";
 235                                 reg = <6>;
 236                                 status = "disabled";
 237                         };
 238                 };
 239
 240                 timers12: timers@40001800 {
 241                         #address-cells = <1>;
 242                         #size-cells = <0>;
 243                         compatible = "st,stm32-timers";
 244                         reg = <0x40001800 0x400>;
 245                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
 246                         clock-names = "int";
 247                         status = "disabled";
 248
 249                         pwm {
 250                                 compatible = "st,stm32-pwm";
 251                                 status = "disabled";
 252                         };
 253
 254                         timer@11 {
 255                                 compatible = "st,stm32-timer-trigger";
 256                                 reg = <11>;
 257                                 status = "disabled";
 258                         };
 259                 };
 260
 261                 timers13: timers@40001c00 {
 262                         #address-cells = <1>;
 263                         #size-cells = <0>;
 264                         compatible = "st,stm32-timers";
 265                         reg = <0x40001C00 0x400>;
 266                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
 267                         clock-names = "int";
 268                         status = "disabled";
 269
 270                         pwm {
 271                                 compatible = "st,stm32-pwm";
 272                                 status = "disabled";
 273                         };
 274                 };
 275
 276                 timers14: timers@40002000 {
 277                         #address-cells = <1>;
 278                         #size-cells = <0>;
 279                         compatible = "st,stm32-timers";
 280                         reg = <0x40002000 0x400>;
 281                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
 282                         clock-names = "int";
 283                         status = "disabled";
 284
 285                         pwm {
 286                                 compatible = "st,stm32-pwm";
 287                                 status = "disabled";
 288                         };
 289                 };
 290
 291                 rtc: rtc@40002800 {
 292                         compatible = "st,stm32-rtc";
 293                         reg = <0x40002800 0x400>;
 294                         clocks = <&rcc 1 CLK_RTC>;
 295                         clock-names = "ck_rtc";
 296                         assigned-clocks = <&rcc 1 CLK_RTC>;
 297                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
 298                         interrupt-parent = <&exti>;
 299                         interrupts = <17 1>;
 300                         interrupt-names = "alarm";
 301                         st,syscfg = <&pwrcfg>;
 302                         status = "disabled";
 303                 };
 304
 305                 iwdg: watchdog@40003000 {
 306                         compatible = "st,stm32-iwdg";
 307                         reg = <0x40003000 0x400>;
 308                         clocks = <&clk_lsi>;
 309                         status = "disabled";
 310                 };
 311
 312                 usart2: serial@40004400 {
 313                         compatible = "st,stm32-uart";
 314                         reg = <0x40004400 0x400>;
 315                         interrupts = <38>;
 316                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
 317                         status = "disabled";
 318                 };
 319
 320                 usart3: serial@40004800 {
 321                         compatible = "st,stm32-uart";
 322                         reg = <0x40004800 0x400>;
 323                         interrupts = <39>;
 324                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
 325                         status = "disabled";
 326                         dmas = <&dma1 1 4 0x400 0x0>,
 327                                <&dma1 3 4 0x400 0x0>;
 328                         dma-names = "rx", "tx";
 329                 };
 330
 331                 usart4: serial@40004c00 {
 332                         compatible = "st,stm32-uart";
 333                         reg = <0x40004c00 0x400>;
 334                         interrupts = <52>;
 335                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
 336                         status = "disabled";
 337                 };
 338
 339                 usart5: serial@40005000 {
 340                         compatible = "st,stm32-uart";
 341                         reg = <0x40005000 0x400>;
 342                         interrupts = <53>;
 343                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
 344                         status = "disabled";
 345                 };
 346
 347                 i2c1: i2c@40005400 {
 348                         compatible = "st,stm32f4-i2c";
 349                         reg = <0x40005400 0x400>;
 350                         interrupts = <31>,
 351                                      <32>;
 352                         resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
 353                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
 354                         #address-cells = <1>;
 355                         #size-cells = <0>;
 356                         status = "disabled";
 357                 };
 358
 359                 dac: dac@40007400 {
 360                         compatible = "st,stm32f4-dac-core";
 361                         reg = <0x40007400 0x400>;
 362                         resets = <&rcc STM32F4_APB1_RESET(DAC)>;
 363                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
 364                         clock-names = "pclk";
 365                         #address-cells = <1>;
 366                         #size-cells = <0>;
 367                         status = "disabled";
 368
 369                         dac1: dac@1 {
 370                                 compatible = "st,stm32-dac";
 371                                 #io-channels-cells = <1>;
 372                                 reg = <1>;
 373                                 status = "disabled";
 374                         };
 375
 376                         dac2: dac@2 {
 377                                 compatible = "st,stm32-dac";
 378                                 #io-channels-cells = <1>;
 379                                 reg = <2>;
 380                                 status = "disabled";
 381                         };
 382                 };
 383
 384                 usart7: serial@40007800 {
 385                         compatible = "st,stm32-uart";
 386                         reg = <0x40007800 0x400>;
 387                         interrupts = <82>;
 388                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
 389                         status = "disabled";
 390                 };
 391
 392                 usart8: serial@40007c00 {
 393                         compatible = "st,stm32-uart";
 394                         reg = <0x40007c00 0x400>;
 395                         interrupts = <83>;
 396                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
 397                         status = "disabled";
 398                 };
 399
 400                 timers1: timers@40010000 {
 401                         #address-cells = <1>;
 402                         #size-cells = <0>;
 403                         compatible = "st,stm32-timers";
 404                         reg = <0x40010000 0x400>;
 405                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
 406                         clock-names = "int";
 407                         status = "disabled";
 408
 409                         pwm {
 410                                 compatible = "st,stm32-pwm";
 411                                 status = "disabled";
 412                         };
 413
 414                         timer@0 {
 415                                 compatible = "st,stm32-timer-trigger";
 416                                 reg = <0>;
 417                                 status = "disabled";
 418                         };
 419                 };
 420
 421                 timers8: timers@40010400 {
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                         compatible = "st,stm32-timers";
 425                         reg = <0x40010400 0x400>;
 426                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
 427                         clock-names = "int";
 428                         status = "disabled";
 429
 430                         pwm {
 431                                 compatible = "st,stm32-pwm";
 432                                 status = "disabled";
 433                         };
 434
 435                         timer@7 {
 436                                 compatible = "st,stm32-timer-trigger";
 437                                 reg = <7>;
 438                                 status = "disabled";
 439                         };
 440                 };
 441
 442                 usart1: serial@40011000 {
 443                         compatible = "st,stm32-uart";
 444                         reg = <0x40011000 0x400>;
 445                         interrupts = <37>;
 446                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
 447                         status = "disabled";
 448                         dmas = <&dma2 2 4 0x400 0x0>,
 449                                <&dma2 7 4 0x400 0x0>;
 450                         dma-names = "rx", "tx";
 451                 };
 452
 453                 usart6: serial@40011400 {
 454                         compatible = "st,stm32-uart";
 455                         reg = <0x40011400 0x400>;
 456                         interrupts = <71>;
 457                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
 458                         status = "disabled";
 459                 };
 460
 461                 adc: adc@40012000 {
 462                         compatible = "st,stm32f4-adc-core";
 463                         reg = <0x40012000 0x400>;
 464                         interrupts = <18>;
 465                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 466                         clock-names = "adc";
 467                         interrupt-controller;
 468                         #interrupt-cells = <1>;
 469                         #address-cells = <1>;
 470                         #size-cells = <0>;
 471                         status = "disabled";
 472
 473                         adc1: adc@0 {
 474                                 compatible = "st,stm32f4-adc";
 475                                 #io-channel-cells = <1>;
 476                                 reg = <0x0>;
 477                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 478                                 interrupt-parent = <&adc>;
 479                                 interrupts = <0>;
 480                                 dmas = <&dma2 0 0 0x400 0x0>;
 481                                 dma-names = "rx";
 482                                 status = "disabled";
 483                         };
 484
 485                         adc2: adc@100 {
 486                                 compatible = "st,stm32f4-adc";
 487                                 #io-channel-cells = <1>;
 488                                 reg = <0x100>;
 489                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
 490                                 interrupt-parent = <&adc>;
 491                                 interrupts = <1>;
 492                                 dmas = <&dma2 3 1 0x400 0x0>;
 493                                 dma-names = "rx";
 494                                 status = "disabled";
 495                         };
 496
 497                         adc3: adc@200 {
 498                                 compatible = "st,stm32f4-adc";
 499                                 #io-channel-cells = <1>;
 500                                 reg = <0x200>;
 501                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
 502                                 interrupt-parent = <&adc>;
 503                                 interrupts = <2>;
 504                                 dmas = <&dma2 1 2 0x400 0x0>;
 505                                 dma-names = "rx";
 506                                 status = "disabled";
 507                         };
 508                 };
 509
 510                 syscfg: system-config@40013800 {
 511                         compatible = "syscon";
 512                         reg = <0x40013800 0x400>;
 513                 };
 514
 515                 exti: interrupt-controller@40013c00 {
 516                         compatible = "st,stm32-exti";
 517                         interrupt-controller;
 518                         #interrupt-cells = <2>;
 519                         reg = <0x40013C00 0x400>;
 520                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 521                 };
 522
 523                 timers9: timers@40014000 {
 524                         #address-cells = <1>;
 525                         #size-cells = <0>;
 526                         compatible = "st,stm32-timers";
 527                         reg = <0x40014000 0x400>;
 528                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
 529                         clock-names = "int";
 530                         status = "disabled";
 531
 532                         pwm {
 533                                 compatible = "st,stm32-pwm";
 534                                 status = "disabled";
 535                         };
 536
 537                         timer@8 {
 538                                 compatible = "st,stm32-timer-trigger";
 539                                 reg = <8>;
 540                                 status = "disabled";
 541                         };
 542                 };
 543
 544                 timers10: timers@40014400 {
 545                         #address-cells = <1>;
 546                         #size-cells = <0>;
 547                         compatible = "st,stm32-timers";
 548                         reg = <0x40014400 0x400>;
 549                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
 550                         clock-names = "int";
 551                         status = "disabled";
 552
 553                         pwm {
 554                                 compatible = "st,stm32-pwm";
 555                                 status = "disabled";
 556                         };
 557                 };
 558
 559                 timers11: timers@40014800 {
 560                         #address-cells = <1>;
 561                         #size-cells = <0>;
 562                         compatible = "st,stm32-timers";
 563                         reg = <0x40014800 0x400>;
 564                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
 565                         clock-names = "int";
 566                         status = "disabled";
 567
 568                         pwm {
 569                                 compatible = "st,stm32-pwm";
 570                                 status = "disabled";
 571                         };
 572                 };
 573
 574                 pwrcfg: power-config@40007000 {
 575                         compatible = "syscon";
 576                         reg = <0x40007000 0x400>;
 577                 };
 578
 579                 sdio: sdio@40012c00 {
 580                         compatible = "st,stm32f4xx-sdio";
 581                         reg = <0x40012c00 0x400>;
 582                         clocks = <&rcc 0 171>;
 583                         interrupts = <49>;
 584                         status = "disabled";
 585                         pinctrl-0 = <&sdio_pins>;
 586                         pinctrl-1 = <&sdio_pins_od>;
 587                         pinctrl-names = "default", "opendrain";
 588                         max-frequency = <48000000>;
 589                 };
 590
 591                 ltdc: display-controller@40016800 {
 592                         compatible = "st,stm32-ltdc";
 593                         reg = <0x40016800 0x200>;
 594                         interrupts = <88>, <89>;
 595                         resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
 596                         clocks = <&rcc 1 CLK_LCD>;
 597                         clock-names = "lcd";
 598                         status = "disabled";
 599                 };
 600
 601                 crc: crc@40023000 {
 602                         compatible = "st,stm32f4-crc";
 603                         reg = <0x40023000 0x400>;
 604                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
 605                         status = "disabled";
 606                 };
 607
 608                 rcc: rcc@40023810 {
 609                         #reset-cells = <1>;
 610                         #clock-cells = <2>;
 611                         compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
 612                         reg = <0x40023800 0x400>;
 613                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
 614                         st,syscfg = <&pwrcfg>;
 615                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 616                         assigned-clock-rates = <1000000>;
 617                 };
 618
 619                 dma1: dma-controller@40026000 {
 620                         compatible = "st,stm32-dma";
 621                         reg = <0x40026000 0x400>;
 622                         interrupts = <11>,
 623                                      <12>,
 624                                      <13>,
 625                                      <14>,
 626                                      <15>,
 627                                      <16>,
 628                                      <17>,
 629                                      <47>;
 630                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
 631                         #dma-cells = <4>;
 632                 };
 633
 634                 dma2: dma-controller@40026400 {
 635                         compatible = "st,stm32-dma";
 636                         reg = <0x40026400 0x400>;
 637                         interrupts = <56>,
 638                                      <57>,
 639                                      <58>,
 640                                      <59>,
 641                                      <60>,
 642                                      <68>,
 643                                      <69>,
 644                                      <70>;
 645                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
 646                         #dma-cells = <4>;
 647                         st,mem2mem;
 648                 };
 649
 650                 mac: ethernet@40028000 {
 651                         compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
 652                         reg = <0x40028000 0x8000>;
 653                         reg-names = "stmmaceth";
 654                         interrupts = <61>;
 655                         interrupt-names = "macirq";
 656                         clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 657                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
 658                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
 659                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
 660                         st,syscon = <&syscfg 0x4>;
 661                         snps,pbl = <8>;
 662                         snps,mixed-burst;
 663                         status = "disabled";
 664                 };
 665
 666                 usbotg_hs: usb@40040000 {
 667                         compatible = "snps,dwc2";
 668                         reg = <0x40040000 0x40000>;
 669                         interrupts = <77>;
 670                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
 671                         clock-names = "otg";
 672                         status = "disabled";
 673                 };
 674
 675                 usbotg_fs: usb@50000000 {
 676                         compatible = "st,stm32f4x9-fsotg";
 677                         reg = <0x50000000 0x40000>;
 678                         interrupts = <67>;
 679                         clocks = <&rcc 0 39>;
 680                         clock-names = "otg";
 681                         status = "disabled";
 682                 };
 683
 684                 dcmi: dcmi@50050000 {
 685                         compatible = "st,stm32-dcmi";
 686                         reg = <0x50050000 0x400>;
 687                         interrupts = <78>;
 688                         resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
 689                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
 690                         clock-names = "mclk";
 691                         pinctrl-names = "default";
 692                         pinctrl-0 = <&dcmi_pins>;
 693                         dmas = <&dma2 1 1 0x414 0x3>;
 694                         dma-names = "tx";
 695                         status = "disabled";
 696                 };
 697
 698                 rng: rng@50060800 {
 699                         compatible = "st,stm32-rng";
 700                         reg = <0x50060800 0x400>;
 701                         interrupts = <80>;
 702                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
 703
 704                 };
 705         };
 706 };
 707
 708 &systick {
 709         clocks = <&rcc 1 SYSTICK>;
 710         status = "okay";
 711 };