git.sur5r.net Git - u-boot/blob - arch/arm/dts/stm32f746.dtsi

   1 /*
   2  * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
   3  *
   4  * Based on:
   5  * stm32f429.dtsi from Linux
   6  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   7  *
   8  * This file is dual-licensed: you can use it either under the terms
   9  * of the GPL or the X11 license, at your option. Note that this dual
  10  * licensing only applies to this file, and not this project as a
  11  * whole.
  12  *
  13  *  a) This file is free software; you can redistribute it and/or
  14  *     modify it under the terms of the GNU General Public License as
  15  *     published by the Free Software Foundation; either version 2 of the
  16  *     License, or (at your option) any later version.
  17  *
  18  *     This file is distributed in the hope that it will be useful,
  19  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *     GNU General Public License for more details.
  22  *
  23  * Or, alternatively,
  24  *
  25  *  b) Permission is hereby granted, free of charge, to any person
  26  *     obtaining a copy of this software and associated documentation
  27  *     files (the "Software"), to deal in the Software without
  28  *     restriction, including without limitation the rights to use,
  29  *     copy, modify, merge, publish, distribute, sublicense, and/or
  30  *     sell copies of the Software, and to permit persons to whom the
  31  *     Software is furnished to do so, subject to the following
  32  *     conditions:
  33  *
  34  *     The above copyright notice and this permission notice shall be
  35  *     included in all copies or substantial portions of the Software.
  36  *
  37  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  44  *     OTHER DEALINGS IN THE SOFTWARE.
  45  */
  46
  47 #include "armv7-m.dtsi"
  48 #include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
  49
  50 / {
  51         clocks {
  52                 clk_hse: clk-hse {
  53                         #clock-cells = <0>;
  54                         compatible = "fixed-clock";
  55                         clock-frequency = <0>;
  56                 };
  57 };
  58
  59         soc {
  60                 u-boot,dm-pre-reloc;
  61                 mac: ethernet@40028000 {
  62                         compatible = "st,stm32-dwmac";
  63                         reg = <0x40028000 0x8000>;
  64                         reg-names = "stmmaceth";
  65                         interrupts = <61>, <62>;
  66                         interrupt-names = "macirq", "eth_wake_irq";
  67                         snps,pbl = <8>;
  68                         snps,mixed-burst;
  69                         dma-ranges;
  70                         status = "disabled";
  71                 };
  72
  73                 qspi: quadspi@A0001000 {
  74                         compatible = "st,stm32-qspi";
  75                         #address-cells = <1>;
  76                         #size-cells = <0>;
  77                         reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
  78                         reg-names = "QuadSPI", "QuadSPI-memory";
  79                         interrupts = <92>;
  80                         spi-max-frequency = <108000000>;
  81                         status = "disabled";
  82                 };
  83                 usart1: serial@40011000 {
  84                         compatible = "st,stm32-usart", "st,stm32-uart";
  85                         reg = <0x40011000 0x400>;
  86                         interrupts = <37>;
  87                         clocks = <&rcc 0 164>;
  88                         status = "disabled";
  89                         u-boot,dm-pre-reloc;
  90                 };
  91                 rcc: rcc@40023810 {
  92                         #reset-cells = <1>;
  93                         #clock-cells = <2>;
  94                         compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
  95                         reg = <0x40023800 0x400>;
  96                         clocks = <&clk_hse>;
  97                         u-boot,dm-pre-reloc;
  98                 };
  99
 100                 pinctrl: pin-controller {
 101                         #address-cells = <1>;
 102                         #size-cells = <1>;
 103                         compatible = "st,stm32f746-pinctrl";
 104                         ranges = <0 0x40020000 0x3000>;
 105                         u-boot,dm-pre-reloc;
 106                         pins-are-numbered;
 107
 108                         usart1_pins_a: usart1@0 {
 109                                 pins1 {
 110                                         pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
 111                                         bias-disable;
 112                                         drive-push-pull;
 113                                         slew-rate = <2>;
 114                                 };
 115                                 pins2 {
 116                                         pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
 117                                         bias-disable;
 118                                 };
 119                         };
 120                         ethernet_mii: mii@0 {
 121                                 pins {
 122                                         pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
 123                                                  <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
 124                                                  <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
 125                                                  <STM32F746_PA2_FUNC_ETH_MDIO>,
 126                                                  <STM32F746_PC1_FUNC_ETH_MDC>,
 127                                                  <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
 128                                                  <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
 129                                                  <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
 130                                                  <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
 131                                         slew-rate = <2>;
 132                                 };
 133                         };
 134                         qspi_pins: qspi@0{
 135                                 pins {
 136                                         pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
 137                                                  <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
 138                                                  <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
 139                                                  <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
 140                                                  <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
 141                                                  <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
 142                                         slew-rate = <2>;
 143                                 };
 144                         };
 145                 };
 146         };
 147 };
 148
 149 &systick {
 150         status = "okay";
 151 };