2 * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
3 * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
6 * stm32f429.dtsi from Linux
7 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
14 * a) This file is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of the
17 * License, or (at your option) any later version.
19 * This file is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
48 #include "armv7-m.dtsi"
49 #include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
55 compatible = "fixed-clock";
56 clock-frequency = <0>;
62 mac: ethernet@40028000 {
63 compatible = "st,stm32-dwmac";
64 reg = <0x40028000 0x8000>;
65 reg-names = "stmmaceth";
66 interrupts = <61>, <62>;
67 interrupt-names = "macirq", "eth_wake_irq";
75 compatible = "st,stm32-fmc";
76 reg = <0xA0000000 0x1000>;
81 qspi: quadspi@A0001000 {
82 compatible = "st,stm32-qspi";
85 reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
86 reg-names = "QuadSPI", "QuadSPI-memory";
88 spi-max-frequency = <108000000>;
92 usart1: serial@40011000 {
93 compatible = "st,stm32-usart", "st,stm32-uart";
94 reg = <0x40011000 0x400>;
96 clocks = <&rcc 0 164>;
103 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
104 reg = <0x40023800 0x400>;
109 pinctrl: pin-controller {
110 #address-cells = <1>;
112 compatible = "st,stm32f746-pinctrl";
113 ranges = <0 0x40020000 0x3000>;
117 gpioa: gpio@40020000 {
120 compatible = "st,stm32-gpio";
123 st,bank-name = "GPIOA";
127 gpiob: gpio@40020400 {
130 compatible = "st,stm32-gpio";
133 st,bank-name = "GPIOB";
138 gpioc: gpio@40020800 {
141 compatible = "st,stm32-gpio";
144 st,bank-name = "GPIOC";
148 gpiod: gpio@40020c00 {
151 compatible = "st,stm32-gpio";
154 st,bank-name = "GPIOD";
158 gpioe: gpio@40021000 {
161 compatible = "st,stm32-gpio";
162 reg = <0x1000 0x400>;
164 st,bank-name = "GPIOE";
168 gpiof: gpio@40021400 {
171 compatible = "st,stm32-gpio";
172 reg = <0x1400 0x400>;
174 st,bank-name = "GPIOF";
178 gpiog: gpio@40021800 {
181 compatible = "st,stm32-gpio";
182 reg = <0x1800 0x400>;
184 st,bank-name = "GPIOG";
188 gpioh: gpio@40021c00 {
191 compatible = "st,stm32-gpio";
192 reg = <0x1c00 0x400>;
194 st,bank-name = "GPIOH";
198 gpioi: gpio@40022000 {
201 compatible = "st,stm32-gpio";
202 reg = <0x2000 0x400>;
204 st,bank-name = "GPIOI";
208 gpioj: gpio@40022400 {
211 compatible = "st,stm32-gpio";
212 reg = <0x2400 0x400>;
214 st,bank-name = "GPIOJ";
218 gpiok: gpio@40022800 {
221 compatible = "st,stm32-gpio";
222 reg = <0x2800 0x400>;
223 clocks = <&rcc 0 10>;
224 st,bank-name = "GPIOK";
228 usart1_pins_a: usart1@0 {
230 pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
236 pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
240 ethernet_mii: mii@0 {
242 pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
243 <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
244 <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
245 <STM32F746_PA2_FUNC_ETH_MDIO>,
246 <STM32F746_PC1_FUNC_ETH_MDC>,
247 <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
248 <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
249 <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
250 <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
256 pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
257 <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
258 <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
259 <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
260 <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
261 <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
268 pinmux = <STM32F746_PD10_FUNC_FMC_D15>,
269 <STM32F746_PD9_FUNC_FMC_D14>,
270 <STM32F746_PD8_FUNC_FMC_D13>,
271 <STM32F746_PE15_FUNC_FMC_D12>,
272 <STM32F746_PE14_FUNC_FMC_D11>,
273 <STM32F746_PE13_FUNC_FMC_D10>,
274 <STM32F746_PE12_FUNC_FMC_D9>,
275 <STM32F746_PE11_FUNC_FMC_D8>,
276 <STM32F746_PE10_FUNC_FMC_D7>,
277 <STM32F746_PE9_FUNC_FMC_D6>,
278 <STM32F746_PE8_FUNC_FMC_D5>,
279 <STM32F746_PE7_FUNC_FMC_D4>,
280 <STM32F746_PD1_FUNC_FMC_D3>,
281 <STM32F746_PD0_FUNC_FMC_D2>,
282 <STM32F746_PD15_FUNC_FMC_D1>,
283 <STM32F746_PD14_FUNC_FMC_D0>,
285 <STM32F746_PE1_FUNC_FMC_NBL1>,
286 <STM32F746_PE0_FUNC_FMC_NBL0>,
288 <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
289 <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
291 <STM32F746_PG1_FUNC_FMC_A11>,
292 <STM32F746_PG0_FUNC_FMC_A10>,
293 <STM32F746_PF15_FUNC_FMC_A9>,
294 <STM32F746_PF14_FUNC_FMC_A8>,
295 <STM32F746_PF13_FUNC_FMC_A7>,
296 <STM32F746_PF12_FUNC_FMC_A6>,
297 <STM32F746_PF5_FUNC_FMC_A5>,
298 <STM32F746_PF4_FUNC_FMC_A4>,
299 <STM32F746_PF3_FUNC_FMC_A3>,
300 <STM32F746_PF2_FUNC_FMC_A2>,
301 <STM32F746_PF1_FUNC_FMC_A1>,
302 <STM32F746_PF0_FUNC_FMC_A0>,
304 <STM32F746_PH3_FUNC_FMC_SDNE0>,
305 <STM32F746_PH5_FUNC_FMC_SDNWE>,
306 <STM32F746_PF11_FUNC_FMC_SDNRAS>,
307 <STM32F746_PG15_FUNC_FMC_SDNCAS>,
308 <STM32F746_PC3_FUNC_FMC_SDCKE0>,
309 <STM32F746_PG8_FUNC_FMC_SDCLK>;