git.sur5r.net Git - u-boot/blob - arch/arm/dts/stm32mp15-ddr.dtsi

   1 /*
   2  * Copyright : STMicroelectronics 2018
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+        BSD-3-Clause
   5  */
   6
   7 / {
   8         soc {
   9                 ddr: ddr@0x5A003000{
  10                         u-boot,dm-pre-reloc;
  11
  12                         compatible = "st,stm32mp1-ddr";
  13
  14                         reg = <0x5A003000 0x550
  15                                0x5A004000 0x234>;
  16
  17                         clocks = <&rcc_clk AXIDCG>,
  18                                  <&rcc_clk DDRC1>,
  19                                  <&rcc_clk DDRC2>,
  20                                  <&rcc_clk DDRPHYC>,
  21                                  <&rcc_clk DDRCAPB>,
  22                                  <&rcc_clk DDRPHYCAPB>;
  23
  24                         clock-names = "axidcg",
  25                                       "ddrc1",
  26                                       "ddrc2",
  27                                       "ddrphyc",
  28                                       "ddrcapb",
  29                                       "ddrphycapb";
  30
  31                         st,mem-name = DDR_MEM_NAME;
  32                         st,mem-speed = <DDR_MEM_SPEED>;
  33                         st,mem-size = <DDR_MEM_SIZE>;
  34
  35                         st,ctl-reg = <
  36                                 DDR_MSTR
  37                                 DDR_MRCTRL0
  38                                 DDR_MRCTRL1
  39                                 DDR_DERATEEN
  40                                 DDR_DERATEINT
  41                                 DDR_PWRCTL
  42                                 DDR_PWRTMG
  43                                 DDR_HWLPCTL
  44                                 DDR_RFSHCTL0
  45                                 DDR_RFSHCTL3
  46                                 DDR_CRCPARCTL0
  47                                 DDR_ZQCTL0
  48                                 DDR_DFITMG0
  49                                 DDR_DFITMG1
  50                                 DDR_DFILPCFG0
  51                                 DDR_DFIUPD0
  52                                 DDR_DFIUPD1
  53                                 DDR_DFIUPD2
  54                                 DDR_DFIPHYMSTR
  55                                 DDR_ODTMAP
  56                                 DDR_DBG0
  57                                 DDR_DBG1
  58                                 DDR_DBGCMD
  59                                 DDR_POISONCFG
  60                                 DDR_PCCFG
  61                         >;
  62
  63                         st,ctl-timing = <
  64                                 DDR_RFSHTMG
  65                                 DDR_DRAMTMG0
  66                                 DDR_DRAMTMG1
  67                                 DDR_DRAMTMG2
  68                                 DDR_DRAMTMG3
  69                                 DDR_DRAMTMG4
  70                                 DDR_DRAMTMG5
  71                                 DDR_DRAMTMG6
  72                                 DDR_DRAMTMG7
  73                                 DDR_DRAMTMG8
  74                                 DDR_DRAMTMG14
  75                                 DDR_ODTCFG
  76                         >;
  77
  78                         st,ctl-map = <
  79                                 DDR_ADDRMAP1
  80                                 DDR_ADDRMAP2
  81                                 DDR_ADDRMAP3
  82                                 DDR_ADDRMAP4
  83                                 DDR_ADDRMAP5
  84                                 DDR_ADDRMAP6
  85                                 DDR_ADDRMAP9
  86                                 DDR_ADDRMAP10
  87                                 DDR_ADDRMAP11
  88                         >;
  89
  90                         st,ctl-perf = <
  91                                 DDR_SCHED
  92                                 DDR_SCHED1
  93                                 DDR_PERFHPR1
  94                                 DDR_PERFLPR1
  95                                 DDR_PERFWR1
  96                                 DDR_PCFGR_0
  97                                 DDR_PCFGW_0
  98                                 DDR_PCFGQOS0_0
  99                                 DDR_PCFGQOS1_0
 100                                 DDR_PCFGWQOS0_0
 101                                 DDR_PCFGWQOS1_0
 102                                 DDR_PCFGR_1
 103                                 DDR_PCFGW_1
 104                                 DDR_PCFGQOS0_1
 105                                 DDR_PCFGQOS1_1
 106                                 DDR_PCFGWQOS0_1
 107                                 DDR_PCFGWQOS1_1
 108                         >;
 109
 110                         st,phy-reg = <
 111                                 DDR_PGCR
 112                                 DDR_ACIOCR
 113                                 DDR_DXCCR
 114                                 DDR_DSGCR
 115                                 DDR_DCR
 116                                 DDR_ODTCR
 117                                 DDR_ZQ0CR1
 118                                 DDR_DX0GCR
 119                                 DDR_DX1GCR
 120                                 DDR_DX2GCR
 121                                 DDR_DX3GCR
 122                         >;
 123
 124                         st,phy-timing = <
 125                                 DDR_PTR0
 126                                 DDR_PTR1
 127                                 DDR_PTR2
 128                                 DDR_DTPR0
 129                                 DDR_DTPR1
 130                                 DDR_DTPR2
 131                                 DDR_MR0
 132                                 DDR_MR1
 133                                 DDR_MR2
 134                                 DDR_MR3
 135                         >;
 136
 137                         st,phy-cal = <
 138                                 DDR_DX0DLLCR
 139                                 DDR_DX0DQTR
 140                                 DDR_DX0DQSTR
 141                                 DDR_DX1DLLCR
 142                                 DDR_DX1DQTR
 143                                 DDR_DX1DQSTR
 144                                 DDR_DX2DLLCR
 145                                 DDR_DX2DQTR
 146                                 DDR_DX2DQSTR
 147                                 DDR_DX3DLLCR
 148                                 DDR_DX3DQTR
 149                                 DDR_DX3DQSTR
 150                         >;
 151
 152                         status = "okay";
 153                 };
 154         };
 155 };