git.sur5r.net Git - u-boot/blob - arch/arm/dts/stm32mp157.dtsi

   1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
   2 /*
   3  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp1-clks.h>
   8 #include <dt-bindings/reset-controller/stm32mp1-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                 };
  23
  24                 cpu1: cpu@1 {
  25                         compatible = "arm,cortex-a7";
  26                         device_type = "cpu";
  27                         reg = <1>;
  28                 };
  29         };
  30
  31         aliases {
  32                 serial3 = &uart4;
  33         };
  34
  35         intc: interrupt-controller@a0021000 {
  36                 compatible = "arm,cortex-a7-gic";
  37                 #interrupt-cells = <3>;
  38                 interrupt-controller;
  39                 reg = <0xa0021000 0x1000>,
  40                       <0xa0022000 0x2000>;
  41         };
  42
  43         clocks {
  44                 clk_hse: clk-hse {
  45                         #clock-cells = <0>;
  46                         compatible = "fixed-clock";
  47                         clock-frequency = <24000000>;
  48                 };
  49
  50                 clk_hsi: clk-hsi {
  51                         #clock-cells = <0>;
  52                         compatible = "fixed-clock";
  53                         clock-frequency = <64000000>;
  54                 };
  55
  56                 clk_lse: clk-lse {
  57                         #clock-cells = <0>;
  58                         compatible = "fixed-clock";
  59                         clock-frequency = <32768>;
  60                 };
  61
  62                 clk_lsi: clk-lsi {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <32000>;
  66                 };
  67
  68                 clk_csi: clk-csi {
  69                         #clock-cells = <0>;
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <4000000>;
  72                 };
  73         };
  74
  75         soc {
  76                 compatible = "simple-bus";
  77                 #address-cells = <1>;
  78                 #size-cells = <1>;
  79                 interrupt-parent = <&intc>;
  80                 ranges;
  81
  82                 uart4: serial@40010000 {
  83                         compatible = "st,stm32h7-uart";
  84                         reg = <0x40010000 0x400>;
  85                         clocks = <&rcc_clk UART4_K>;
  86                         status = "disabled";
  87                 };
  88
  89                 sdmmc3: sdmmc@48004000 {
  90                         compatible = "st,stm32-sdmmc2";
  91                         reg = <0x48004000 0x400>, <0x48005000 0x400>;
  92                         reg-names = "sdmmc", "delay";
  93                         interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>;
  94                         clocks = <&rcc_clk SDMMC3_K>;
  95                         resets = <&rcc_rst SDMMC3_R>;
  96                         st,idma = <1>;
  97                         cap-sd-highspeed;
  98                         cap-mmc-highspeed;
  99                         max-frequency = <120000000>;
 100                         status = "disabled";
 101                 };
 102
 103                 rcc: rcc@50000000 {
 104                         compatible = "syscon", "simple-mfd";
 105
 106                         reg = <0x50000000 0x1000>;
 107
 108                         rcc_clk: rcc-clk@50000000 {
 109                                 #clock-cells = <1>;
 110                                 compatible = "st,stm32mp1-rcc-clk";
 111                         };
 112
 113                         rcc_rst: rcc-reset@50000000 {
 114                                 #reset-cells = <1>;
 115                                 compatible = "st,stm32mp1-rcc-rst";
 116                         };
 117                 };
 118
 119                 pinctrl: pin-controller {
 120                         compatible = "st,stm32mp157-pinctrl";
 121                         #address-cells = <1>;
 122                         #size-cells = <1>;
 123                         ranges = <0 0x50002000 0xa400>;
 124                         pins-are-numbered;
 125
 126                         gpioa: gpio@50002000 {
 127                                 gpio-controller;
 128                                 #gpio-cells = <2>;
 129                                 interrupt-controller;
 130                                 #interrupt-cells = <2>;
 131                                 reg = <0x0 0x400>;
 132                                 clocks = <&rcc_clk GPIOA>;
 133                                 st,bank-name = "GPIOA";
 134                                 ngpios = <16>;
 135                                 gpio-ranges = <&pinctrl 0 0 16>;
 136                                 status = "disabled";
 137                         };
 138
 139                         gpiob: gpio@50003000 {
 140                                 gpio-controller;
 141                                 #gpio-cells = <2>;
 142                                 interrupt-controller;
 143                                 #interrupt-cells = <2>;
 144                                 reg = <0x1000 0x400>;
 145                                 clocks = <&rcc_clk GPIOB>;
 146                                 st,bank-name = "GPIOB";
 147                                 ngpios = <16>;
 148                                 gpio-ranges = <&pinctrl 0 16 16>;
 149                                 status = "disabled";
 150                         };
 151
 152                         gpioc: gpio@50004000 {
 153                                 gpio-controller;
 154                                 #gpio-cells = <2>;
 155                                 interrupt-controller;
 156                                 #interrupt-cells = <2>;
 157                                 reg = <0x2000 0x400>;
 158                                 clocks = <&rcc_clk GPIOC>;
 159                                 st,bank-name = "GPIOC";
 160                                 ngpios = <16>;
 161                                 gpio-ranges = <&pinctrl 0 32 16>;
 162                                 status = "disabled";
 163                         };
 164
 165                         gpiod: gpio@50005000 {
 166                                 gpio-controller;
 167                                 #gpio-cells = <2>;
 168                                 interrupt-controller;
 169                                 #interrupt-cells = <2>;
 170                                 reg = <0x3000 0x400>;
 171                                 clocks = <&rcc_clk GPIOD>;
 172                                 st,bank-name = "GPIOD";
 173                                 ngpios = <16>;
 174                                 gpio-ranges = <&pinctrl 0 48 16>;
 175                                 status = "disabled";
 176                         };
 177
 178                         gpioe: gpio@50006000 {
 179                                 gpio-controller;
 180                                 #gpio-cells = <2>;
 181                                 interrupt-controller;
 182                                 #interrupt-cells = <2>;
 183                                 reg = <0x4000 0x400>;
 184                                 clocks = <&rcc_clk GPIOE>;
 185                                 st,bank-name = "GPIOE";
 186                                 ngpios = <16>;
 187                                 gpio-ranges = <&pinctrl 0 64 16>;
 188                                 status = "disabled";
 189                         };
 190
 191                         gpiof: gpio@50007000 {
 192                                 gpio-controller;
 193                                 #gpio-cells = <2>;
 194                                 interrupt-controller;
 195                                 #interrupt-cells = <2>;
 196                                 reg = <0x5000 0x400>;
 197                                 clocks = <&rcc_clk GPIOF>;
 198                                 st,bank-name = "GPIOF";
 199                                 ngpios = <16>;
 200                                 gpio-ranges = <&pinctrl 0 80 16>;
 201                                 status = "disabled";
 202                         };
 203
 204                         gpiog: gpio@50008000 {
 205                                 gpio-controller;
 206                                 #gpio-cells = <2>;
 207                                 interrupt-controller;
 208                                 #interrupt-cells = <2>;
 209                                 reg = <0x6000 0x400>;
 210                                 clocks = <&rcc_clk GPIOG>;
 211                                 st,bank-name = "GPIOG";
 212                                 ngpios = <16>;
 213                                 gpio-ranges = <&pinctrl 0 96 16>;
 214                                 status = "disabled";
 215                         };
 216
 217                         gpioh: gpio@50009000 {
 218                                 gpio-controller;
 219                                 #gpio-cells = <2>;
 220                                 interrupt-controller;
 221                                 #interrupt-cells = <2>;
 222                                 reg = <0x7000 0x400>;
 223                                 clocks = <&rcc_clk GPIOH>;
 224                                 st,bank-name = "GPIOH";
 225                                 ngpios = <16>;
 226                                 gpio-ranges = <&pinctrl 0 112 16>;
 227                                 status = "disabled";
 228                         };
 229
 230                         gpioi: gpio@5000a000 {
 231                                 gpio-controller;
 232                                 #gpio-cells = <2>;
 233                                 interrupt-controller;
 234                                 #interrupt-cells = <2>;
 235                                 reg = <0x8000 0x400>;
 236                                 clocks = <&rcc_clk GPIOI>;
 237                                 st,bank-name = "GPIOI";
 238                                 ngpios = <16>;
 239                                 gpio-ranges = <&pinctrl 0 128 16>;
 240                                 status = "disabled";
 241                         };
 242
 243                         gpioj: gpio@5000b000 {
 244                                 gpio-controller;
 245                                 #gpio-cells = <2>;
 246                                 interrupt-controller;
 247                                 #interrupt-cells = <2>;
 248                                 reg = <0x9000 0x400>;
 249                                 clocks = <&rcc_clk GPIOJ>;
 250                                 st,bank-name = "GPIOJ";
 251                                 ngpios = <16>;
 252                                 gpio-ranges = <&pinctrl 0 144 16>;
 253                                 status = "disabled";
 254                         };
 255
 256                         gpiok: gpio@5000c000 {
 257                                 gpio-controller;
 258                                 #gpio-cells = <2>;
 259                                 interrupt-controller;
 260                                 #interrupt-cells = <2>;
 261                                 reg = <0xa000 0x400>;
 262                                 clocks = <&rcc_clk GPIOK>;
 263                                 st,bank-name = "GPIOK";
 264                                 ngpios = <8>;
 265                                 gpio-ranges = <&pinctrl 0 160 8>;
 266                                 status = "disabled";
 267                         };
 268                 };
 269
 270                 pinctrl_z: pin-controller-z {
 271                         compatible = "st,stm32mp157-z-pinctrl";
 272                         #address-cells = <1>;
 273                         #size-cells = <1>;
 274                         ranges = <0 0x54004000 0x400>;
 275                         pins-are-numbered;
 276
 277                         gpioz: gpio@54004000 {
 278                                 gpio-controller;
 279                                 #gpio-cells = <2>;
 280                                 interrupt-controller;
 281                                 #interrupt-cells = <2>;
 282                                 reg = <0 0x400>;
 283                                 clocks = <&rcc_clk GPIOZ>;
 284                                 st,bank-name = "GPIOZ";
 285                                 st,bank-ioport = <11>;
 286                                 ngpios = <8>;
 287                                 gpio-ranges = <&pinctrl_z 0 400 8>;
 288                                 status = "disabled";
 289                         };
 290                 };
 291
 292                 sdmmc1: sdmmc@58005000 {
 293                         compatible = "st,stm32-sdmmc2";
 294                         reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
 295                         reg-names = "sdmmc", "delay";
 296                         clocks = <&rcc_clk SDMMC1_K>;
 297                         resets = <&rcc_rst SDMMC1_R>;
 298                         st,idma = <1>;
 299                         cap-sd-highspeed;
 300                         cap-mmc-highspeed;
 301                         max-frequency = <120000000>;
 302                         status = "disabled";
 303                 };
 304
 305                 sdmmc2: sdmmc@58007000 {
 306                         compatible = "st,stm32-sdmmc2";
 307                         reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
 308                         reg-names = "sdmmc", "delay";
 309                         interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
 310                         clocks = <&rcc_clk SDMMC2_K>;
 311                         resets = <&rcc_rst SDMMC2_R>;
 312                         st,idma = <1>;
 313                         cap-sd-highspeed;
 314                         cap-mmc-highspeed;
 315                         max-frequency = <120000000>;
 316                         status = "disabled";
 317                 };
 318
 319                 i2c4: i2c@5c002000 {
 320                         compatible = "st,stm32f7-i2c";
 321                         reg = <0x5c002000 0x400>;
 322                         interrupt-names = "event", "error", "wakeup";
 323                         clocks = <&rcc_clk I2C4_K>;
 324                         resets = <&rcc_rst I2C4_R>;
 325                         #address-cells = <1>;
 326                         #size-cells = <0>;
 327                         wakeup-source;
 328                         status = "disabled";
 329                 };
 330         };
 331 };