git.sur5r.net Git - u-boot/blob - arch/arm/dts/stm32mp157.dtsi

   1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
   2 /*
   3  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp1-clks.h>
   8 #include <dt-bindings/reset-controller/stm32mp1-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                 };
  23
  24                 cpu1: cpu@1 {
  25                         compatible = "arm,cortex-a7";
  26                         device_type = "cpu";
  27                         reg = <1>;
  28                 };
  29         };
  30
  31         aliases {
  32                 serial3 = &uart4;
  33         };
  34
  35         intc: interrupt-controller@a0021000 {
  36                 compatible = "arm,cortex-a7-gic";
  37                 #interrupt-cells = <3>;
  38                 interrupt-controller;
  39                 reg = <0xa0021000 0x1000>,
  40                       <0xa0022000 0x2000>;
  41         };
  42
  43         clocks {
  44                 clk_hse: clk-hse {
  45                         #clock-cells = <0>;
  46                         compatible = "fixed-clock";
  47                         clock-frequency = <24000000>;
  48                 };
  49
  50                 clk_hsi: clk-hsi {
  51                         #clock-cells = <0>;
  52                         compatible = "fixed-clock";
  53                         clock-frequency = <64000000>;
  54                 };
  55
  56                 clk_lse: clk-lse {
  57                         #clock-cells = <0>;
  58                         compatible = "fixed-clock";
  59                         clock-frequency = <32768>;
  60                 };
  61
  62                 clk_lsi: clk-lsi {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <32000>;
  66                 };
  67
  68                 clk_csi: clk-csi {
  69                         #clock-cells = <0>;
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <4000000>;
  72                 };
  73         };
  74
  75         soc {
  76                 compatible = "simple-bus";
  77                 #address-cells = <1>;
  78                 #size-cells = <1>;
  79                 interrupt-parent = <&intc>;
  80                 ranges;
  81
  82                 uart4: serial@40010000 {
  83                         compatible = "st,stm32h7-uart";
  84                         reg = <0x40010000 0x400>;
  85                         clocks = <&rcc_clk UART4_K>;
  86                         status = "disabled";
  87                 };
  88
  89                 sdmmc3: sdmmc@48004000 {
  90                         compatible = "st,stm32-sdmmc2";
  91                         reg = <0x48004000 0x400>, <0x48005000 0x400>;
  92                         reg-names = "sdmmc", "delay";
  93                         interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>;
  94                         clocks = <&rcc_clk SDMMC3_K>;
  95                         resets = <&rcc_rst SDMMC3_R>;
  96                         st,idma = <1>;
  97                         cap-sd-highspeed;
  98                         cap-mmc-highspeed;
  99                         max-frequency = <120000000>;
 100                         status = "disabled";
 101                 };
 102
 103                 rcc: rcc@50000000 {
 104                         compatible = "syscon", "simple-mfd";
 105
 106                         reg = <0x50000000 0x1000>;
 107
 108                         rcc_clk: rcc-clk@50000000 {
 109                                 #clock-cells = <1>;
 110                                 compatible = "st,stm32mp1-rcc-clk";
 111                         };
 112
 113                         rcc_rst: rcc-reset@50000000 {
 114                                 #reset-cells = <1>;
 115                                 compatible = "st,stm32mp1-rcc-rst";
 116                         };
 117
 118                         rcc_reboot: rcc-reboot@50000000 {
 119                                 compatible = "syscon-reboot";
 120                                 regmap = <&rcc>;
 121                                 offset = <0x404>;
 122                                 mask = <0x1>;
 123                         };
 124                 };
 125
 126                 pinctrl: pin-controller {
 127                         compatible = "st,stm32mp157-pinctrl";
 128                         #address-cells = <1>;
 129                         #size-cells = <1>;
 130                         ranges = <0 0x50002000 0xa400>;
 131                         pins-are-numbered;
 132
 133                         gpioa: gpio@50002000 {
 134                                 gpio-controller;
 135                                 #gpio-cells = <2>;
 136                                 interrupt-controller;
 137                                 #interrupt-cells = <2>;
 138                                 reg = <0x0 0x400>;
 139                                 clocks = <&rcc_clk GPIOA>;
 140                                 st,bank-name = "GPIOA";
 141                                 ngpios = <16>;
 142                                 gpio-ranges = <&pinctrl 0 0 16>;
 143                                 status = "disabled";
 144                         };
 145
 146                         gpiob: gpio@50003000 {
 147                                 gpio-controller;
 148                                 #gpio-cells = <2>;
 149                                 interrupt-controller;
 150                                 #interrupt-cells = <2>;
 151                                 reg = <0x1000 0x400>;
 152                                 clocks = <&rcc_clk GPIOB>;
 153                                 st,bank-name = "GPIOB";
 154                                 ngpios = <16>;
 155                                 gpio-ranges = <&pinctrl 0 16 16>;
 156                                 status = "disabled";
 157                         };
 158
 159                         gpioc: gpio@50004000 {
 160                                 gpio-controller;
 161                                 #gpio-cells = <2>;
 162                                 interrupt-controller;
 163                                 #interrupt-cells = <2>;
 164                                 reg = <0x2000 0x400>;
 165                                 clocks = <&rcc_clk GPIOC>;
 166                                 st,bank-name = "GPIOC";
 167                                 ngpios = <16>;
 168                                 gpio-ranges = <&pinctrl 0 32 16>;
 169                                 status = "disabled";
 170                         };
 171
 172                         gpiod: gpio@50005000 {
 173                                 gpio-controller;
 174                                 #gpio-cells = <2>;
 175                                 interrupt-controller;
 176                                 #interrupt-cells = <2>;
 177                                 reg = <0x3000 0x400>;
 178                                 clocks = <&rcc_clk GPIOD>;
 179                                 st,bank-name = "GPIOD";
 180                                 ngpios = <16>;
 181                                 gpio-ranges = <&pinctrl 0 48 16>;
 182                                 status = "disabled";
 183                         };
 184
 185                         gpioe: gpio@50006000 {
 186                                 gpio-controller;
 187                                 #gpio-cells = <2>;
 188                                 interrupt-controller;
 189                                 #interrupt-cells = <2>;
 190                                 reg = <0x4000 0x400>;
 191                                 clocks = <&rcc_clk GPIOE>;
 192                                 st,bank-name = "GPIOE";
 193                                 ngpios = <16>;
 194                                 gpio-ranges = <&pinctrl 0 64 16>;
 195                                 status = "disabled";
 196                         };
 197
 198                         gpiof: gpio@50007000 {
 199                                 gpio-controller;
 200                                 #gpio-cells = <2>;
 201                                 interrupt-controller;
 202                                 #interrupt-cells = <2>;
 203                                 reg = <0x5000 0x400>;
 204                                 clocks = <&rcc_clk GPIOF>;
 205                                 st,bank-name = "GPIOF";
 206                                 ngpios = <16>;
 207                                 gpio-ranges = <&pinctrl 0 80 16>;
 208                                 status = "disabled";
 209                         };
 210
 211                         gpiog: gpio@50008000 {
 212                                 gpio-controller;
 213                                 #gpio-cells = <2>;
 214                                 interrupt-controller;
 215                                 #interrupt-cells = <2>;
 216                                 reg = <0x6000 0x400>;
 217                                 clocks = <&rcc_clk GPIOG>;
 218                                 st,bank-name = "GPIOG";
 219                                 ngpios = <16>;
 220                                 gpio-ranges = <&pinctrl 0 96 16>;
 221                                 status = "disabled";
 222                         };
 223
 224                         gpioh: gpio@50009000 {
 225                                 gpio-controller;
 226                                 #gpio-cells = <2>;
 227                                 interrupt-controller;
 228                                 #interrupt-cells = <2>;
 229                                 reg = <0x7000 0x400>;
 230                                 clocks = <&rcc_clk GPIOH>;
 231                                 st,bank-name = "GPIOH";
 232                                 ngpios = <16>;
 233                                 gpio-ranges = <&pinctrl 0 112 16>;
 234                                 status = "disabled";
 235                         };
 236
 237                         gpioi: gpio@5000a000 {
 238                                 gpio-controller;
 239                                 #gpio-cells = <2>;
 240                                 interrupt-controller;
 241                                 #interrupt-cells = <2>;
 242                                 reg = <0x8000 0x400>;
 243                                 clocks = <&rcc_clk GPIOI>;
 244                                 st,bank-name = "GPIOI";
 245                                 ngpios = <16>;
 246                                 gpio-ranges = <&pinctrl 0 128 16>;
 247                                 status = "disabled";
 248                         };
 249
 250                         gpioj: gpio@5000b000 {
 251                                 gpio-controller;
 252                                 #gpio-cells = <2>;
 253                                 interrupt-controller;
 254                                 #interrupt-cells = <2>;
 255                                 reg = <0x9000 0x400>;
 256                                 clocks = <&rcc_clk GPIOJ>;
 257                                 st,bank-name = "GPIOJ";
 258                                 ngpios = <16>;
 259                                 gpio-ranges = <&pinctrl 0 144 16>;
 260                                 status = "disabled";
 261                         };
 262
 263                         gpiok: gpio@5000c000 {
 264                                 gpio-controller;
 265                                 #gpio-cells = <2>;
 266                                 interrupt-controller;
 267                                 #interrupt-cells = <2>;
 268                                 reg = <0xa000 0x400>;
 269                                 clocks = <&rcc_clk GPIOK>;
 270                                 st,bank-name = "GPIOK";
 271                                 ngpios = <8>;
 272                                 gpio-ranges = <&pinctrl 0 160 8>;
 273                                 status = "disabled";
 274                         };
 275                 };
 276
 277                 pinctrl_z: pin-controller-z {
 278                         compatible = "st,stm32mp157-z-pinctrl";
 279                         #address-cells = <1>;
 280                         #size-cells = <1>;
 281                         ranges = <0 0x54004000 0x400>;
 282                         pins-are-numbered;
 283
 284                         gpioz: gpio@54004000 {
 285                                 gpio-controller;
 286                                 #gpio-cells = <2>;
 287                                 interrupt-controller;
 288                                 #interrupt-cells = <2>;
 289                                 reg = <0 0x400>;
 290                                 clocks = <&rcc_clk GPIOZ>;
 291                                 st,bank-name = "GPIOZ";
 292                                 st,bank-ioport = <11>;
 293                                 ngpios = <8>;
 294                                 gpio-ranges = <&pinctrl_z 0 400 8>;
 295                                 status = "disabled";
 296                         };
 297                 };
 298
 299                 sdmmc1: sdmmc@58005000 {
 300                         compatible = "st,stm32-sdmmc2";
 301                         reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
 302                         reg-names = "sdmmc", "delay";
 303                         clocks = <&rcc_clk SDMMC1_K>;
 304                         resets = <&rcc_rst SDMMC1_R>;
 305                         st,idma = <1>;
 306                         cap-sd-highspeed;
 307                         cap-mmc-highspeed;
 308                         max-frequency = <120000000>;
 309                         status = "disabled";
 310                 };
 311
 312                 sdmmc2: sdmmc@58007000 {
 313                         compatible = "st,stm32-sdmmc2";
 314                         reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
 315                         reg-names = "sdmmc", "delay";
 316                         interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
 317                         clocks = <&rcc_clk SDMMC2_K>;
 318                         resets = <&rcc_rst SDMMC2_R>;
 319                         st,idma = <1>;
 320                         cap-sd-highspeed;
 321                         cap-mmc-highspeed;
 322                         max-frequency = <120000000>;
 323                         status = "disabled";
 324                 };
 325
 326                 i2c4: i2c@5c002000 {
 327                         compatible = "st,stm32f7-i2c";
 328                         reg = <0x5c002000 0x400>;
 329                         interrupt-names = "event", "error", "wakeup";
 330                         clocks = <&rcc_clk I2C4_K>;
 331                         resets = <&rcc_rst I2C4_R>;
 332                         #address-cells = <1>;
 333                         #size-cells = <0>;
 334                         wakeup-source;
 335                         status = "disabled";
 336                 };
 337         };
 338 };