git.sur5r.net Git - u-boot/blob - arch/arm/dts/sun4i-a10.dtsi

   1 /*
   2  * Copyright 2012 Stefan Roese
   3  * Stefan Roese <sr@denx.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This library is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This library is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include "skeleton.dtsi"
  45
  46 #include <dt-bindings/thermal/thermal.h>
  47
  48 #include <dt-bindings/clock/sun4i-a10-pll2.h>
  49 #include <dt-bindings/dma/sun4i-a10.h>
  50 #include <dt-bindings/pinctrl/sun4i-a10.h>
  51
  52 / {
  53         interrupt-parent = <&intc>;
  54
  55         aliases {
  56                 ethernet0 = &emac;
  57         };
  58
  59         chosen {
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 ranges;
  63
  64                 framebuffer@0 {
  65                         compatible = "allwinner,simple-framebuffer",
  66                                      "simple-framebuffer";
  67                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  68                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  69                                  <&ahb_gates 44>, <&dram_gates 26>;
  70                         status = "disabled";
  71                 };
  72
  73                 framebuffer@1 {
  74                         compatible = "allwinner,simple-framebuffer",
  75                                      "simple-framebuffer";
  76                         allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
  77                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  78                                  <&ahb_gates 44>, <&ahb_gates 46>,
  79                                  <&dram_gates 25>, <&dram_gates 26>;
  80                         status = "disabled";
  81                 };
  82
  83                 framebuffer@2 {
  84                         compatible = "allwinner,simple-framebuffer",
  85                                      "simple-framebuffer";
  86                         allwinner,pipeline = "de_fe0-de_be0-lcd0";
  87                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
  88                                  <&ahb_gates 46>, <&dram_gates 25>,
  89                                  <&dram_gates 26>;
  90                         status = "disabled";
  91                 };
  92
  93                 framebuffer@3 {
  94                         compatible = "allwinner,simple-framebuffer",
  95                                      "simple-framebuffer";
  96                         allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
  97                         clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
  98                                  <&ahb_gates 44>, <&ahb_gates 46>,
  99                                  <&dram_gates 25>, <&dram_gates 26>;
 100                         status = "disabled";
 101                 };
 102         };
 103
 104         cpus {
 105                 #address-cells = <1>;
 106                 #size-cells = <0>;
 107                 cpu0: cpu@0 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a8";
 110                         reg = <0x0>;
 111                         clocks = <&cpu>;
 112                         clock-latency = <244144>; /* 8 32k periods */
 113                         operating-points = <
 114                                 /* kHz    uV */
 115                                 1008000 1400000
 116                                 912000  1350000
 117                                 864000  1300000
 118                                 624000  1250000
 119                                 >;
 120                         #cooling-cells = <2>;
 121                         cooling-min-level = <0>;
 122                         cooling-max-level = <3>;
 123                 };
 124         };
 125
 126         thermal-zones {
 127                 cpu_thermal {
 128                         /* milliseconds */
 129                         polling-delay-passive = <250>;
 130                         polling-delay = <1000>;
 131                         thermal-sensors = <&rtp>;
 132
 133                         cooling-maps {
 134                                 map0 {
 135                                         trip = <&cpu_alert0>;
 136                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 137                                 };
 138                         };
 139
 140                         trips {
 141                                 cpu_alert0: cpu_alert0 {
 142                                         /* milliCelsius */
 143                                         temperature = <850000>;
 144                                         hysteresis = <2000>;
 145                                         type = "passive";
 146                                 };
 147
 148                                 cpu_crit: cpu_crit {
 149                                         /* milliCelsius */
 150                                         temperature = <100000>;
 151                                         hysteresis = <2000>;
 152                                         type = "critical";
 153                                 };
 154                         };
 155                 };
 156         };
 157
 158         memory {
 159                 reg = <0x40000000 0x80000000>;
 160         };
 161
 162         clocks {
 163                 #address-cells = <1>;
 164                 #size-cells = <1>;
 165                 ranges;
 166
 167                 /*
 168                  * This is a dummy clock, to be used as placeholder on
 169                  * other mux clocks when a specific parent clock is not
 170                  * yet implemented. It should be dropped when the driver
 171                  * is complete.
 172                  */
 173                 dummy: dummy {
 174                         #clock-cells = <0>;
 175                         compatible = "fixed-clock";
 176                         clock-frequency = <0>;
 177                 };
 178
 179                 osc24M: clk@01c20050 {
 180                         #clock-cells = <0>;
 181                         compatible = "allwinner,sun4i-a10-osc-clk";
 182                         reg = <0x01c20050 0x4>;
 183                         clock-frequency = <24000000>;
 184                         clock-output-names = "osc24M";
 185                 };
 186
 187                 osc32k: clk@0 {
 188                         #clock-cells = <0>;
 189                         compatible = "fixed-clock";
 190                         clock-frequency = <32768>;
 191                         clock-output-names = "osc32k";
 192                 };
 193
 194                 pll1: clk@01c20000 {
 195                         #clock-cells = <0>;
 196                         compatible = "allwinner,sun4i-a10-pll1-clk";
 197                         reg = <0x01c20000 0x4>;
 198                         clocks = <&osc24M>;
 199                         clock-output-names = "pll1";
 200                 };
 201
 202                 pll2: clk@01c20008 {
 203                         #clock-cells = <1>;
 204                         compatible = "allwinner,sun4i-a10-pll2-clk";
 205                         reg = <0x01c20008 0x8>;
 206                         clocks = <&osc24M>;
 207                         clock-output-names = "pll2-1x", "pll2-2x",
 208                                              "pll2-4x", "pll2-8x";
 209                 };
 210
 211                 pll4: clk@01c20018 {
 212                         #clock-cells = <0>;
 213                         compatible = "allwinner,sun4i-a10-pll1-clk";
 214                         reg = <0x01c20018 0x4>;
 215                         clocks = <&osc24M>;
 216                         clock-output-names = "pll4";
 217                 };
 218
 219                 pll5: clk@01c20020 {
 220                         #clock-cells = <1>;
 221                         compatible = "allwinner,sun4i-a10-pll5-clk";
 222                         reg = <0x01c20020 0x4>;
 223                         clocks = <&osc24M>;
 224                         clock-output-names = "pll5_ddr", "pll5_other";
 225                 };
 226
 227                 pll6: clk@01c20028 {
 228                         #clock-cells = <1>;
 229                         compatible = "allwinner,sun4i-a10-pll6-clk";
 230                         reg = <0x01c20028 0x4>;
 231                         clocks = <&osc24M>;
 232                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 233                 };
 234
 235                 /* dummy is 200M */
 236                 cpu: cpu@01c20054 {
 237                         #clock-cells = <0>;
 238                         compatible = "allwinner,sun4i-a10-cpu-clk";
 239                         reg = <0x01c20054 0x4>;
 240                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 241                         clock-output-names = "cpu";
 242                 };
 243
 244                 axi: axi@01c20054 {
 245                         #clock-cells = <0>;
 246                         compatible = "allwinner,sun4i-a10-axi-clk";
 247                         reg = <0x01c20054 0x4>;
 248                         clocks = <&cpu>;
 249                         clock-output-names = "axi";
 250                 };
 251
 252                 axi_gates: clk@01c2005c {
 253                         #clock-cells = <1>;
 254                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 255                         reg = <0x01c2005c 0x4>;
 256                         clocks = <&axi>;
 257                         clock-indices = <0>;
 258                         clock-output-names = "axi_dram";
 259                 };
 260
 261                 ahb: ahb@01c20054 {
 262                         #clock-cells = <0>;
 263                         compatible = "allwinner,sun4i-a10-ahb-clk";
 264                         reg = <0x01c20054 0x4>;
 265                         clocks = <&axi>;
 266                         clock-output-names = "ahb";
 267                 };
 268
 269                 ahb_gates: clk@01c20060 {
 270                         #clock-cells = <1>;
 271                         compatible = "allwinner,sun4i-a10-ahb-gates-clk";
 272                         reg = <0x01c20060 0x8>;
 273                         clocks = <&ahb>;
 274                         clock-indices = <0>, <1>,
 275                                         <2>, <3>,
 276                                         <4>, <5>, <6>,
 277                                         <7>, <8>, <9>,
 278                                         <10>, <11>, <12>,
 279                                         <13>, <14>, <16>,
 280                                         <17>, <18>, <20>,
 281                                         <21>, <22>, <23>,
 282                                         <24>, <25>, <26>,
 283                                         <32>, <33>, <34>,
 284                                         <35>, <36>, <37>,
 285                                         <40>, <41>, <43>,
 286                                         <44>, <45>,
 287                                         <46>, <47>,
 288                                         <50>, <52>;
 289                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 290                                              "ahb_ohci0", "ahb_ehci1",
 291                                              "ahb_ohci1", "ahb_ss", "ahb_dma",
 292                                              "ahb_bist", "ahb_mmc0", "ahb_mmc1",
 293                                              "ahb_mmc2", "ahb_mmc3", "ahb_ms",
 294                                              "ahb_nand", "ahb_sdram", "ahb_ace",
 295                                              "ahb_emac", "ahb_ts", "ahb_spi0",
 296                                              "ahb_spi1", "ahb_spi2", "ahb_spi3",
 297                                              "ahb_pata", "ahb_sata", "ahb_gps",
 298                                              "ahb_ve", "ahb_tvd", "ahb_tve0",
 299                                              "ahb_tve1", "ahb_lcd0", "ahb_lcd1",
 300                                              "ahb_csi0", "ahb_csi1", "ahb_hdmi",
 301                                              "ahb_de_be0", "ahb_de_be1",
 302                                              "ahb_de_fe0", "ahb_de_fe1",
 303                                              "ahb_mp", "ahb_mali400";
 304                 };
 305
 306                 apb0: apb0@01c20054 {
 307                         #clock-cells = <0>;
 308                         compatible = "allwinner,sun4i-a10-apb0-clk";
 309                         reg = <0x01c20054 0x4>;
 310                         clocks = <&ahb>;
 311                         clock-output-names = "apb0";
 312                 };
 313
 314                 apb0_gates: clk@01c20068 {
 315                         #clock-cells = <1>;
 316                         compatible = "allwinner,sun4i-a10-apb0-gates-clk";
 317                         reg = <0x01c20068 0x4>;
 318                         clocks = <&apb0>;
 319                         clock-indices = <0>, <1>,
 320                                         <2>, <3>,
 321                                         <5>, <6>,
 322                                         <7>, <10>;
 323                         clock-output-names = "apb0_codec", "apb0_spdif",
 324                                              "apb0_ac97", "apb0_iis",
 325                                              "apb0_pio", "apb0_ir0",
 326                                              "apb0_ir1", "apb0_keypad";
 327                 };
 328
 329                 apb1: clk@01c20058 {
 330                         #clock-cells = <0>;
 331                         compatible = "allwinner,sun4i-a10-apb1-clk";
 332                         reg = <0x01c20058 0x4>;
 333                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 334                         clock-output-names = "apb1";
 335                 };
 336
 337                 apb1_gates: clk@01c2006c {
 338                         #clock-cells = <1>;
 339                         compatible = "allwinner,sun4i-a10-apb1-gates-clk";
 340                         reg = <0x01c2006c 0x4>;
 341                         clocks = <&apb1>;
 342                         clock-indices = <0>, <1>,
 343                                         <2>, <4>,
 344                                         <5>, <6>,
 345                                         <7>, <16>,
 346                                         <17>, <18>,
 347                                         <19>, <20>,
 348                                         <21>, <22>,
 349                                         <23>;
 350                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 351                                              "apb1_i2c2", "apb1_can",
 352                                              "apb1_scr", "apb1_ps20",
 353                                              "apb1_ps21", "apb1_uart0",
 354                                              "apb1_uart1", "apb1_uart2",
 355                                              "apb1_uart3", "apb1_uart4",
 356                                              "apb1_uart5", "apb1_uart6",
 357                                              "apb1_uart7";
 358                 };
 359
 360                 nand_clk: clk@01c20080 {
 361                         #clock-cells = <0>;
 362                         compatible = "allwinner,sun4i-a10-mod0-clk";
 363                         reg = <0x01c20080 0x4>;
 364                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 365                         clock-output-names = "nand";
 366                 };
 367
 368                 ms_clk: clk@01c20084 {
 369                         #clock-cells = <0>;
 370                         compatible = "allwinner,sun4i-a10-mod0-clk";
 371                         reg = <0x01c20084 0x4>;
 372                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 373                         clock-output-names = "ms";
 374                 };
 375
 376                 mmc0_clk: clk@01c20088 {
 377                         #clock-cells = <1>;
 378                         compatible = "allwinner,sun4i-a10-mmc-clk";
 379                         reg = <0x01c20088 0x4>;
 380                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 381                         clock-output-names = "mmc0",
 382                                              "mmc0_output",
 383                                              "mmc0_sample";
 384                 };
 385
 386                 mmc1_clk: clk@01c2008c {
 387                         #clock-cells = <1>;
 388                         compatible = "allwinner,sun4i-a10-mmc-clk";
 389                         reg = <0x01c2008c 0x4>;
 390                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 391                         clock-output-names = "mmc1",
 392                                              "mmc1_output",
 393                                              "mmc1_sample";
 394                 };
 395
 396                 mmc2_clk: clk@01c20090 {
 397                         #clock-cells = <1>;
 398                         compatible = "allwinner,sun4i-a10-mmc-clk";
 399                         reg = <0x01c20090 0x4>;
 400                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 401                         clock-output-names = "mmc2",
 402                                              "mmc2_output",
 403                                              "mmc2_sample";
 404                 };
 405
 406                 mmc3_clk: clk@01c20094 {
 407                         #clock-cells = <1>;
 408                         compatible = "allwinner,sun4i-a10-mmc-clk";
 409                         reg = <0x01c20094 0x4>;
 410                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 411                         clock-output-names = "mmc3",
 412                                              "mmc3_output",
 413                                              "mmc3_sample";
 414                 };
 415
 416                 ts_clk: clk@01c20098 {
 417                         #clock-cells = <0>;
 418                         compatible = "allwinner,sun4i-a10-mod0-clk";
 419                         reg = <0x01c20098 0x4>;
 420                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 421                         clock-output-names = "ts";
 422                 };
 423
 424                 ss_clk: clk@01c2009c {
 425                         #clock-cells = <0>;
 426                         compatible = "allwinner,sun4i-a10-mod0-clk";
 427                         reg = <0x01c2009c 0x4>;
 428                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 429                         clock-output-names = "ss";
 430                 };
 431
 432                 spi0_clk: clk@01c200a0 {
 433                         #clock-cells = <0>;
 434                         compatible = "allwinner,sun4i-a10-mod0-clk";
 435                         reg = <0x01c200a0 0x4>;
 436                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 437                         clock-output-names = "spi0";
 438                 };
 439
 440                 spi1_clk: clk@01c200a4 {
 441                         #clock-cells = <0>;
 442                         compatible = "allwinner,sun4i-a10-mod0-clk";
 443                         reg = <0x01c200a4 0x4>;
 444                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 445                         clock-output-names = "spi1";
 446                 };
 447
 448                 spi2_clk: clk@01c200a8 {
 449                         #clock-cells = <0>;
 450                         compatible = "allwinner,sun4i-a10-mod0-clk";
 451                         reg = <0x01c200a8 0x4>;
 452                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 453                         clock-output-names = "spi2";
 454                 };
 455
 456                 pata_clk: clk@01c200ac {
 457                         #clock-cells = <0>;
 458                         compatible = "allwinner,sun4i-a10-mod0-clk";
 459                         reg = <0x01c200ac 0x4>;
 460                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 461                         clock-output-names = "pata";
 462                 };
 463
 464                 ir0_clk: clk@01c200b0 {
 465                         #clock-cells = <0>;
 466                         compatible = "allwinner,sun4i-a10-mod0-clk";
 467                         reg = <0x01c200b0 0x4>;
 468                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 469                         clock-output-names = "ir0";
 470                 };
 471
 472                 ir1_clk: clk@01c200b4 {
 473                         #clock-cells = <0>;
 474                         compatible = "allwinner,sun4i-a10-mod0-clk";
 475                         reg = <0x01c200b4 0x4>;
 476                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 477                         clock-output-names = "ir1";
 478                 };
 479
 480                 usb_clk: clk@01c200cc {
 481                         #clock-cells = <1>;
 482                         #reset-cells = <1>;
 483                         compatible = "allwinner,sun4i-a10-usb-clk";
 484                         reg = <0x01c200cc 0x4>;
 485                         clocks = <&pll6 1>;
 486                         clock-output-names = "usb_ohci0", "usb_ohci1",
 487                                              "usb_phy";
 488                 };
 489
 490                 spi3_clk: clk@01c200d4 {
 491                         #clock-cells = <0>;
 492                         compatible = "allwinner,sun4i-a10-mod0-clk";
 493                         reg = <0x01c200d4 0x4>;
 494                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 495                         clock-output-names = "spi3";
 496                 };
 497
 498                 dram_gates: clk@01c20100 {
 499                         #clock-cells = <1>;
 500                         compatible = "allwinner,sun4i-a10-dram-gates-clk";
 501                         reg = <0x01c20100 0x4>;
 502                         clocks = <&pll5 0>;
 503                         clock-indices = <0>,
 504                                         <1>, <2>,
 505                                         <3>,
 506                                         <4>,
 507                                         <5>, <6>,
 508                                         <15>,
 509                                         <24>, <25>,
 510                                         <26>, <27>,
 511                                         <28>, <29>;
 512                         clock-output-names = "dram_ve",
 513                                              "dram_csi0", "dram_csi1",
 514                                              "dram_ts",
 515                                              "dram_tvd",
 516                                              "dram_tve0", "dram_tve1",
 517                                              "dram_output",
 518                                              "dram_de_fe1", "dram_de_fe0",
 519                                              "dram_de_be0", "dram_de_be1",
 520                                              "dram_de_mp", "dram_ace";
 521                 };
 522
 523                 ve_clk: clk@01c2013c {
 524                         #clock-cells = <0>;
 525                         #reset-cells = <0>;
 526                         compatible = "allwinner,sun4i-a10-ve-clk";
 527                         reg = <0x01c2013c 0x4>;
 528                         clocks = <&pll4>;
 529                         clock-output-names = "ve";
 530                 };
 531
 532                 codec_clk: clk@01c20140 {
 533                         #clock-cells = <0>;
 534                         compatible = "allwinner,sun4i-a10-codec-clk";
 535                         reg = <0x01c20140 0x4>;
 536                         clocks = <&pll2 SUN4I_A10_PLL2_1X>;
 537                         clock-output-names = "codec";
 538                 };
 539         };
 540
 541         soc@01c00000 {
 542                 compatible = "simple-bus";
 543                 #address-cells = <1>;
 544                 #size-cells = <1>;
 545                 ranges;
 546
 547                 sram-controller@01c00000 {
 548                         compatible = "allwinner,sun4i-a10-sram-controller";
 549                         reg = <0x01c00000 0x30>;
 550                         #address-cells = <1>;
 551                         #size-cells = <1>;
 552                         ranges;
 553
 554                         sram_a: sram@00000000 {
 555                                 compatible = "mmio-sram";
 556                                 reg = <0x00000000 0xc000>;
 557                                 #address-cells = <1>;
 558                                 #size-cells = <1>;
 559                                 ranges = <0 0x00000000 0xc000>;
 560
 561                                 emac_sram: sram-section@8000 {
 562                                         compatible = "allwinner,sun4i-a10-sram-a3-a4";
 563                                         reg = <0x8000 0x4000>;
 564                                         status = "disabled";
 565                                 };
 566                         };
 567
 568                         sram_d: sram@00010000 {
 569                                 compatible = "mmio-sram";
 570                                 reg = <0x00010000 0x1000>;
 571                                 #address-cells = <1>;
 572                                 #size-cells = <1>;
 573                                 ranges = <0 0x00010000 0x1000>;
 574
 575                                 otg_sram: sram-section@0000 {
 576                                         compatible = "allwinner,sun4i-a10-sram-d";
 577                                         reg = <0x0000 0x1000>;
 578                                         status = "disabled";
 579                                 };
 580                         };
 581                 };
 582
 583                 dma: dma-controller@01c02000 {
 584                         compatible = "allwinner,sun4i-a10-dma";
 585                         reg = <0x01c02000 0x1000>;
 586                         interrupts = <27>;
 587                         clocks = <&ahb_gates 6>;
 588                         #dma-cells = <2>;
 589                 };
 590
 591                 spi0: spi@01c05000 {
 592                         compatible = "allwinner,sun4i-a10-spi";
 593                         reg = <0x01c05000 0x1000>;
 594                         interrupts = <10>;
 595                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 596                         clock-names = "ahb", "mod";
 597                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 598                                <&dma SUN4I_DMA_DEDICATED 26>;
 599                         dma-names = "rx", "tx";
 600                         status = "disabled";
 601                         #address-cells = <1>;
 602                         #size-cells = <0>;
 603                 };
 604
 605                 spi1: spi@01c06000 {
 606                         compatible = "allwinner,sun4i-a10-spi";
 607                         reg = <0x01c06000 0x1000>;
 608                         interrupts = <11>;
 609                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 610                         clock-names = "ahb", "mod";
 611                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 612                                <&dma SUN4I_DMA_DEDICATED 8>;
 613                         dma-names = "rx", "tx";
 614                         status = "disabled";
 615                         #address-cells = <1>;
 616                         #size-cells = <0>;
 617                 };
 618
 619                 emac: ethernet@01c0b000 {
 620                         compatible = "allwinner,sun4i-a10-emac";
 621                         reg = <0x01c0b000 0x1000>;
 622                         interrupts = <55>;
 623                         clocks = <&ahb_gates 17>;
 624                         allwinner,sram = <&emac_sram 1>;
 625                         status = "disabled";
 626                 };
 627
 628                 mdio: mdio@01c0b080 {
 629                         compatible = "allwinner,sun4i-a10-mdio";
 630                         reg = <0x01c0b080 0x14>;
 631                         status = "disabled";
 632                         #address-cells = <1>;
 633                         #size-cells = <0>;
 634                 };
 635
 636                 mmc0: mmc@01c0f000 {
 637                         compatible = "allwinner,sun4i-a10-mmc";
 638                         reg = <0x01c0f000 0x1000>;
 639                         clocks = <&ahb_gates 8>,
 640                                  <&mmc0_clk 0>,
 641                                  <&mmc0_clk 1>,
 642                                  <&mmc0_clk 2>;
 643                         clock-names = "ahb",
 644                                       "mmc",
 645                                       "output",
 646                                       "sample";
 647                         interrupts = <32>;
 648                         status = "disabled";
 649                         #address-cells = <1>;
 650                         #size-cells = <0>;
 651                 };
 652
 653                 mmc1: mmc@01c10000 {
 654                         compatible = "allwinner,sun4i-a10-mmc";
 655                         reg = <0x01c10000 0x1000>;
 656                         clocks = <&ahb_gates 9>,
 657                                  <&mmc1_clk 0>,
 658                                  <&mmc1_clk 1>,
 659                                  <&mmc1_clk 2>;
 660                         clock-names = "ahb",
 661                                       "mmc",
 662                                       "output",
 663                                       "sample";
 664                         interrupts = <33>;
 665                         status = "disabled";
 666                         #address-cells = <1>;
 667                         #size-cells = <0>;
 668                 };
 669
 670                 mmc2: mmc@01c11000 {
 671                         compatible = "allwinner,sun4i-a10-mmc";
 672                         reg = <0x01c11000 0x1000>;
 673                         clocks = <&ahb_gates 10>,
 674                                  <&mmc2_clk 0>,
 675                                  <&mmc2_clk 1>,
 676                                  <&mmc2_clk 2>;
 677                         clock-names = "ahb",
 678                                       "mmc",
 679                                       "output",
 680                                       "sample";
 681                         interrupts = <34>;
 682                         status = "disabled";
 683                         #address-cells = <1>;
 684                         #size-cells = <0>;
 685                 };
 686
 687                 mmc3: mmc@01c12000 {
 688                         compatible = "allwinner,sun4i-a10-mmc";
 689                         reg = <0x01c12000 0x1000>;
 690                         clocks = <&ahb_gates 11>,
 691                                  <&mmc3_clk 0>,
 692                                  <&mmc3_clk 1>,
 693                                  <&mmc3_clk 2>;
 694                         clock-names = "ahb",
 695                                       "mmc",
 696                                       "output",
 697                                       "sample";
 698                         interrupts = <35>;
 699                         status = "disabled";
 700                         #address-cells = <1>;
 701                         #size-cells = <0>;
 702                 };
 703
 704                 usb_otg: usb@01c13000 {
 705                         compatible = "allwinner,sun4i-a10-musb";
 706                         reg = <0x01c13000 0x0400>;
 707                         clocks = <&ahb_gates 0>;
 708                         interrupts = <38>;
 709                         interrupt-names = "mc";
 710                         phys = <&usbphy 0>;
 711                         phy-names = "usb";
 712                         extcon = <&usbphy 0>;
 713                         allwinner,sram = <&otg_sram 1>;
 714                         status = "disabled";
 715                 };
 716
 717                 usbphy: phy@01c13400 {
 718                         #phy-cells = <1>;
 719                         compatible = "allwinner,sun4i-a10-usb-phy";
 720                         reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
 721                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 722                         clocks = <&usb_clk 8>;
 723                         clock-names = "usb_phy";
 724                         resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
 725                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 726                         status = "disabled";
 727                 };
 728
 729                 ehci0: usb@01c14000 {
 730                         compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
 731                         reg = <0x01c14000 0x100>;
 732                         interrupts = <39>;
 733                         clocks = <&ahb_gates 1>;
 734                         phys = <&usbphy 1>;
 735                         phy-names = "usb";
 736                         status = "disabled";
 737                 };
 738
 739                 ohci0: usb@01c14400 {
 740                         compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
 741                         reg = <0x01c14400 0x100>;
 742                         interrupts = <64>;
 743                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 744                         phys = <&usbphy 1>;
 745                         phy-names = "usb";
 746                         status = "disabled";
 747                 };
 748
 749                 crypto: crypto-engine@01c15000 {
 750                         compatible = "allwinner,sun4i-a10-crypto";
 751                         reg = <0x01c15000 0x1000>;
 752                         interrupts = <86>;
 753                         clocks = <&ahb_gates 5>, <&ss_clk>;
 754                         clock-names = "ahb", "mod";
 755                 };
 756
 757                 spi2: spi@01c17000 {
 758                         compatible = "allwinner,sun4i-a10-spi";
 759                         reg = <0x01c17000 0x1000>;
 760                         interrupts = <12>;
 761                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 762                         clock-names = "ahb", "mod";
 763                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 764                                <&dma SUN4I_DMA_DEDICATED 28>;
 765                         dma-names = "rx", "tx";
 766                         status = "disabled";
 767                         #address-cells = <1>;
 768                         #size-cells = <0>;
 769                 };
 770
 771                 ahci: sata@01c18000 {
 772                         compatible = "allwinner,sun4i-a10-ahci";
 773                         reg = <0x01c18000 0x1000>;
 774                         interrupts = <56>;
 775                         clocks = <&pll6 0>, <&ahb_gates 25>;
 776                         status = "disabled";
 777                 };
 778
 779                 ehci1: usb@01c1c000 {
 780                         compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
 781                         reg = <0x01c1c000 0x100>;
 782                         interrupts = <40>;
 783                         clocks = <&ahb_gates 3>;
 784                         phys = <&usbphy 2>;
 785                         phy-names = "usb";
 786                         status = "disabled";
 787                 };
 788
 789                 ohci1: usb@01c1c400 {
 790                         compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
 791                         reg = <0x01c1c400 0x100>;
 792                         interrupts = <65>;
 793                         clocks = <&usb_clk 7>, <&ahb_gates 4>;
 794                         phys = <&usbphy 2>;
 795                         phy-names = "usb";
 796                         status = "disabled";
 797                 };
 798
 799                 spi3: spi@01c1f000 {
 800                         compatible = "allwinner,sun4i-a10-spi";
 801                         reg = <0x01c1f000 0x1000>;
 802                         interrupts = <50>;
 803                         clocks = <&ahb_gates 23>, <&spi3_clk>;
 804                         clock-names = "ahb", "mod";
 805                         dmas = <&dma SUN4I_DMA_DEDICATED 31>,
 806                                <&dma SUN4I_DMA_DEDICATED 30>;
 807                         dma-names = "rx", "tx";
 808                         status = "disabled";
 809                         #address-cells = <1>;
 810                         #size-cells = <0>;
 811                 };
 812
 813                 intc: interrupt-controller@01c20400 {
 814                         compatible = "allwinner,sun4i-a10-ic";
 815                         reg = <0x01c20400 0x400>;
 816                         interrupt-controller;
 817                         #interrupt-cells = <1>;
 818                 };
 819
 820                 pio: pinctrl@01c20800 {
 821                         compatible = "allwinner,sun4i-a10-pinctrl";
 822                         reg = <0x01c20800 0x400>;
 823                         interrupts = <28>;
 824                         clocks = <&apb0_gates 5>;
 825                         gpio-controller;
 826                         interrupt-controller;
 827                         #interrupt-cells = <3>;
 828                         #gpio-cells = <3>;
 829
 830                         pwm0_pins_a: pwm0@0 {
 831                                 allwinner,pins = "PB2";
 832                                 allwinner,function = "pwm";
 833                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 834                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 835                         };
 836
 837                         pwm1_pins_a: pwm1@0 {
 838                                 allwinner,pins = "PI3";
 839                                 allwinner,function = "pwm";
 840                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 841                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 842                         };
 843
 844                         uart0_pins_a: uart0@0 {
 845                                 allwinner,pins = "PB22", "PB23";
 846                                 allwinner,function = "uart0";
 847                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 848                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 849                         };
 850
 851                         uart0_pins_b: uart0@1 {
 852                                 allwinner,pins = "PF2", "PF4";
 853                                 allwinner,function = "uart0";
 854                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 855                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 856                         };
 857
 858                         uart1_pins_a: uart1@0 {
 859                                 allwinner,pins = "PA10", "PA11";
 860                                 allwinner,function = "uart1";
 861                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 862                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 863                         };
 864
 865                         i2c0_pins_a: i2c0@0 {
 866                                 allwinner,pins = "PB0", "PB1";
 867                                 allwinner,function = "i2c0";
 868                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 869                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 870                         };
 871
 872                         i2c1_pins_a: i2c1@0 {
 873                                 allwinner,pins = "PB18", "PB19";
 874                                 allwinner,function = "i2c1";
 875                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 876                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 877                         };
 878
 879                         i2c2_pins_a: i2c2@0 {
 880                                 allwinner,pins = "PB20", "PB21";
 881                                 allwinner,function = "i2c2";
 882                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 883                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 884                         };
 885
 886                         emac_pins_a: emac0@0 {
 887                                 allwinner,pins = "PA0", "PA1", "PA2",
 888                                                 "PA3", "PA4", "PA5", "PA6",
 889                                                 "PA7", "PA8", "PA9", "PA10",
 890                                                 "PA11", "PA12", "PA13", "PA14",
 891                                                 "PA15", "PA16";
 892                                 allwinner,function = "emac";
 893                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 894                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 895                         };
 896
 897                         mmc0_pins_a: mmc0@0 {
 898                                 allwinner,pins = "PF0", "PF1", "PF2",
 899                                                  "PF3", "PF4", "PF5";
 900                                 allwinner,function = "mmc0";
 901                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 902                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 903                         };
 904
 905                         mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
 906                                 allwinner,pins = "PH1";
 907                                 allwinner,function = "gpio_in";
 908                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 909                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 910                         };
 911
 912                         ir0_rx_pins_a: ir0@0 {
 913                                 allwinner,pins = "PB4";
 914                                 allwinner,function = "ir0";
 915                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 916                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 917                         };
 918
 919                         ir0_tx_pins_a: ir0@1 {
 920                                 allwinner,pins = "PB3";
 921                                 allwinner,function = "ir0";
 922                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 923                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 924                         };
 925
 926                         ir1_rx_pins_a: ir1@0 {
 927                                 allwinner,pins = "PB23";
 928                                 allwinner,function = "ir1";
 929                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 930                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 931                         };
 932
 933                         ir1_tx_pins_a: ir1@1 {
 934                                 allwinner,pins = "PB22";
 935                                 allwinner,function = "ir1";
 936                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 937                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 938                         };
 939
 940                         spi0_pins_a: spi0@0 {
 941                                 allwinner,pins = "PI11", "PI12", "PI13";
 942                                 allwinner,function = "spi0";
 943                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 944                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 945                         };
 946
 947                         spi0_cs0_pins_a: spi0_cs0@0 {
 948                                 allwinner,pins = "PI10";
 949                                 allwinner,function = "spi0";
 950                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 951                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 952                         };
 953
 954                         spi1_pins_a: spi1@0 {
 955                                 allwinner,pins = "PI17", "PI18", "PI19";
 956                                 allwinner,function = "spi1";
 957                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 958                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 959                         };
 960
 961                         spi1_cs0_pins_a: spi1_cs0@0 {
 962                                 allwinner,pins = "PI16";
 963                                 allwinner,function = "spi1";
 964                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 965                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 966                         };
 967
 968                         spi2_pins_a: spi2@0 {
 969                                 allwinner,pins = "PC20", "PC21", "PC22";
 970                                 allwinner,function = "spi2";
 971                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 972                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 973                         };
 974
 975                         spi2_pins_b: spi2@1 {
 976                                 allwinner,pins = "PB15", "PB16", "PB17";
 977                                 allwinner,function = "spi2";
 978                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 979                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 980                         };
 981
 982                         spi2_cs0_pins_a: spi2_cs0@0 {
 983                                 allwinner,pins = "PC19";
 984                                 allwinner,function = "spi2";
 985                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 986                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 987                         };
 988
 989                         spi2_cs0_pins_b: spi2_cs0@1 {
 990                                 allwinner,pins = "PB14";
 991                                 allwinner,function = "spi2";
 992                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 993                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 994                         };
 995
 996                         ps20_pins_a: ps20@0 {
 997                                 allwinner,pins = "PI20", "PI21";
 998                                 allwinner,function = "ps2";
 999                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1000                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1001                         };
1002
1003                         ps21_pins_a: ps21@0 {
1004                                 allwinner,pins = "PH12", "PH13";
1005                                 allwinner,function = "ps2";
1006                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1007                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1008                         };
1009                 };
1010
1011                 timer@01c20c00 {
1012                         compatible = "allwinner,sun4i-a10-timer";
1013                         reg = <0x01c20c00 0x90>;
1014                         interrupts = <22>;
1015                         clocks = <&osc24M>;
1016                 };
1017
1018                 wdt: watchdog@01c20c90 {
1019                         compatible = "allwinner,sun4i-a10-wdt";
1020                         reg = <0x01c20c90 0x10>;
1021                 };
1022
1023                 rtc: rtc@01c20d00 {
1024                         compatible = "allwinner,sun4i-a10-rtc";
1025                         reg = <0x01c20d00 0x20>;
1026                         interrupts = <24>;
1027                 };
1028
1029                 pwm: pwm@01c20e00 {
1030                         compatible = "allwinner,sun4i-a10-pwm";
1031                         reg = <0x01c20e00 0xc>;
1032                         clocks = <&osc24M>;
1033                         #pwm-cells = <3>;
1034                         status = "disabled";
1035                 };
1036
1037                 ir0: ir@01c21800 {
1038                         compatible = "allwinner,sun4i-a10-ir";
1039                         clocks = <&apb0_gates 6>, <&ir0_clk>;
1040                         clock-names = "apb", "ir";
1041                         interrupts = <5>;
1042                         reg = <0x01c21800 0x40>;
1043                         status = "disabled";
1044                 };
1045
1046                 ir1: ir@01c21c00 {
1047                         compatible = "allwinner,sun4i-a10-ir";
1048                         clocks = <&apb0_gates 7>, <&ir1_clk>;
1049                         clock-names = "apb", "ir";
1050                         interrupts = <6>;
1051                         reg = <0x01c21c00 0x40>;
1052                         status = "disabled";
1053                 };
1054
1055                 lradc: lradc@01c22800 {
1056                         compatible = "allwinner,sun4i-a10-lradc-keys";
1057                         reg = <0x01c22800 0x100>;
1058                         interrupts = <31>;
1059                         status = "disabled";
1060                 };
1061
1062                 codec: codec@01c22c00 {
1063                         #sound-dai-cells = <0>;
1064                         compatible = "allwinner,sun4i-a10-codec";
1065                         reg = <0x01c22c00 0x40>;
1066                         interrupts = <30>;
1067                         clocks = <&apb0_gates 0>, <&codec_clk>;
1068                         clock-names = "apb", "codec";
1069                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
1070                                <&dma SUN4I_DMA_NORMAL 19>;
1071                         dma-names = "rx", "tx";
1072                         status = "disabled";
1073                 };
1074
1075                 sid: eeprom@01c23800 {
1076                         compatible = "allwinner,sun4i-a10-sid";
1077                         reg = <0x01c23800 0x10>;
1078                 };
1079
1080                 rtp: rtp@01c25000 {
1081                         compatible = "allwinner,sun4i-a10-ts";
1082                         reg = <0x01c25000 0x100>;
1083                         interrupts = <29>;
1084                         #thermal-sensor-cells = <0>;
1085                 };
1086
1087                 uart0: serial@01c28000 {
1088                         compatible = "snps,dw-apb-uart";
1089                         reg = <0x01c28000 0x400>;
1090                         interrupts = <1>;
1091                         reg-shift = <2>;
1092                         reg-io-width = <4>;
1093                         clocks = <&apb1_gates 16>;
1094                         status = "disabled";
1095                 };
1096
1097                 uart1: serial@01c28400 {
1098                         compatible = "snps,dw-apb-uart";
1099                         reg = <0x01c28400 0x400>;
1100                         interrupts = <2>;
1101                         reg-shift = <2>;
1102                         reg-io-width = <4>;
1103                         clocks = <&apb1_gates 17>;
1104                         status = "disabled";
1105                 };
1106
1107                 uart2: serial@01c28800 {
1108                         compatible = "snps,dw-apb-uart";
1109                         reg = <0x01c28800 0x400>;
1110                         interrupts = <3>;
1111                         reg-shift = <2>;
1112                         reg-io-width = <4>;
1113                         clocks = <&apb1_gates 18>;
1114                         status = "disabled";
1115                 };
1116
1117                 uart3: serial@01c28c00 {
1118                         compatible = "snps,dw-apb-uart";
1119                         reg = <0x01c28c00 0x400>;
1120                         interrupts = <4>;
1121                         reg-shift = <2>;
1122                         reg-io-width = <4>;
1123                         clocks = <&apb1_gates 19>;
1124                         status = "disabled";
1125                 };
1126
1127                 uart4: serial@01c29000 {
1128                         compatible = "snps,dw-apb-uart";
1129                         reg = <0x01c29000 0x400>;
1130                         interrupts = <17>;
1131                         reg-shift = <2>;
1132                         reg-io-width = <4>;
1133                         clocks = <&apb1_gates 20>;
1134                         status = "disabled";
1135                 };
1136
1137                 uart5: serial@01c29400 {
1138                         compatible = "snps,dw-apb-uart";
1139                         reg = <0x01c29400 0x400>;
1140                         interrupts = <18>;
1141                         reg-shift = <2>;
1142                         reg-io-width = <4>;
1143                         clocks = <&apb1_gates 21>;
1144                         status = "disabled";
1145                 };
1146
1147                 uart6: serial@01c29800 {
1148                         compatible = "snps,dw-apb-uart";
1149                         reg = <0x01c29800 0x400>;
1150                         interrupts = <19>;
1151                         reg-shift = <2>;
1152                         reg-io-width = <4>;
1153                         clocks = <&apb1_gates 22>;
1154                         status = "disabled";
1155                 };
1156
1157                 uart7: serial@01c29c00 {
1158                         compatible = "snps,dw-apb-uart";
1159                         reg = <0x01c29c00 0x400>;
1160                         interrupts = <20>;
1161                         reg-shift = <2>;
1162                         reg-io-width = <4>;
1163                         clocks = <&apb1_gates 23>;
1164                         status = "disabled";
1165                 };
1166
1167                 i2c0: i2c@01c2ac00 {
1168                         compatible = "allwinner,sun4i-a10-i2c";
1169                         reg = <0x01c2ac00 0x400>;
1170                         interrupts = <7>;
1171                         clocks = <&apb1_gates 0>;
1172                         status = "disabled";
1173                         #address-cells = <1>;
1174                         #size-cells = <0>;
1175                 };
1176
1177                 i2c1: i2c@01c2b000 {
1178                         compatible = "allwinner,sun4i-a10-i2c";
1179                         reg = <0x01c2b000 0x400>;
1180                         interrupts = <8>;
1181                         clocks = <&apb1_gates 1>;
1182                         status = "disabled";
1183                         #address-cells = <1>;
1184                         #size-cells = <0>;
1185                 };
1186
1187                 i2c2: i2c@01c2b400 {
1188                         compatible = "allwinner,sun4i-a10-i2c";
1189                         reg = <0x01c2b400 0x400>;
1190                         interrupts = <9>;
1191                         clocks = <&apb1_gates 2>;
1192                         status = "disabled";
1193                         #address-cells = <1>;
1194                         #size-cells = <0>;
1195                 };
1196
1197                 ps20: ps2@01c2a000 {
1198                         compatible = "allwinner,sun4i-a10-ps2";
1199                         reg = <0x01c2a000 0x400>;
1200                         interrupts = <62>;
1201                         clocks = <&apb1_gates 6>;
1202                         status = "disabled";
1203                 };
1204
1205                 ps21: ps2@01c2a400 {
1206                         compatible = "allwinner,sun4i-a10-ps2";
1207                         reg = <0x01c2a400 0x400>;
1208                         interrupts = <63>;
1209                         clocks = <&apb1_gates 7>;
1210                         status = "disabled";
1211                 };
1212         };
1213 };