2 * Copyright (C) 2016 ARM Ltd.
3 * based on the Allwinner H3 dtsi:
4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/clock/sun50i-a64-ccu.h>
46 #include <dt-bindings/clock/sun8i-r-ccu.h>
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/reset/sun50i-a64-ccu.h>
51 interrupt-parent = <&gic>;
61 * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU.
62 * However there is no support for this clock on A64 yet, so we depend
63 * on the upstream clocks here to keep them (and thus CLK_MIXER0) up.
65 simplefb_lcd: framebuffer-lcd {
66 compatible = "allwinner,simple-framebuffer",
68 allwinner,pipeline = "mixer0-lcd0";
69 clocks = <&ccu CLK_TCON0>,
70 <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
80 compatible = "arm,cortex-a53", "arm,armv8";
83 enable-method = "psci";
87 compatible = "arm,cortex-a53", "arm,armv8";
90 enable-method = "psci";
94 compatible = "arm,cortex-a53", "arm,armv8";
97 enable-method = "psci";
101 compatible = "arm,cortex-a53", "arm,armv8";
104 enable-method = "psci";
110 compatible = "fixed-clock";
111 clock-frequency = <24000000>;
112 clock-output-names = "osc24M";
117 compatible = "fixed-clock";
118 clock-frequency = <32768>;
119 clock-output-names = "osc32k";
122 iosc: internal-osc-clk {
124 compatible = "fixed-clock";
125 clock-frequency = <16000000>;
126 clock-accuracy = <300000000>;
127 clock-output-names = "iosc";
131 compatible = "arm,psci-0.2";
136 compatible = "simple-audio-card";
137 simple-audio-card,name = "On-board SPDIF";
139 simple-audio-card,cpu {
140 sound-dai = <&spdif>;
143 simple-audio-card,codec {
144 sound-dai = <&spdif_out>;
148 spdif_out: spdif-out {
149 #sound-dai-cells = <0>;
150 compatible = "linux,spdif-dit";
154 compatible = "arm,armv8-timer";
155 interrupts = <GIC_PPI 13
156 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
158 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
160 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
162 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
166 compatible = "simple-bus";
167 #address-cells = <1>;
171 syscon: syscon@1c00000 {
172 compatible = "allwinner,sun50i-a64-system-controller",
174 reg = <0x01c00000 0x1000>;
177 dma: dma-controller@1c02000 {
178 compatible = "allwinner,sun50i-a64-dma";
179 reg = <0x01c02000 0x1000>;
180 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&ccu CLK_BUS_DMA>;
184 resets = <&ccu RST_BUS_DMA>;
189 compatible = "allwinner,sun50i-a64-mmc";
190 reg = <0x01c0f000 0x1000>;
191 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
192 clock-names = "ahb", "mmc";
193 resets = <&ccu RST_BUS_MMC0>;
195 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
196 max-frequency = <150000000>;
198 #address-cells = <1>;
203 compatible = "allwinner,sun50i-a64-mmc";
204 reg = <0x01c10000 0x1000>;
205 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
206 clock-names = "ahb", "mmc";
207 resets = <&ccu RST_BUS_MMC1>;
209 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
210 max-frequency = <150000000>;
212 #address-cells = <1>;
217 compatible = "allwinner,sun50i-a64-emmc";
218 reg = <0x01c11000 0x1000>;
219 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
220 clock-names = "ahb", "mmc";
221 resets = <&ccu RST_BUS_MMC2>;
223 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
224 max-frequency = <200000000>;
226 #address-cells = <1>;
230 usb_otg: usb@1c19000 {
231 compatible = "allwinner,sun8i-a33-musb";
232 reg = <0x01c19000 0x0400>;
233 clocks = <&ccu CLK_BUS_OTG>;
234 resets = <&ccu RST_BUS_OTG>;
235 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
236 interrupt-names = "mc";
239 extcon = <&usbphy 0>;
243 usbphy: phy@1c19400 {
244 compatible = "allwinner,sun50i-a64-usb-phy";
245 reg = <0x01c19400 0x14>,
248 reg-names = "phy_ctrl",
251 clocks = <&ccu CLK_USB_PHY0>,
253 clock-names = "usb0_phy",
255 resets = <&ccu RST_USB_PHY0>,
257 reset-names = "usb0_reset",
264 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
265 reg = <0x01c1a000 0x100>;
266 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&ccu CLK_BUS_OHCI0>,
268 <&ccu CLK_BUS_EHCI0>,
269 <&ccu CLK_USB_OHCI0>;
270 resets = <&ccu RST_BUS_OHCI0>,
271 <&ccu RST_BUS_EHCI0>;
276 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
277 reg = <0x01c1a400 0x100>;
278 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&ccu CLK_BUS_OHCI0>,
280 <&ccu CLK_USB_OHCI0>;
281 resets = <&ccu RST_BUS_OHCI0>;
286 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
287 reg = <0x01c1b000 0x100>;
288 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&ccu CLK_BUS_OHCI1>,
290 <&ccu CLK_BUS_EHCI1>,
291 <&ccu CLK_USB_OHCI1>;
292 resets = <&ccu RST_BUS_OHCI1>,
293 <&ccu RST_BUS_EHCI1>;
300 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
301 reg = <0x01c1b400 0x100>;
302 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&ccu CLK_BUS_OHCI1>,
304 <&ccu CLK_USB_OHCI1>;
305 resets = <&ccu RST_BUS_OHCI1>;
312 compatible = "allwinner,sun50i-a64-ccu";
313 reg = <0x01c20000 0x400>;
314 clocks = <&osc24M>, <&osc32k>;
315 clock-names = "hosc", "losc";
320 pio: pinctrl@1c20800 {
321 compatible = "allwinner,sun50i-a64-pinctrl";
322 reg = <0x01c20800 0x400>;
323 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
329 interrupt-controller;
330 #interrupt-cells = <3>;
332 i2c0_pins: i2c0_pins {
337 i2c1_pins: i2c1_pins {
342 mmc0_pins: mmc0-pins {
343 pins = "PF0", "PF1", "PF2", "PF3",
346 drive-strength = <30>;
350 mmc1_pins: mmc1-pins {
351 pins = "PG0", "PG1", "PG2", "PG3",
354 drive-strength = <30>;
358 mmc2_pins: mmc2-pins {
359 pins = "PC1", "PC5", "PC6", "PC8", "PC9",
360 "PC10","PC11", "PC12", "PC13",
361 "PC14", "PC15", "PC16";
363 drive-strength = <30>;
367 rmii_pins: rmii_pins {
368 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
369 "PD18", "PD19", "PD20", "PD22", "PD23";
371 drive-strength = <40>;
374 rgmii_pins: rgmii_pins {
375 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
376 "PD13", "PD15", "PD16", "PD17", "PD18",
377 "PD19", "PD20", "PD21", "PD22", "PD23";
379 drive-strength = <40>;
382 spdif_tx_pin: spdif {
388 pins = "PC0", "PC1", "PC2", "PC3";
393 pins = "PD0", "PD1", "PD2", "PD3";
397 uart0_pins_a: uart0 {
402 uart1_pins: uart1_pins {
407 uart1_rts_cts_pins: uart1_rts_cts_pins {
412 uart2_pins: uart2-pins {
417 uart3_pins: uart3-pins {
422 uart4_pins: uart4-pins {
427 uart4_rts_cts_pins: uart4-rts-cts-pins {
433 spdif: spdif@1c21000 {
434 #sound-dai-cells = <0>;
435 compatible = "allwinner,sun50i-a64-spdif",
436 "allwinner,sun8i-h3-spdif";
437 reg = <0x01c21000 0x400>;
438 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
440 resets = <&ccu RST_BUS_SPDIF>;
441 clock-names = "apb", "spdif";
444 pinctrl-names = "default";
445 pinctrl-0 = <&spdif_tx_pin>;
450 #sound-dai-cells = <0>;
451 compatible = "allwinner,sun50i-a64-i2s",
452 "allwinner,sun8i-h3-i2s";
453 reg = <0x01c22000 0x400>;
454 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
456 clock-names = "apb", "mod";
457 resets = <&ccu RST_BUS_I2S0>;
458 dma-names = "rx", "tx";
459 dmas = <&dma 3>, <&dma 3>;
464 #sound-dai-cells = <0>;
465 compatible = "allwinner,sun50i-a64-i2s",
466 "allwinner,sun8i-h3-i2s";
467 reg = <0x01c22400 0x400>;
468 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
470 clock-names = "apb", "mod";
471 resets = <&ccu RST_BUS_I2S1>;
472 dma-names = "rx", "tx";
473 dmas = <&dma 4>, <&dma 4>;
478 compatible = "allwinner,sun50i-a64-pwm",
479 "allwinner,sun5i-a13-pwm";
480 reg = <0x01c21400 0x8>;
486 uart0: serial@1c28000 {
487 compatible = "snps,dw-apb-uart";
488 reg = <0x01c28000 0x400>;
489 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&ccu CLK_BUS_UART0>;
493 resets = <&ccu RST_BUS_UART0>;
497 uart1: serial@1c28400 {
498 compatible = "snps,dw-apb-uart";
499 reg = <0x01c28400 0x400>;
500 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&ccu CLK_BUS_UART1>;
504 resets = <&ccu RST_BUS_UART1>;
508 uart2: serial@1c28800 {
509 compatible = "snps,dw-apb-uart";
510 reg = <0x01c28800 0x400>;
511 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&ccu CLK_BUS_UART2>;
515 resets = <&ccu RST_BUS_UART2>;
519 uart3: serial@1c28c00 {
520 compatible = "snps,dw-apb-uart";
521 reg = <0x01c28c00 0x400>;
522 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&ccu CLK_BUS_UART3>;
526 resets = <&ccu RST_BUS_UART3>;
530 uart4: serial@1c29000 {
531 compatible = "snps,dw-apb-uart";
532 reg = <0x01c29000 0x400>;
533 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&ccu CLK_BUS_UART4>;
537 resets = <&ccu RST_BUS_UART4>;
542 compatible = "allwinner,sun6i-a31-i2c";
543 reg = <0x01c2ac00 0x400>;
544 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&ccu CLK_BUS_I2C0>;
546 resets = <&ccu RST_BUS_I2C0>;
548 #address-cells = <1>;
553 compatible = "allwinner,sun6i-a31-i2c";
554 reg = <0x01c2b000 0x400>;
555 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&ccu CLK_BUS_I2C1>;
557 resets = <&ccu RST_BUS_I2C1>;
559 #address-cells = <1>;
564 compatible = "allwinner,sun6i-a31-i2c";
565 reg = <0x01c2b400 0x400>;
566 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&ccu CLK_BUS_I2C2>;
568 resets = <&ccu RST_BUS_I2C2>;
570 #address-cells = <1>;
576 compatible = "allwinner,sun8i-h3-spi";
577 reg = <0x01c68000 0x1000>;
578 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
580 clock-names = "ahb", "mod";
581 dmas = <&dma 23>, <&dma 23>;
582 dma-names = "rx", "tx";
583 pinctrl-names = "default";
584 pinctrl-0 = <&spi0_pins>;
585 resets = <&ccu RST_BUS_SPI0>;
588 #address-cells = <1>;
593 compatible = "allwinner,sun8i-h3-spi";
594 reg = <0x01c69000 0x1000>;
595 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
597 clock-names = "ahb", "mod";
598 dmas = <&dma 24>, <&dma 24>;
599 dma-names = "rx", "tx";
600 pinctrl-names = "default";
601 pinctrl-0 = <&spi1_pins>;
602 resets = <&ccu RST_BUS_SPI1>;
605 #address-cells = <1>;
609 emac: ethernet@1c30000 {
610 compatible = "allwinner,sun50i-a64-emac";
612 reg = <0x01c30000 0x10000>;
613 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
614 interrupt-names = "macirq";
615 resets = <&ccu RST_BUS_EMAC>;
616 reset-names = "stmmaceth";
617 clocks = <&ccu CLK_BUS_EMAC>;
618 clock-names = "stmmaceth";
620 #address-cells = <1>;
624 compatible = "snps,dwmac-mdio";
625 #address-cells = <1>;
630 gic: interrupt-controller@1c81000 {
631 compatible = "arm,gic-400";
632 reg = <0x01c81000 0x1000>,
636 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
637 interrupt-controller;
638 #interrupt-cells = <3>;
642 compatible = "allwinner,sun6i-a31-rtc";
643 reg = <0x01f00000 0x54>;
644 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
648 r_intc: interrupt-controller@1f00c00 {
649 compatible = "allwinner,sun50i-a64-r-intc",
650 "allwinner,sun6i-a31-r-intc";
651 interrupt-controller;
652 #interrupt-cells = <2>;
653 reg = <0x01f00c00 0x400>;
654 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
657 r_ccu: clock@1f01400 {
658 compatible = "allwinner,sun50i-a64-r-ccu";
659 reg = <0x01f01400 0x100>;
660 clocks = <&osc24M>, <&osc32k>, <&iosc>,
662 clock-names = "hosc", "losc", "iosc", "pll-periph";
667 r_pio: pinctrl@1f02c00 {
668 compatible = "allwinner,sun50i-a64-r-pinctrl";
669 reg = <0x01f02c00 0x400>;
670 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
672 clock-names = "apb", "hosc", "losc";
675 interrupt-controller;
676 #interrupt-cells = <3>;
685 compatible = "allwinner,sun8i-a23-rsb";
686 reg = <0x01f03400 0x400>;
687 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
689 clock-frequency = <3000000>;
691 pinctrl-names = "default";
692 pinctrl-0 = <&r_rsb_pins>;
694 #address-cells = <1>;
698 wdt0: watchdog@1c20ca0 {
699 compatible = "allwinner,sun50i-a64-wdt",
700 "allwinner,sun6i-a31-wdt";
701 reg = <0x01c20ca0 0x20>;
702 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;