git.sur5r.net Git - u-boot/blob - arch/arm/dts/sun7i-a20.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48 #include <dt-bindings/thermal/thermal.h>
  49
  50 #include <dt-bindings/clock/sun4i-a10-pll2.h>
  51 #include <dt-bindings/dma/sun4i-a10.h>
  52 #include <dt-bindings/pinctrl/sun4i-a10.h>
  53
  54 / {
  55         interrupt-parent = <&gic>;
  56
  57         aliases {
  58                 ethernet0 = &gmac;
  59         };
  60
  61         chosen {
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 ranges;
  65
  66                 framebuffer@0 {
  67                         compatible = "allwinner,simple-framebuffer",
  68                                      "simple-framebuffer";
  69                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  70                         clocks = <&ahb_gates 36>, <&ahb_gates 43>,
  71                                  <&ahb_gates 44>, <&de_be0_clk>,
  72                                  <&tcon0_ch1_clk>, <&dram_gates 26>;
  73                         status = "disabled";
  74                 };
  75
  76                 framebuffer@1 {
  77                         compatible = "allwinner,simple-framebuffer",
  78                                      "simple-framebuffer";
  79                         allwinner,pipeline = "de_be0-lcd0";
  80                         clocks = <&ahb_gates 36>, <&ahb_gates 44>,
  81                                  <&de_be0_clk>, <&tcon0_ch0_clk>,
  82                                  <&dram_gates 26>;
  83                         status = "disabled";
  84                 };
  85
  86                 framebuffer@2 {
  87                         compatible = "allwinner,simple-framebuffer",
  88                                      "simple-framebuffer";
  89                         allwinner,pipeline = "de_be0-lcd0-tve0";
  90                         clocks = <&ahb_gates 34>, <&ahb_gates 36>,
  91                                  <&ahb_gates 44>,
  92                                  <&de_be0_clk>, <&tcon0_ch1_clk>,
  93                                  <&dram_gates 5>, <&dram_gates 26>;
  94                         status = "disabled";
  95                 };
  96         };
  97
  98         cpus {
  99                 #address-cells = <1>;
 100                 #size-cells = <0>;
 101
 102                 cpu0: cpu@0 {
 103                         compatible = "arm,cortex-a7";
 104                         device_type = "cpu";
 105                         reg = <0>;
 106                         clocks = <&cpu>;
 107                         clock-latency = <244144>; /* 8 32k periods */
 108                         operating-points = <
 109                                 /* kHz    uV */
 110                                 960000  1400000
 111                                 912000  1400000
 112                                 864000  1300000
 113                                 720000  1200000
 114                                 528000  1100000
 115                                 312000  1000000
 116                                 144000  1000000
 117                                 >;
 118                         #cooling-cells = <2>;
 119                         cooling-min-level = <0>;
 120                         cooling-max-level = <6>;
 121                 };
 122
 123                 cpu@1 {
 124                         compatible = "arm,cortex-a7";
 125                         device_type = "cpu";
 126                         reg = <1>;
 127                 };
 128         };
 129
 130         thermal-zones {
 131                 cpu_thermal {
 132                         /* milliseconds */
 133                         polling-delay-passive = <250>;
 134                         polling-delay = <1000>;
 135                         thermal-sensors = <&rtp>;
 136
 137                         cooling-maps {
 138                                 map0 {
 139                                         trip = <&cpu_alert0>;
 140                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 141                                 };
 142                         };
 143
 144                         trips {
 145                                 cpu_alert0: cpu_alert0 {
 146                                         /* milliCelsius */
 147                                         temperature = <75000>;
 148                                         hysteresis = <2000>;
 149                                         type = "passive";
 150                                 };
 151
 152                                 cpu_crit: cpu_crit {
 153                                         /* milliCelsius */
 154                                         temperature = <100000>;
 155                                         hysteresis = <2000>;
 156                                         type = "critical";
 157                                 };
 158                         };
 159                 };
 160         };
 161
 162         memory {
 163                 reg = <0x40000000 0x80000000>;
 164         };
 165
 166         timer {
 167                 compatible = "arm,armv7-timer";
 168                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 169                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 170                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 171                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 172         };
 173
 174         pmu {
 175                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
 176                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 177                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 178         };
 179
 180         clocks {
 181                 #address-cells = <1>;
 182                 #size-cells = <1>;
 183                 ranges;
 184
 185                 osc24M: clk@01c20050 {
 186                         #clock-cells = <0>;
 187                         compatible = "allwinner,sun4i-a10-osc-clk";
 188                         reg = <0x01c20050 0x4>;
 189                         clock-frequency = <24000000>;
 190                         clock-output-names = "osc24M";
 191                 };
 192
 193                 osc3M: osc3M_clk {
 194                         #clock-cells = <0>;
 195                         compatible = "fixed-factor-clock";
 196                         clock-div = <8>;
 197                         clock-mult = <1>;
 198                         clocks = <&osc24M>;
 199                         clock-output-names = "osc3M";
 200                 };
 201
 202                 osc32k: clk@0 {
 203                         #clock-cells = <0>;
 204                         compatible = "fixed-clock";
 205                         clock-frequency = <32768>;
 206                         clock-output-names = "osc32k";
 207                 };
 208
 209                 pll1: clk@01c20000 {
 210                         #clock-cells = <0>;
 211                         compatible = "allwinner,sun4i-a10-pll1-clk";
 212                         reg = <0x01c20000 0x4>;
 213                         clocks = <&osc24M>;
 214                         clock-output-names = "pll1";
 215                 };
 216
 217                 pll2: clk@01c20008 {
 218                         #clock-cells = <1>;
 219                         compatible = "allwinner,sun4i-a10-pll2-clk";
 220                         reg = <0x01c20008 0x8>;
 221                         clocks = <&osc24M>;
 222                         clock-output-names = "pll2-1x", "pll2-2x",
 223                                              "pll2-4x", "pll2-8x";
 224                 };
 225
 226                 pll3: clk@01c20010 {
 227                         #clock-cells = <0>;
 228                         compatible = "allwinner,sun4i-a10-pll3-clk";
 229                         reg = <0x01c20010 0x4>;
 230                         clocks = <&osc3M>;
 231                         clock-output-names = "pll3";
 232                 };
 233
 234                 pll3x2: pll3x2_clk {
 235                         #clock-cells = <0>;
 236                         compatible = "fixed-factor-clock";
 237                         clocks = <&pll3>;
 238                         clock-div = <1>;
 239                         clock-mult = <2>;
 240                         clock-output-names = "pll3-2x";
 241                 };
 242
 243                 pll4: clk@01c20018 {
 244                         #clock-cells = <0>;
 245                         compatible = "allwinner,sun7i-a20-pll4-clk";
 246                         reg = <0x01c20018 0x4>;
 247                         clocks = <&osc24M>;
 248                         clock-output-names = "pll4";
 249                 };
 250
 251                 pll5: clk@01c20020 {
 252                         #clock-cells = <1>;
 253                         compatible = "allwinner,sun4i-a10-pll5-clk";
 254                         reg = <0x01c20020 0x4>;
 255                         clocks = <&osc24M>;
 256                         clock-output-names = "pll5_ddr", "pll5_other";
 257                 };
 258
 259                 pll6: clk@01c20028 {
 260                         #clock-cells = <1>;
 261                         compatible = "allwinner,sun4i-a10-pll6-clk";
 262                         reg = <0x01c20028 0x4>;
 263                         clocks = <&osc24M>;
 264                         clock-output-names = "pll6_sata", "pll6_other", "pll6",
 265                                              "pll6_div_4";
 266                 };
 267
 268                 pll7: clk@01c20030 {
 269                         #clock-cells = <0>;
 270                         compatible = "allwinner,sun4i-a10-pll3-clk";
 271                         reg = <0x01c20030 0x4>;
 272                         clocks = <&osc3M>;
 273                         clock-output-names = "pll7";
 274                 };
 275
 276                 pll7x2: pll7x2_clk {
 277                         #clock-cells = <0>;
 278                         compatible = "fixed-factor-clock";
 279                         clocks = <&pll7>;
 280                         clock-div = <1>;
 281                         clock-mult = <2>;
 282                         clock-output-names = "pll7-2x";
 283                 };
 284
 285                 pll8: clk@01c20040 {
 286                         #clock-cells = <0>;
 287                         compatible = "allwinner,sun7i-a20-pll4-clk";
 288                         reg = <0x01c20040 0x4>;
 289                         clocks = <&osc24M>;
 290                         clock-output-names = "pll8";
 291                 };
 292
 293                 cpu: cpu@01c20054 {
 294                         #clock-cells = <0>;
 295                         compatible = "allwinner,sun4i-a10-cpu-clk";
 296                         reg = <0x01c20054 0x4>;
 297                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
 298                         clock-output-names = "cpu";
 299                 };
 300
 301                 axi: axi@01c20054 {
 302                         #clock-cells = <0>;
 303                         compatible = "allwinner,sun4i-a10-axi-clk";
 304                         reg = <0x01c20054 0x4>;
 305                         clocks = <&cpu>;
 306                         clock-output-names = "axi";
 307                 };
 308
 309                 ahb: ahb@01c20054 {
 310                         #clock-cells = <0>;
 311                         compatible = "allwinner,sun5i-a13-ahb-clk";
 312                         reg = <0x01c20054 0x4>;
 313                         clocks = <&axi>, <&pll6 3>, <&pll6 1>;
 314                         clock-output-names = "ahb";
 315                         /*
 316                          * Use PLL6 as parent, instead of CPU/AXI
 317                          * which has rate changes due to cpufreq
 318                          */
 319                         assigned-clocks = <&ahb>;
 320                         assigned-clock-parents = <&pll6 3>;
 321                 };
 322
 323                 ahb_gates: clk@01c20060 {
 324                         #clock-cells = <1>;
 325                         compatible = "allwinner,sun7i-a20-ahb-gates-clk";
 326                         reg = <0x01c20060 0x8>;
 327                         clocks = <&ahb>;
 328                         clock-indices = <0>, <1>,
 329                                         <2>, <3>, <4>,
 330                                         <5>, <6>, <7>, <8>,
 331                                         <9>, <10>, <11>, <12>,
 332                                         <13>, <14>, <16>,
 333                                         <17>, <18>, <20>, <21>,
 334                                         <22>, <23>, <25>,
 335                                         <28>, <32>, <33>, <34>,
 336                                         <35>, <36>, <37>, <40>,
 337                                         <41>, <42>, <43>,
 338                                         <44>, <45>, <46>,
 339                                         <47>, <49>, <50>,
 340                                         <52>;
 341                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 342                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
 343                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 344                                 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
 345                                 "ahb_nand", "ahb_sdram", "ahb_ace",
 346                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 347                                 "ahb_spi2", "ahb_spi3", "ahb_sata",
 348                                 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
 349                                 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
 350                                 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
 351                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 352                                 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
 353                                 "ahb_mali";
 354                 };
 355
 356                 apb0: apb0@01c20054 {
 357                         #clock-cells = <0>;
 358                         compatible = "allwinner,sun4i-a10-apb0-clk";
 359                         reg = <0x01c20054 0x4>;
 360                         clocks = <&ahb>;
 361                         clock-output-names = "apb0";
 362                 };
 363
 364                 apb0_gates: clk@01c20068 {
 365                         #clock-cells = <1>;
 366                         compatible = "allwinner,sun7i-a20-apb0-gates-clk";
 367                         reg = <0x01c20068 0x4>;
 368                         clocks = <&apb0>;
 369                         clock-indices = <0>, <1>,
 370                                         <2>, <3>, <4>,
 371                                         <5>, <6>, <7>,
 372                                         <8>, <10>;
 373                         clock-output-names = "apb0_codec", "apb0_spdif",
 374                                 "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
 375                                 "apb0_pio", "apb0_ir0", "apb0_ir1",
 376                                 "apb0_i2s2", "apb0_keypad";
 377                 };
 378
 379                 apb1: clk@01c20058 {
 380                         #clock-cells = <0>;
 381                         compatible = "allwinner,sun4i-a10-apb1-clk";
 382                         reg = <0x01c20058 0x4>;
 383                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 384                         clock-output-names = "apb1";
 385                 };
 386
 387                 apb1_gates: clk@01c2006c {
 388                         #clock-cells = <1>;
 389                         compatible = "allwinner,sun7i-a20-apb1-gates-clk";
 390                         reg = <0x01c2006c 0x4>;
 391                         clocks = <&apb1>;
 392                         clock-indices = <0>, <1>,
 393                                         <2>, <3>, <4>,
 394                                         <5>, <6>, <7>,
 395                                         <15>, <16>, <17>,
 396                                         <18>, <19>, <20>,
 397                                         <21>, <22>, <23>;
 398                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 399                                 "apb1_i2c2", "apb1_i2c3", "apb1_can",
 400                                 "apb1_scr", "apb1_ps20", "apb1_ps21",
 401                                 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
 402                                 "apb1_uart2", "apb1_uart3", "apb1_uart4",
 403                                 "apb1_uart5", "apb1_uart6", "apb1_uart7";
 404                 };
 405
 406                 nand_clk: clk@01c20080 {
 407                         #clock-cells = <0>;
 408                         compatible = "allwinner,sun4i-a10-mod0-clk";
 409                         reg = <0x01c20080 0x4>;
 410                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 411                         clock-output-names = "nand";
 412                 };
 413
 414                 ms_clk: clk@01c20084 {
 415                         #clock-cells = <0>;
 416                         compatible = "allwinner,sun4i-a10-mod0-clk";
 417                         reg = <0x01c20084 0x4>;
 418                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 419                         clock-output-names = "ms";
 420                 };
 421
 422                 mmc0_clk: clk@01c20088 {
 423                         #clock-cells = <1>;
 424                         compatible = "allwinner,sun4i-a10-mmc-clk";
 425                         reg = <0x01c20088 0x4>;
 426                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 427                         clock-output-names = "mmc0",
 428                                              "mmc0_output",
 429                                              "mmc0_sample";
 430                 };
 431
 432                 mmc1_clk: clk@01c2008c {
 433                         #clock-cells = <1>;
 434                         compatible = "allwinner,sun4i-a10-mmc-clk";
 435                         reg = <0x01c2008c 0x4>;
 436                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 437                         clock-output-names = "mmc1",
 438                                              "mmc1_output",
 439                                              "mmc1_sample";
 440                 };
 441
 442                 mmc2_clk: clk@01c20090 {
 443                         #clock-cells = <1>;
 444                         compatible = "allwinner,sun4i-a10-mmc-clk";
 445                         reg = <0x01c20090 0x4>;
 446                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 447                         clock-output-names = "mmc2",
 448                                              "mmc2_output",
 449                                              "mmc2_sample";
 450                 };
 451
 452                 mmc3_clk: clk@01c20094 {
 453                         #clock-cells = <1>;
 454                         compatible = "allwinner,sun4i-a10-mmc-clk";
 455                         reg = <0x01c20094 0x4>;
 456                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 457                         clock-output-names = "mmc3",
 458                                              "mmc3_output",
 459                                              "mmc3_sample";
 460                 };
 461
 462                 ts_clk: clk@01c20098 {
 463                         #clock-cells = <0>;
 464                         compatible = "allwinner,sun4i-a10-mod0-clk";
 465                         reg = <0x01c20098 0x4>;
 466                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 467                         clock-output-names = "ts";
 468                 };
 469
 470                 ss_clk: clk@01c2009c {
 471                         #clock-cells = <0>;
 472                         compatible = "allwinner,sun4i-a10-mod0-clk";
 473                         reg = <0x01c2009c 0x4>;
 474                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 475                         clock-output-names = "ss";
 476                 };
 477
 478                 spi0_clk: clk@01c200a0 {
 479                         #clock-cells = <0>;
 480                         compatible = "allwinner,sun4i-a10-mod0-clk";
 481                         reg = <0x01c200a0 0x4>;
 482                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 483                         clock-output-names = "spi0";
 484                 };
 485
 486                 spi1_clk: clk@01c200a4 {
 487                         #clock-cells = <0>;
 488                         compatible = "allwinner,sun4i-a10-mod0-clk";
 489                         reg = <0x01c200a4 0x4>;
 490                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 491                         clock-output-names = "spi1";
 492                 };
 493
 494                 spi2_clk: clk@01c200a8 {
 495                         #clock-cells = <0>;
 496                         compatible = "allwinner,sun4i-a10-mod0-clk";
 497                         reg = <0x01c200a8 0x4>;
 498                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 499                         clock-output-names = "spi2";
 500                 };
 501
 502                 pata_clk: clk@01c200ac {
 503                         #clock-cells = <0>;
 504                         compatible = "allwinner,sun4i-a10-mod0-clk";
 505                         reg = <0x01c200ac 0x4>;
 506                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 507                         clock-output-names = "pata";
 508                 };
 509
 510                 ir0_clk: clk@01c200b0 {
 511                         #clock-cells = <0>;
 512                         compatible = "allwinner,sun4i-a10-mod0-clk";
 513                         reg = <0x01c200b0 0x4>;
 514                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 515                         clock-output-names = "ir0";
 516                 };
 517
 518                 ir1_clk: clk@01c200b4 {
 519                         #clock-cells = <0>;
 520                         compatible = "allwinner,sun4i-a10-mod0-clk";
 521                         reg = <0x01c200b4 0x4>;
 522                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 523                         clock-output-names = "ir1";
 524                 };
 525
 526                 i2s0_clk: clk@01c200b8 {
 527                         #clock-cells = <0>;
 528                         compatible = "allwinner,sun4i-a10-mod1-clk";
 529                         reg = <0x01c200b8 0x4>;
 530                         clocks = <&pll2 SUN4I_A10_PLL2_8X>,
 531                                  <&pll2 SUN4I_A10_PLL2_4X>,
 532                                  <&pll2 SUN4I_A10_PLL2_2X>,
 533                                  <&pll2 SUN4I_A10_PLL2_1X>;
 534                         clock-output-names = "i2s0";
 535                 };
 536
 537                 ac97_clk: clk@01c200bc {
 538                         #clock-cells = <0>;
 539                         compatible = "allwinner,sun4i-a10-mod1-clk";
 540                         reg = <0x01c200bc 0x4>;
 541                         clocks = <&pll2 SUN4I_A10_PLL2_8X>,
 542                                  <&pll2 SUN4I_A10_PLL2_4X>,
 543                                  <&pll2 SUN4I_A10_PLL2_2X>,
 544                                  <&pll2 SUN4I_A10_PLL2_1X>;
 545                         clock-output-names = "ac97";
 546                 };
 547
 548                 spdif_clk: clk@01c200c0 {
 549                         #clock-cells = <0>;
 550                         compatible = "allwinner,sun4i-a10-mod1-clk";
 551                         reg = <0x01c200c0 0x4>;
 552                         clocks = <&pll2 SUN4I_A10_PLL2_8X>,
 553                                  <&pll2 SUN4I_A10_PLL2_4X>,
 554                                  <&pll2 SUN4I_A10_PLL2_2X>,
 555                                  <&pll2 SUN4I_A10_PLL2_1X>;
 556                         clock-output-names = "spdif";
 557                 };
 558
 559                 keypad_clk: clk@01c200c4 {
 560                         #clock-cells = <0>;
 561                         compatible = "allwinner,sun4i-a10-mod0-clk";
 562                         reg = <0x01c200c4 0x4>;
 563                         clocks = <&osc24M>;
 564                         clock-output-names = "keypad";
 565                 };
 566
 567                 usb_clk: clk@01c200cc {
 568                         #clock-cells = <1>;
 569                         #reset-cells = <1>;
 570                         compatible = "allwinner,sun4i-a10-usb-clk";
 571                         reg = <0x01c200cc 0x4>;
 572                         clocks = <&pll6 1>;
 573                         clock-output-names = "usb_ohci0", "usb_ohci1",
 574                                              "usb_phy";
 575                 };
 576
 577                 spi3_clk: clk@01c200d4 {
 578                         #clock-cells = <0>;
 579                         compatible = "allwinner,sun4i-a10-mod0-clk";
 580                         reg = <0x01c200d4 0x4>;
 581                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 582                         clock-output-names = "spi3";
 583                 };
 584
 585                 i2s1_clk: clk@01c200d8 {
 586                         #clock-cells = <0>;
 587                         compatible = "allwinner,sun4i-a10-mod1-clk";
 588                         reg = <0x01c200d8 0x4>;
 589                         clocks = <&pll2 SUN4I_A10_PLL2_8X>,
 590                                  <&pll2 SUN4I_A10_PLL2_4X>,
 591                                  <&pll2 SUN4I_A10_PLL2_2X>,
 592                                  <&pll2 SUN4I_A10_PLL2_1X>;
 593                         clock-output-names = "i2s1";
 594                 };
 595
 596                 i2s2_clk: clk@01c200dc {
 597                         #clock-cells = <0>;
 598                         compatible = "allwinner,sun4i-a10-mod1-clk";
 599                         reg = <0x01c200dc 0x4>;
 600                         clocks = <&pll2 SUN4I_A10_PLL2_8X>,
 601                                  <&pll2 SUN4I_A10_PLL2_4X>,
 602                                  <&pll2 SUN4I_A10_PLL2_2X>,
 603                                  <&pll2 SUN4I_A10_PLL2_1X>;
 604                         clock-output-names = "i2s2";
 605                 };
 606
 607                 dram_gates: clk@01c20100 {
 608                         #clock-cells = <1>;
 609                         compatible = "allwinner,sun4i-a10-dram-gates-clk";
 610                         reg = <0x01c20100 0x4>;
 611                         clocks = <&pll5 0>;
 612                         clock-indices = <0>,
 613                                         <1>, <2>,
 614                                         <3>,
 615                                         <4>,
 616                                         <5>, <6>,
 617                                         <15>,
 618                                         <24>, <25>,
 619                                         <26>, <27>,
 620                                         <28>, <29>;
 621                         clock-output-names = "dram_ve",
 622                                              "dram_csi0", "dram_csi1",
 623                                              "dram_ts",
 624                                              "dram_tvd",
 625                                              "dram_tve0", "dram_tve1",
 626                                              "dram_output",
 627                                              "dram_de_fe1", "dram_de_fe0",
 628                                              "dram_de_be0", "dram_de_be1",
 629                                              "dram_de_mp", "dram_ace";
 630                 };
 631
 632                 de_be0_clk: clk@01c20104 {
 633                         #clock-cells = <0>;
 634                         #reset-cells = <0>;
 635                         compatible = "allwinner,sun4i-a10-display-clk";
 636                         reg = <0x01c20104 0x4>;
 637                         clocks = <&pll3>, <&pll7>, <&pll5 1>;
 638                         clock-output-names = "de-be0";
 639                 };
 640
 641                 de_be1_clk: clk@01c20108 {
 642                         #clock-cells = <0>;
 643                         #reset-cells = <0>;
 644                         compatible = "allwinner,sun4i-a10-display-clk";
 645                         reg = <0x01c20108 0x4>;
 646                         clocks = <&pll3>, <&pll7>, <&pll5 1>;
 647                         clock-output-names = "de-be1";
 648                 };
 649
 650                 de_fe0_clk: clk@01c2010c {
 651                         #clock-cells = <0>;
 652                         #reset-cells = <0>;
 653                         compatible = "allwinner,sun4i-a10-display-clk";
 654                         reg = <0x01c2010c 0x4>;
 655                         clocks = <&pll3>, <&pll7>, <&pll5 1>;
 656                         clock-output-names = "de-fe0";
 657                 };
 658
 659                 de_fe1_clk: clk@01c20110 {
 660                         #clock-cells = <0>;
 661                         #reset-cells = <0>;
 662                         compatible = "allwinner,sun4i-a10-display-clk";
 663                         reg = <0x01c20110 0x4>;
 664                         clocks = <&pll3>, <&pll7>, <&pll5 1>;
 665                         clock-output-names = "de-fe1";
 666                 };
 667
 668                 tcon0_ch0_clk: clk@01c20118 {
 669                         #clock-cells = <0>;
 670                         #reset-cells = <1>;
 671                         compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
 672                         reg = <0x01c20118 0x4>;
 673                         clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
 674                         clock-output-names = "tcon0-ch0-sclk";
 675
 676                 };
 677
 678                 tcon1_ch0_clk: clk@01c2011c {
 679                         #clock-cells = <0>;
 680                         #reset-cells = <1>;
 681                         compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
 682                         reg = <0x01c2011c 0x4>;
 683                         clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
 684                         clock-output-names = "tcon1-ch0-sclk";
 685
 686                 };
 687
 688                 tcon0_ch1_clk: clk@01c2012c {
 689                         #clock-cells = <0>;
 690                         compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
 691                         reg = <0x01c2012c 0x4>;
 692                         clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
 693                         clock-output-names = "tcon0-ch1-sclk";
 694
 695                 };
 696
 697                 tcon1_ch1_clk: clk@01c20130 {
 698                         #clock-cells = <0>;
 699                         compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
 700                         reg = <0x01c20130 0x4>;
 701                         clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
 702                         clock-output-names = "tcon1-ch1-sclk";
 703
 704                 };
 705
 706                 ve_clk: clk@01c2013c {
 707                         #clock-cells = <0>;
 708                         #reset-cells = <0>;
 709                         compatible = "allwinner,sun4i-a10-ve-clk";
 710                         reg = <0x01c2013c 0x4>;
 711                         clocks = <&pll4>;
 712                         clock-output-names = "ve";
 713                 };
 714
 715                 codec_clk: clk@01c20140 {
 716                         #clock-cells = <0>;
 717                         compatible = "allwinner,sun4i-a10-codec-clk";
 718                         reg = <0x01c20140 0x4>;
 719                         clocks = <&pll2 SUN4I_A10_PLL2_1X>;
 720                         clock-output-names = "codec";
 721                 };
 722
 723                 mbus_clk: clk@01c2015c {
 724                         #clock-cells = <0>;
 725                         compatible = "allwinner,sun5i-a13-mbus-clk";
 726                         reg = <0x01c2015c 0x4>;
 727                         clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
 728                         clock-output-names = "mbus";
 729                 };
 730
 731                 /*
 732                  * The following two are dummy clocks, placeholders
 733                  * used in the gmac_tx clock. The gmac driver will
 734                  * choose one parent depending on the PHY interface
 735                  * mode, using clk_set_rate auto-reparenting.
 736                  *
 737                  * The actual TX clock rate is not controlled by the
 738                  * gmac_tx clock.
 739                  */
 740                 mii_phy_tx_clk: clk@2 {
 741                         #clock-cells = <0>;
 742                         compatible = "fixed-clock";
 743                         clock-frequency = <25000000>;
 744                         clock-output-names = "mii_phy_tx";
 745                 };
 746
 747                 gmac_int_tx_clk: clk@3 {
 748                         #clock-cells = <0>;
 749                         compatible = "fixed-clock";
 750                         clock-frequency = <125000000>;
 751                         clock-output-names = "gmac_int_tx";
 752                 };
 753
 754                 gmac_tx_clk: clk@01c20164 {
 755                         #clock-cells = <0>;
 756                         compatible = "allwinner,sun7i-a20-gmac-clk";
 757                         reg = <0x01c20164 0x4>;
 758                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 759                         clock-output-names = "gmac_tx";
 760                 };
 761
 762                 /*
 763                  * Dummy clock used by output clocks
 764                  */
 765                 osc24M_32k: clk@1 {
 766                         #clock-cells = <0>;
 767                         compatible = "fixed-factor-clock";
 768                         clock-div = <750>;
 769                         clock-mult = <1>;
 770                         clocks = <&osc24M>;
 771                         clock-output-names = "osc24M_32k";
 772                 };
 773
 774                 clk_out_a: clk@01c201f0 {
 775                         #clock-cells = <0>;
 776                         compatible = "allwinner,sun7i-a20-out-clk";
 777                         reg = <0x01c201f0 0x4>;
 778                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 779                         clock-output-names = "clk_out_a";
 780                 };
 781
 782                 clk_out_b: clk@01c201f4 {
 783                         #clock-cells = <0>;
 784                         compatible = "allwinner,sun7i-a20-out-clk";
 785                         reg = <0x01c201f4 0x4>;
 786                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 787                         clock-output-names = "clk_out_b";
 788                 };
 789         };
 790
 791         soc@01c00000 {
 792                 compatible = "simple-bus";
 793                 #address-cells = <1>;
 794                 #size-cells = <1>;
 795                 ranges;
 796
 797                 sram-controller@01c00000 {
 798                         compatible = "allwinner,sun4i-a10-sram-controller";
 799                         reg = <0x01c00000 0x30>;
 800                         #address-cells = <1>;
 801                         #size-cells = <1>;
 802                         ranges;
 803
 804                         sram_a: sram@00000000 {
 805                                 compatible = "mmio-sram";
 806                                 reg = <0x00000000 0xc000>;
 807                                 #address-cells = <1>;
 808                                 #size-cells = <1>;
 809                                 ranges = <0 0x00000000 0xc000>;
 810
 811                                 emac_sram: sram-section@8000 {
 812                                         compatible = "allwinner,sun4i-a10-sram-a3-a4";
 813                                         reg = <0x8000 0x4000>;
 814                                         status = "disabled";
 815                                 };
 816                         };
 817
 818                         sram_d: sram@00010000 {
 819                                 compatible = "mmio-sram";
 820                                 reg = <0x00010000 0x1000>;
 821                                 #address-cells = <1>;
 822                                 #size-cells = <1>;
 823                                 ranges = <0 0x00010000 0x1000>;
 824
 825                                 otg_sram: sram-section@0000 {
 826                                         compatible = "allwinner,sun4i-a10-sram-d";
 827                                         reg = <0x0000 0x1000>;
 828                                         status = "disabled";
 829                                 };
 830                         };
 831                 };
 832
 833                 nmi_intc: interrupt-controller@01c00030 {
 834                         compatible = "allwinner,sun7i-a20-sc-nmi";
 835                         interrupt-controller;
 836                         #interrupt-cells = <2>;
 837                         reg = <0x01c00030 0x0c>;
 838                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 839                 };
 840
 841                 dma: dma-controller@01c02000 {
 842                         compatible = "allwinner,sun4i-a10-dma";
 843                         reg = <0x01c02000 0x1000>;
 844                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 845                         clocks = <&ahb_gates 6>;
 846                         #dma-cells = <2>;
 847                 };
 848
 849                 nfc: nand@01c03000 {
 850                         compatible = "allwinner,sun4i-a10-nand";
 851                         reg = <0x01c03000 0x1000>;
 852                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 853                         clocks = <&ahb_gates 13>, <&nand_clk>;
 854                         clock-names = "ahb", "mod";
 855                         dmas = <&dma SUN4I_DMA_DEDICATED 3>;
 856                         dma-names = "rxtx";
 857                         status = "disabled";
 858                         #address-cells = <1>;
 859                         #size-cells = <0>;
 860                 };
 861
 862                 spi0: spi@01c05000 {
 863                         compatible = "allwinner,sun4i-a10-spi";
 864                         reg = <0x01c05000 0x1000>;
 865                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 866                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 867                         clock-names = "ahb", "mod";
 868                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 869                                <&dma SUN4I_DMA_DEDICATED 26>;
 870                         dma-names = "rx", "tx";
 871                         status = "disabled";
 872                         #address-cells = <1>;
 873                         #size-cells = <0>;
 874                 };
 875
 876                 spi1: spi@01c06000 {
 877                         compatible = "allwinner,sun4i-a10-spi";
 878                         reg = <0x01c06000 0x1000>;
 879                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 880                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 881                         clock-names = "ahb", "mod";
 882                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 883                                <&dma SUN4I_DMA_DEDICATED 8>;
 884                         dma-names = "rx", "tx";
 885                         status = "disabled";
 886                         #address-cells = <1>;
 887                         #size-cells = <0>;
 888                 };
 889
 890                 emac: ethernet@01c0b000 {
 891                         compatible = "allwinner,sun4i-a10-emac";
 892                         reg = <0x01c0b000 0x1000>;
 893                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 894                         clocks = <&ahb_gates 17>;
 895                         allwinner,sram = <&emac_sram 1>;
 896                         status = "disabled";
 897                 };
 898
 899                 mdio: mdio@01c0b080 {
 900                         compatible = "allwinner,sun4i-a10-mdio";
 901                         reg = <0x01c0b080 0x14>;
 902                         status = "disabled";
 903                         #address-cells = <1>;
 904                         #size-cells = <0>;
 905                 };
 906
 907                 mmc0: mmc@01c0f000 {
 908                         compatible = "allwinner,sun7i-a20-mmc",
 909                                      "allwinner,sun5i-a13-mmc";
 910                         reg = <0x01c0f000 0x1000>;
 911                         clocks = <&ahb_gates 8>,
 912                                  <&mmc0_clk 0>,
 913                                  <&mmc0_clk 1>,
 914                                  <&mmc0_clk 2>;
 915                         clock-names = "ahb",
 916                                       "mmc",
 917                                       "output",
 918                                       "sample";
 919                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 920                         status = "disabled";
 921                         #address-cells = <1>;
 922                         #size-cells = <0>;
 923                 };
 924
 925                 mmc1: mmc@01c10000 {
 926                         compatible = "allwinner,sun7i-a20-mmc",
 927                                      "allwinner,sun5i-a13-mmc";
 928                         reg = <0x01c10000 0x1000>;
 929                         clocks = <&ahb_gates 9>,
 930                                  <&mmc1_clk 0>,
 931                                  <&mmc1_clk 1>,
 932                                  <&mmc1_clk 2>;
 933                         clock-names = "ahb",
 934                                       "mmc",
 935                                       "output",
 936                                       "sample";
 937                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 938                         status = "disabled";
 939                         #address-cells = <1>;
 940                         #size-cells = <0>;
 941                 };
 942
 943                 mmc2: mmc@01c11000 {
 944                         compatible = "allwinner,sun7i-a20-mmc",
 945                                      "allwinner,sun5i-a13-mmc";
 946                         reg = <0x01c11000 0x1000>;
 947                         clocks = <&ahb_gates 10>,
 948                                  <&mmc2_clk 0>,
 949                                  <&mmc2_clk 1>,
 950                                  <&mmc2_clk 2>;
 951                         clock-names = "ahb",
 952                                       "mmc",
 953                                       "output",
 954                                       "sample";
 955                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 956                         status = "disabled";
 957                         #address-cells = <1>;
 958                         #size-cells = <0>;
 959                 };
 960
 961                 mmc3: mmc@01c12000 {
 962                         compatible = "allwinner,sun7i-a20-mmc",
 963                                      "allwinner,sun5i-a13-mmc";
 964                         reg = <0x01c12000 0x1000>;
 965                         clocks = <&ahb_gates 11>,
 966                                  <&mmc3_clk 0>,
 967                                  <&mmc3_clk 1>,
 968                                  <&mmc3_clk 2>;
 969                         clock-names = "ahb",
 970                                       "mmc",
 971                                       "output",
 972                                       "sample";
 973                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 974                         status = "disabled";
 975                         #address-cells = <1>;
 976                         #size-cells = <0>;
 977                 };
 978
 979                 usb_otg: usb@01c13000 {
 980                         compatible = "allwinner,sun4i-a10-musb";
 981                         reg = <0x01c13000 0x0400>;
 982                         clocks = <&ahb_gates 0>;
 983                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 984                         interrupt-names = "mc";
 985                         phys = <&usbphy 0>;
 986                         phy-names = "usb";
 987                         extcon = <&usbphy 0>;
 988                         allwinner,sram = <&otg_sram 1>;
 989                         status = "disabled";
 990                 };
 991
 992                 usbphy: phy@01c13400 {
 993                         #phy-cells = <1>;
 994                         compatible = "allwinner,sun7i-a20-usb-phy";
 995                         reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
 996                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 997                         clocks = <&usb_clk 8>;
 998                         clock-names = "usb_phy";
 999                         resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
1000                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
1001                         status = "disabled";
1002                 };
1003
1004                 ehci0: usb@01c14000 {
1005                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
1006                         reg = <0x01c14000 0x100>;
1007                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1008                         clocks = <&ahb_gates 1>;
1009                         phys = <&usbphy 1>;
1010                         phy-names = "usb";
1011                         status = "disabled";
1012                 };
1013
1014                 ohci0: usb@01c14400 {
1015                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
1016                         reg = <0x01c14400 0x100>;
1017                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1018                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
1019                         phys = <&usbphy 1>;
1020                         phy-names = "usb";
1021                         status = "disabled";
1022                 };
1023
1024                 crypto: crypto-engine@01c15000 {
1025                         compatible = "allwinner,sun4i-a10-crypto";
1026                         reg = <0x01c15000 0x1000>;
1027                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1028                         clocks = <&ahb_gates 5>, <&ss_clk>;
1029                         clock-names = "ahb", "mod";
1030                 };
1031
1032                 spi2: spi@01c17000 {
1033                         compatible = "allwinner,sun4i-a10-spi";
1034                         reg = <0x01c17000 0x1000>;
1035                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1036                         clocks = <&ahb_gates 22>, <&spi2_clk>;
1037                         clock-names = "ahb", "mod";
1038                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
1039                                <&dma SUN4I_DMA_DEDICATED 28>;
1040                         dma-names = "rx", "tx";
1041                         status = "disabled";
1042                         #address-cells = <1>;
1043                         #size-cells = <0>;
1044                 };
1045
1046                 ahci: sata@01c18000 {
1047                         compatible = "allwinner,sun4i-a10-ahci";
1048                         reg = <0x01c18000 0x1000>;
1049                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1050                         clocks = <&pll6 0>, <&ahb_gates 25>;
1051                         status = "disabled";
1052                 };
1053
1054                 ehci1: usb@01c1c000 {
1055                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
1056                         reg = <0x01c1c000 0x100>;
1057                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1058                         clocks = <&ahb_gates 3>;
1059                         phys = <&usbphy 2>;
1060                         phy-names = "usb";
1061                         status = "disabled";
1062                 };
1063
1064                 ohci1: usb@01c1c400 {
1065                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
1066                         reg = <0x01c1c400 0x100>;
1067                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1068                         clocks = <&usb_clk 7>, <&ahb_gates 4>;
1069                         phys = <&usbphy 2>;
1070                         phy-names = "usb";
1071                         status = "disabled";
1072                 };
1073
1074                 spi3: spi@01c1f000 {
1075                         compatible = "allwinner,sun4i-a10-spi";
1076                         reg = <0x01c1f000 0x1000>;
1077                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1078                         clocks = <&ahb_gates 23>, <&spi3_clk>;
1079                         clock-names = "ahb", "mod";
1080                         dmas = <&dma SUN4I_DMA_DEDICATED 31>,
1081                                <&dma SUN4I_DMA_DEDICATED 30>;
1082                         dma-names = "rx", "tx";
1083                         status = "disabled";
1084                         #address-cells = <1>;
1085                         #size-cells = <0>;
1086                 };
1087
1088                 pio: pinctrl@01c20800 {
1089                         compatible = "allwinner,sun7i-a20-pinctrl";
1090                         reg = <0x01c20800 0x400>;
1091                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1092                         clocks = <&apb0_gates 5>;
1093                         gpio-controller;
1094                         interrupt-controller;
1095                         #interrupt-cells = <3>;
1096                         #gpio-cells = <3>;
1097
1098                         clk_out_a_pins_a: clk_out_a@0 {
1099                                 allwinner,pins = "PI12";
1100                                 allwinner,function = "clk_out_a";
1101                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1102                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1103                         };
1104
1105                         clk_out_b_pins_a: clk_out_b@0 {
1106                                 allwinner,pins = "PI13";
1107                                 allwinner,function = "clk_out_b";
1108                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1109                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1110                         };
1111
1112                         emac_pins_a: emac0@0 {
1113                                 allwinner,pins = "PA0", "PA1", "PA2",
1114                                                 "PA3", "PA4", "PA5", "PA6",
1115                                                 "PA7", "PA8", "PA9", "PA10",
1116                                                 "PA11", "PA12", "PA13", "PA14",
1117                                                 "PA15", "PA16";
1118                                 allwinner,function = "emac";
1119                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1120                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1121                         };
1122
1123                         gmac_pins_mii_a: gmac_mii@0 {
1124                                 allwinner,pins = "PA0", "PA1", "PA2",
1125                                                 "PA3", "PA4", "PA5", "PA6",
1126                                                 "PA7", "PA8", "PA9", "PA10",
1127                                                 "PA11", "PA12", "PA13", "PA14",
1128                                                 "PA15", "PA16";
1129                                 allwinner,function = "gmac";
1130                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1131                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1132                         };
1133
1134                         gmac_pins_rgmii_a: gmac_rgmii@0 {
1135                                 allwinner,pins = "PA0", "PA1", "PA2",
1136                                                 "PA3", "PA4", "PA5", "PA6",
1137                                                 "PA7", "PA8", "PA10",
1138                                                 "PA11", "PA12", "PA13",
1139                                                 "PA15", "PA16";
1140                                 allwinner,function = "gmac";
1141                                 /*
1142                                  * data lines in RGMII mode use DDR mode
1143                                  * and need a higher signal drive strength
1144                                  */
1145                                 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
1146                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1147                         };
1148
1149                         i2c0_pins_a: i2c0@0 {
1150                                 allwinner,pins = "PB0", "PB1";
1151                                 allwinner,function = "i2c0";
1152                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1153                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1154                         };
1155
1156                         i2c1_pins_a: i2c1@0 {
1157                                 allwinner,pins = "PB18", "PB19";
1158                                 allwinner,function = "i2c1";
1159                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1160                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1161                         };
1162
1163                         i2c2_pins_a: i2c2@0 {
1164                                 allwinner,pins = "PB20", "PB21";
1165                                 allwinner,function = "i2c2";
1166                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1167                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1168                         };
1169
1170                         i2c3_pins_a: i2c3@0 {
1171                                 allwinner,pins = "PI0", "PI1";
1172                                 allwinner,function = "i2c3";
1173                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1174                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1175                         };
1176
1177                         ir0_rx_pins_a: ir0@0 {
1178                                     allwinner,pins = "PB4";
1179                                     allwinner,function = "ir0";
1180                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1181                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1182                         };
1183
1184                         ir0_tx_pins_a: ir0@1 {
1185                                     allwinner,pins = "PB3";
1186                                     allwinner,function = "ir0";
1187                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1188                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1189                         };
1190
1191                         ir1_rx_pins_a: ir1@0 {
1192                                     allwinner,pins = "PB23";
1193                                     allwinner,function = "ir1";
1194                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1195                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1196                         };
1197
1198                         ir1_tx_pins_a: ir1@1 {
1199                                     allwinner,pins = "PB22";
1200                                     allwinner,function = "ir1";
1201                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1202                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1203                         };
1204
1205                         mmc0_pins_a: mmc0@0 {
1206                                 allwinner,pins = "PF0", "PF1", "PF2",
1207                                                  "PF3", "PF4", "PF5";
1208                                 allwinner,function = "mmc0";
1209                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1210                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1211                         };
1212
1213                         mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
1214                                 allwinner,pins = "PH1";
1215                                 allwinner,function = "gpio_in";
1216                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1217                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1218                         };
1219
1220                         mmc2_pins_a: mmc2@0 {
1221                                 allwinner,pins = "PC6", "PC7", "PC8",
1222                                                  "PC9", "PC10", "PC11";
1223                                 allwinner,function = "mmc2";
1224                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1225                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1226                         };
1227
1228                         mmc3_pins_a: mmc3@0 {
1229                                 allwinner,pins = "PI4", "PI5", "PI6",
1230                                                  "PI7", "PI8", "PI9";
1231                                 allwinner,function = "mmc3";
1232                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1233                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1234                         };
1235
1236                         ps20_pins_a: ps20@0 {
1237                                 allwinner,pins = "PI20", "PI21";
1238                                 allwinner,function = "ps2";
1239                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1240                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1241                         };
1242
1243                         ps21_pins_a: ps21@0 {
1244                                 allwinner,pins = "PH12", "PH13";
1245                                 allwinner,function = "ps2";
1246                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1247                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1248                         };
1249
1250                         pwm0_pins_a: pwm0@0 {
1251                                 allwinner,pins = "PB2";
1252                                 allwinner,function = "pwm";
1253                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1254                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1255                         };
1256
1257                         pwm1_pins_a: pwm1@0 {
1258                                 allwinner,pins = "PI3";
1259                                 allwinner,function = "pwm";
1260                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1261                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1262                         };
1263
1264                         spdif_tx_pins_a: spdif@0 {
1265                                 allwinner,pins = "PB13";
1266                                 allwinner,function = "spdif";
1267                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1268                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1269                         };
1270
1271                         spi0_pins_a: spi0@0 {
1272                                 allwinner,pins = "PI11", "PI12", "PI13";
1273                                 allwinner,function = "spi0";
1274                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1275                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1276                         };
1277
1278                         spi0_cs0_pins_a: spi0_cs0@0 {
1279                                 allwinner,pins = "PI10";
1280                                 allwinner,function = "spi0";
1281                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1282                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1283                         };
1284
1285                         spi0_cs1_pins_a: spi0_cs1@0 {
1286                                 allwinner,pins = "PI14";
1287                                 allwinner,function = "spi0";
1288                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1289                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1290                         };
1291
1292                         spi1_pins_a: spi1@0 {
1293                                 allwinner,pins = "PI17", "PI18", "PI19";
1294                                 allwinner,function = "spi1";
1295                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1296                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1297                         };
1298
1299                         spi1_cs0_pins_a: spi1_cs0@0 {
1300                                 allwinner,pins = "PI16";
1301                                 allwinner,function = "spi1";
1302                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1303                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1304                         };
1305
1306                         spi2_pins_a: spi2@0 {
1307                                 allwinner,pins = "PC20", "PC21", "PC22";
1308                                 allwinner,function = "spi2";
1309                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1310                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1311                         };
1312
1313                         spi2_pins_b: spi2@1 {
1314                                 allwinner,pins = "PB15", "PB16", "PB17";
1315                                 allwinner,function = "spi2";
1316                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1317                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1318                         };
1319
1320                         spi2_cs0_pins_a: spi2_cs0@0 {
1321                                 allwinner,pins = "PC19";
1322                                 allwinner,function = "spi2";
1323                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1324                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1325                         };
1326
1327                         spi2_cs0_pins_b: spi2_cs0@1 {
1328                                 allwinner,pins = "PB14";
1329                                 allwinner,function = "spi2";
1330                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1331                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1332                         };
1333
1334                         uart0_pins_a: uart0@0 {
1335                                 allwinner,pins = "PB22", "PB23";
1336                                 allwinner,function = "uart0";
1337                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1338                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1339                         };
1340
1341                         uart2_pins_a: uart2@0 {
1342                                 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
1343                                 allwinner,function = "uart2";
1344                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1345                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1346                         };
1347
1348                         uart3_pins_a: uart3@0 {
1349                                 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
1350                                 allwinner,function = "uart3";
1351                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1352                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1353                         };
1354
1355                         uart3_pins_b: uart3@1 {
1356                                 allwinner,pins = "PH0", "PH1";
1357                                 allwinner,function = "uart3";
1358                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1359                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1360                         };
1361
1362                         uart4_pins_a: uart4@0 {
1363                                 allwinner,pins = "PG10", "PG11";
1364                                 allwinner,function = "uart4";
1365                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1366                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1367                         };
1368
1369                         uart4_pins_b: uart4@1 {
1370                                 allwinner,pins = "PH4", "PH5";
1371                                 allwinner,function = "uart4";
1372                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1373                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1374                         };
1375
1376                         uart5_pins_a: uart5@0 {
1377                                 allwinner,pins = "PI10", "PI11";
1378                                 allwinner,function = "uart5";
1379                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1380                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1381                         };
1382
1383                         uart6_pins_a: uart6@0 {
1384                                 allwinner,pins = "PI12", "PI13";
1385                                 allwinner,function = "uart6";
1386                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1387                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1388                         };
1389
1390                         uart7_pins_a: uart7@0 {
1391                                 allwinner,pins = "PI20", "PI21";
1392                                 allwinner,function = "uart7";
1393                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1394                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1395                         };
1396                 };
1397
1398                 timer@01c20c00 {
1399                         compatible = "allwinner,sun4i-a10-timer";
1400                         reg = <0x01c20c00 0x90>;
1401                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1402                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1403                                      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1404                                      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1405                                      <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1406                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1407                         clocks = <&osc24M>;
1408                 };
1409
1410                 wdt: watchdog@01c20c90 {
1411                         compatible = "allwinner,sun4i-a10-wdt";
1412                         reg = <0x01c20c90 0x10>;
1413                 };
1414
1415                 rtc: rtc@01c20d00 {
1416                         compatible = "allwinner,sun7i-a20-rtc";
1417                         reg = <0x01c20d00 0x20>;
1418                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1419                 };
1420
1421                 pwm: pwm@01c20e00 {
1422                         compatible = "allwinner,sun7i-a20-pwm";
1423                         reg = <0x01c20e00 0xc>;
1424                         clocks = <&osc24M>;
1425                         #pwm-cells = <3>;
1426                         status = "disabled";
1427                 };
1428
1429                 spdif: spdif@01c21000 {
1430                         #sound-dai-cells = <0>;
1431                         compatible = "allwinner,sun4i-a10-spdif";
1432                         reg = <0x01c21000 0x400>;
1433                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1434                         clocks = <&apb0_gates 1>, <&spdif_clk>;
1435                         clock-names = "apb", "spdif";
1436                         dmas = <&dma SUN4I_DMA_NORMAL 2>,
1437                                <&dma SUN4I_DMA_NORMAL 2>;
1438                         dma-names = "rx", "tx";
1439                         status = "disabled";
1440                 };
1441
1442                 ir0: ir@01c21800 {
1443                         compatible = "allwinner,sun4i-a10-ir";
1444                         clocks = <&apb0_gates 6>, <&ir0_clk>;
1445                         clock-names = "apb", "ir";
1446                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1447                         reg = <0x01c21800 0x40>;
1448                         status = "disabled";
1449                 };
1450
1451                 ir1: ir@01c21c00 {
1452                         compatible = "allwinner,sun4i-a10-ir";
1453                         clocks = <&apb0_gates 7>, <&ir1_clk>;
1454                         clock-names = "apb", "ir";
1455                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1456                         reg = <0x01c21c00 0x40>;
1457                         status = "disabled";
1458                 };
1459
1460                 i2s1: i2s@01c22000 {
1461                         #sound-dai-cells = <0>;
1462                         compatible = "allwinner,sun4i-a10-i2s";
1463                         reg = <0x01c22000 0x400>;
1464                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1465                         clocks = <&apb0_gates 4>, <&i2s1_clk>;
1466                         clock-names = "apb", "mod";
1467                         dmas = <&dma SUN4I_DMA_NORMAL 4>,
1468                                <&dma SUN4I_DMA_NORMAL 4>;
1469                         dma-names = "rx", "tx";
1470                         status = "disabled";
1471                 };
1472
1473                 i2s0: i2s@01c22400 {
1474                         #sound-dai-cells = <0>;
1475                         compatible = "allwinner,sun4i-a10-i2s";
1476                         reg = <0x01c22400 0x400>;
1477                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1478                         clocks = <&apb0_gates 3>, <&i2s0_clk>;
1479                         clock-names = "apb", "mod";
1480                         dmas = <&dma SUN4I_DMA_NORMAL 3>,
1481                                <&dma SUN4I_DMA_NORMAL 3>;
1482                         dma-names = "rx", "tx";
1483                         status = "disabled";
1484                 };
1485
1486                 lradc: lradc@01c22800 {
1487                         compatible = "allwinner,sun4i-a10-lradc-keys";
1488                         reg = <0x01c22800 0x100>;
1489                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1490                         status = "disabled";
1491                 };
1492
1493                 codec: codec@01c22c00 {
1494                         #sound-dai-cells = <0>;
1495                         compatible = "allwinner,sun7i-a20-codec";
1496                         reg = <0x01c22c00 0x40>;
1497                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1498                         clocks = <&apb0_gates 0>, <&codec_clk>;
1499                         clock-names = "apb", "codec";
1500                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
1501                                <&dma SUN4I_DMA_NORMAL 19>;
1502                         dma-names = "rx", "tx";
1503                         status = "disabled";
1504                 };
1505
1506                 sid: eeprom@01c23800 {
1507                         compatible = "allwinner,sun7i-a20-sid";
1508                         reg = <0x01c23800 0x200>;
1509                 };
1510
1511                 i2s2: i2s@01c24400 {
1512                         #sound-dai-cells = <0>;
1513                         compatible = "allwinner,sun4i-a10-i2s";
1514                         reg = <0x01c24400 0x400>;
1515                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1516                         clocks = <&apb0_gates 8>, <&i2s2_clk>;
1517                         clock-names = "apb", "mod";
1518                         dmas = <&dma SUN4I_DMA_NORMAL 6>,
1519                                <&dma SUN4I_DMA_NORMAL 6>;
1520                         dma-names = "rx", "tx";
1521                         status = "disabled";
1522                 };
1523
1524                 rtp: rtp@01c25000 {
1525                         compatible = "allwinner,sun5i-a13-ts";
1526                         reg = <0x01c25000 0x100>;
1527                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1528                         #thermal-sensor-cells = <0>;
1529                 };
1530
1531                 uart0: serial@01c28000 {
1532                         compatible = "snps,dw-apb-uart";
1533                         reg = <0x01c28000 0x400>;
1534                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1535                         reg-shift = <2>;
1536                         reg-io-width = <4>;
1537                         clocks = <&apb1_gates 16>;
1538                         status = "disabled";
1539                 };
1540
1541                 uart1: serial@01c28400 {
1542                         compatible = "snps,dw-apb-uart";
1543                         reg = <0x01c28400 0x400>;
1544                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1545                         reg-shift = <2>;
1546                         reg-io-width = <4>;
1547                         clocks = <&apb1_gates 17>;
1548                         status = "disabled";
1549                 };
1550
1551                 uart2: serial@01c28800 {
1552                         compatible = "snps,dw-apb-uart";
1553                         reg = <0x01c28800 0x400>;
1554                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1555                         reg-shift = <2>;
1556                         reg-io-width = <4>;
1557                         clocks = <&apb1_gates 18>;
1558                         status = "disabled";
1559                 };
1560
1561                 uart3: serial@01c28c00 {
1562                         compatible = "snps,dw-apb-uart";
1563                         reg = <0x01c28c00 0x400>;
1564                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1565                         reg-shift = <2>;
1566                         reg-io-width = <4>;
1567                         clocks = <&apb1_gates 19>;
1568                         status = "disabled";
1569                 };
1570
1571                 uart4: serial@01c29000 {
1572                         compatible = "snps,dw-apb-uart";
1573                         reg = <0x01c29000 0x400>;
1574                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1575                         reg-shift = <2>;
1576                         reg-io-width = <4>;
1577                         clocks = <&apb1_gates 20>;
1578                         status = "disabled";
1579                 };
1580
1581                 uart5: serial@01c29400 {
1582                         compatible = "snps,dw-apb-uart";
1583                         reg = <0x01c29400 0x400>;
1584                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1585                         reg-shift = <2>;
1586                         reg-io-width = <4>;
1587                         clocks = <&apb1_gates 21>;
1588                         status = "disabled";
1589                 };
1590
1591                 uart6: serial@01c29800 {
1592                         compatible = "snps,dw-apb-uart";
1593                         reg = <0x01c29800 0x400>;
1594                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1595                         reg-shift = <2>;
1596                         reg-io-width = <4>;
1597                         clocks = <&apb1_gates 22>;
1598                         status = "disabled";
1599                 };
1600
1601                 uart7: serial@01c29c00 {
1602                         compatible = "snps,dw-apb-uart";
1603                         reg = <0x01c29c00 0x400>;
1604                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1605                         reg-shift = <2>;
1606                         reg-io-width = <4>;
1607                         clocks = <&apb1_gates 23>;
1608                         status = "disabled";
1609                 };
1610
1611                 i2c0: i2c@01c2ac00 {
1612                         compatible = "allwinner,sun7i-a20-i2c",
1613                                      "allwinner,sun4i-a10-i2c";
1614                         reg = <0x01c2ac00 0x400>;
1615                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1616                         clocks = <&apb1_gates 0>;
1617                         status = "disabled";
1618                         #address-cells = <1>;
1619                         #size-cells = <0>;
1620                 };
1621
1622                 i2c1: i2c@01c2b000 {
1623                         compatible = "allwinner,sun7i-a20-i2c",
1624                                      "allwinner,sun4i-a10-i2c";
1625                         reg = <0x01c2b000 0x400>;
1626                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1627                         clocks = <&apb1_gates 1>;
1628                         status = "disabled";
1629                         #address-cells = <1>;
1630                         #size-cells = <0>;
1631                 };
1632
1633                 i2c2: i2c@01c2b400 {
1634                         compatible = "allwinner,sun7i-a20-i2c",
1635                                      "allwinner,sun4i-a10-i2c";
1636                         reg = <0x01c2b400 0x400>;
1637                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1638                         clocks = <&apb1_gates 2>;
1639                         status = "disabled";
1640                         #address-cells = <1>;
1641                         #size-cells = <0>;
1642                 };
1643
1644                 i2c3: i2c@01c2b800 {
1645                         compatible = "allwinner,sun7i-a20-i2c",
1646                                      "allwinner,sun4i-a10-i2c";
1647                         reg = <0x01c2b800 0x400>;
1648                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1649                         clocks = <&apb1_gates 3>;
1650                         status = "disabled";
1651                         #address-cells = <1>;
1652                         #size-cells = <0>;
1653                 };
1654
1655                 i2c4: i2c@01c2c000 {
1656                         compatible = "allwinner,sun7i-a20-i2c",
1657                                      "allwinner,sun4i-a10-i2c";
1658                         reg = <0x01c2c000 0x400>;
1659                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1660                         clocks = <&apb1_gates 15>;
1661                         status = "disabled";
1662                         #address-cells = <1>;
1663                         #size-cells = <0>;
1664                 };
1665
1666                 gmac: ethernet@01c50000 {
1667                         compatible = "allwinner,sun7i-a20-gmac";
1668                         reg = <0x01c50000 0x10000>;
1669                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1670                         interrupt-names = "macirq";
1671                         clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1672                         clock-names = "stmmaceth", "allwinner_gmac_tx";
1673                         snps,pbl = <2>;
1674                         snps,fixed-burst;
1675                         snps,force_sf_dma_mode;
1676                         status = "disabled";
1677                         #address-cells = <1>;
1678                         #size-cells = <0>;
1679                 };
1680
1681                 hstimer@01c60000 {
1682                         compatible = "allwinner,sun7i-a20-hstimer";
1683                         reg = <0x01c60000 0x1000>;
1684                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1685                                      <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1686                                      <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1687                                      <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1688                         clocks = <&ahb_gates 28>;
1689                 };
1690
1691                 gic: interrupt-controller@01c81000 {
1692                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1693                         reg = <0x01c81000 0x1000>,
1694                               <0x01c82000 0x1000>,
1695                               <0x01c84000 0x2000>,
1696                               <0x01c86000 0x2000>;
1697                         interrupt-controller;
1698                         #interrupt-cells = <3>;
1699                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1700                 };
1701
1702                 ps20: ps2@01c2a000 {
1703                         compatible = "allwinner,sun4i-a10-ps2";
1704                         reg = <0x01c2a000 0x400>;
1705                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1706                         clocks = <&apb1_gates 6>;
1707                         status = "disabled";
1708                 };
1709
1710                 ps21: ps2@01c2a400 {
1711                         compatible = "allwinner,sun4i-a10-ps2";
1712                         reg = <0x01c2a400 0x400>;
1713                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1714                         clocks = <&apb1_gates 7>;
1715                         status = "disabled";
1716                 };
1717         };
1718 };