git.sur5r.net Git - u-boot/blob - arch/arm/dts/sun7i-a20.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *     You should have received a copy of the GNU General Public
  22  *     License along with this file; if not, write to the Free
  23  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  24  *     MA 02110-1301 USA
  25  *
  26  * Or, alternatively,
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use,
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48  */
  49
  50 #include "skeleton.dtsi"
  51
  52 #include <dt-bindings/interrupt-controller/arm-gic.h>
  53 #include <dt-bindings/thermal/thermal.h>
  54
  55 #include <dt-bindings/dma/sun4i-a10.h>
  56 #include <dt-bindings/pinctrl/sun4i-a10.h>
  57
  58 / {
  59         interrupt-parent = <&gic>;
  60
  61         aliases {
  62                 ethernet0 = &gmac;
  63         };
  64
  65         chosen {
  66                 #address-cells = <1>;
  67                 #size-cells = <1>;
  68                 ranges;
  69
  70                 framebuffer@0 {
  71                         compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  72                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  73                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  74                                  <&ahb_gates 44>;
  75                         status = "disabled";
  76                 };
  77
  78                 framebuffer@1 {
  79                         compatible = "allwinner,simple-framebuffer",
  80                                      "simple-framebuffer";
  81                         allwinner,pipeline = "de_be0-lcd0";
  82                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
  83                         status = "disabled";
  84                 };
  85
  86                 framebuffer@2 {
  87                         compatible = "allwinner,simple-framebuffer",
  88                                      "simple-framebuffer";
  89                         allwinner,pipeline = "de_be0-lcd0-tve0";
  90                         clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
  91                                  <&ahb_gates 44>;
  92                         status = "disabled";
  93                 };
  94         };
  95
  96         cpus {
  97                 #address-cells = <1>;
  98                 #size-cells = <0>;
  99
 100                 cpu0: cpu@0 {
 101                         compatible = "arm,cortex-a7";
 102                         device_type = "cpu";
 103                         reg = <0>;
 104                         clocks = <&cpu>;
 105                         clock-latency = <244144>; /* 8 32k periods */
 106                         operating-points = <
 107                                 /* kHz    uV */
 108                                 960000  1400000
 109                                 912000  1400000
 110                                 864000  1300000
 111                                 720000  1200000
 112                                 528000  1100000
 113                                 312000  1000000
 114                                 144000  900000
 115                                 >;
 116                         #cooling-cells = <2>;
 117                         cooling-min-level = <0>;
 118                         cooling-max-level = <6>;
 119                 };
 120
 121                 cpu@1 {
 122                         compatible = "arm,cortex-a7";
 123                         device_type = "cpu";
 124                         reg = <1>;
 125                 };
 126         };
 127
 128         thermal-zones {
 129                 cpu_thermal {
 130                         /* milliseconds */
 131                         polling-delay-passive = <250>;
 132                         polling-delay = <1000>;
 133                         thermal-sensors = <&rtp>;
 134
 135                         cooling-maps {
 136                                 map0 {
 137                                         trip = <&cpu_alert0>;
 138                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 139                                 };
 140                         };
 141
 142                         trips {
 143                                 cpu_alert0: cpu_alert0 {
 144                                         /* milliCelsius */
 145                                         temperature = <75000>;
 146                                         hysteresis = <2000>;
 147                                         type = "passive";
 148                                 };
 149
 150                                 cpu_crit: cpu_crit {
 151                                         /* milliCelsius */
 152                                         temperature = <100000>;
 153                                         hysteresis = <2000>;
 154                                         type = "critical";
 155                                 };
 156                         };
 157                 };
 158         };
 159
 160         memory {
 161                 reg = <0x40000000 0x80000000>;
 162         };
 163
 164         timer {
 165                 compatible = "arm,armv7-timer";
 166                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 167                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 168                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 169                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 170         };
 171
 172         pmu {
 173                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
 174                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 176         };
 177
 178         clocks {
 179                 #address-cells = <1>;
 180                 #size-cells = <1>;
 181                 ranges;
 182
 183                 osc24M: clk@01c20050 {
 184                         #clock-cells = <0>;
 185                         compatible = "allwinner,sun4i-a10-osc-clk";
 186                         reg = <0x01c20050 0x4>;
 187                         clock-frequency = <24000000>;
 188                         clock-output-names = "osc24M";
 189                 };
 190
 191                 osc32k: clk@0 {
 192                         #clock-cells = <0>;
 193                         compatible = "fixed-clock";
 194                         clock-frequency = <32768>;
 195                         clock-output-names = "osc32k";
 196                 };
 197
 198                 pll1: clk@01c20000 {
 199                         #clock-cells = <0>;
 200                         compatible = "allwinner,sun4i-a10-pll1-clk";
 201                         reg = <0x01c20000 0x4>;
 202                         clocks = <&osc24M>;
 203                         clock-output-names = "pll1";
 204                 };
 205
 206                 pll4: clk@01c20018 {
 207                         #clock-cells = <0>;
 208                         compatible = "allwinner,sun7i-a20-pll4-clk";
 209                         reg = <0x01c20018 0x4>;
 210                         clocks = <&osc24M>;
 211                         clock-output-names = "pll4";
 212                 };
 213
 214                 pll5: clk@01c20020 {
 215                         #clock-cells = <1>;
 216                         compatible = "allwinner,sun4i-a10-pll5-clk";
 217                         reg = <0x01c20020 0x4>;
 218                         clocks = <&osc24M>;
 219                         clock-output-names = "pll5_ddr", "pll5_other";
 220                 };
 221
 222                 pll6: clk@01c20028 {
 223                         #clock-cells = <1>;
 224                         compatible = "allwinner,sun4i-a10-pll6-clk";
 225                         reg = <0x01c20028 0x4>;
 226                         clocks = <&osc24M>;
 227                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 228                 };
 229
 230                 pll8: clk@01c20040 {
 231                         #clock-cells = <0>;
 232                         compatible = "allwinner,sun7i-a20-pll4-clk";
 233                         reg = <0x01c20040 0x4>;
 234                         clocks = <&osc24M>;
 235                         clock-output-names = "pll8";
 236                 };
 237
 238                 cpu: cpu@01c20054 {
 239                         #clock-cells = <0>;
 240                         compatible = "allwinner,sun4i-a10-cpu-clk";
 241                         reg = <0x01c20054 0x4>;
 242                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
 243                         clock-output-names = "cpu";
 244                 };
 245
 246                 axi: axi@01c20054 {
 247                         #clock-cells = <0>;
 248                         compatible = "allwinner,sun4i-a10-axi-clk";
 249                         reg = <0x01c20054 0x4>;
 250                         clocks = <&cpu>;
 251                         clock-output-names = "axi";
 252                 };
 253
 254                 ahb: ahb@01c20054 {
 255                         #clock-cells = <0>;
 256                         compatible = "allwinner,sun4i-a10-ahb-clk";
 257                         reg = <0x01c20054 0x4>;
 258                         clocks = <&axi>;
 259                         clock-output-names = "ahb";
 260                 };
 261
 262                 ahb_gates: clk@01c20060 {
 263                         #clock-cells = <1>;
 264                         compatible = "allwinner,sun7i-a20-ahb-gates-clk";
 265                         reg = <0x01c20060 0x8>;
 266                         clocks = <&ahb>;
 267                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 268                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
 269                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 270                                 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
 271                                 "ahb_nand", "ahb_sdram", "ahb_ace",
 272                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 273                                 "ahb_spi2", "ahb_spi3", "ahb_sata",
 274                                 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
 275                                 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
 276                                 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
 277                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 278                                 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
 279                                 "ahb_mali";
 280                 };
 281
 282                 apb0: apb0@01c20054 {
 283                         #clock-cells = <0>;
 284                         compatible = "allwinner,sun4i-a10-apb0-clk";
 285                         reg = <0x01c20054 0x4>;
 286                         clocks = <&ahb>;
 287                         clock-output-names = "apb0";
 288                 };
 289
 290                 apb0_gates: clk@01c20068 {
 291                         #clock-cells = <1>;
 292                         compatible = "allwinner,sun7i-a20-apb0-gates-clk";
 293                         reg = <0x01c20068 0x4>;
 294                         clocks = <&apb0>;
 295                         clock-output-names = "apb0_codec", "apb0_spdif",
 296                                 "apb0_ac97", "apb0_iis0", "apb0_iis1",
 297                                 "apb0_pio", "apb0_ir0", "apb0_ir1",
 298                                 "apb0_iis2", "apb0_keypad";
 299                 };
 300
 301                 apb1: clk@01c20058 {
 302                         #clock-cells = <0>;
 303                         compatible = "allwinner,sun4i-a10-apb1-clk";
 304                         reg = <0x01c20058 0x4>;
 305                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 306                         clock-output-names = "apb1";
 307                 };
 308
 309                 apb1_gates: clk@01c2006c {
 310                         #clock-cells = <1>;
 311                         compatible = "allwinner,sun7i-a20-apb1-gates-clk";
 312                         reg = <0x01c2006c 0x4>;
 313                         clocks = <&apb1>;
 314                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 315                                 "apb1_i2c2", "apb1_i2c3", "apb1_can",
 316                                 "apb1_scr", "apb1_ps20", "apb1_ps21",
 317                                 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
 318                                 "apb1_uart2", "apb1_uart3", "apb1_uart4",
 319                                 "apb1_uart5", "apb1_uart6", "apb1_uart7";
 320                 };
 321
 322                 nand_clk: clk@01c20080 {
 323                         #clock-cells = <0>;
 324                         compatible = "allwinner,sun4i-a10-mod0-clk";
 325                         reg = <0x01c20080 0x4>;
 326                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 327                         clock-output-names = "nand";
 328                 };
 329
 330                 ms_clk: clk@01c20084 {
 331                         #clock-cells = <0>;
 332                         compatible = "allwinner,sun4i-a10-mod0-clk";
 333                         reg = <0x01c20084 0x4>;
 334                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 335                         clock-output-names = "ms";
 336                 };
 337
 338                 mmc0_clk: clk@01c20088 {
 339                         #clock-cells = <1>;
 340                         compatible = "allwinner,sun4i-a10-mmc-clk";
 341                         reg = <0x01c20088 0x4>;
 342                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 343                         clock-output-names = "mmc0",
 344                                              "mmc0_output",
 345                                              "mmc0_sample";
 346                 };
 347
 348                 mmc1_clk: clk@01c2008c {
 349                         #clock-cells = <1>;
 350                         compatible = "allwinner,sun4i-a10-mmc-clk";
 351                         reg = <0x01c2008c 0x4>;
 352                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 353                         clock-output-names = "mmc1",
 354                                              "mmc1_output",
 355                                              "mmc1_sample";
 356                 };
 357
 358                 mmc2_clk: clk@01c20090 {
 359                         #clock-cells = <1>;
 360                         compatible = "allwinner,sun4i-a10-mmc-clk";
 361                         reg = <0x01c20090 0x4>;
 362                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 363                         clock-output-names = "mmc2",
 364                                              "mmc2_output",
 365                                              "mmc2_sample";
 366                 };
 367
 368                 mmc3_clk: clk@01c20094 {
 369                         #clock-cells = <1>;
 370                         compatible = "allwinner,sun4i-a10-mmc-clk";
 371                         reg = <0x01c20094 0x4>;
 372                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 373                         clock-output-names = "mmc3",
 374                                              "mmc3_output",
 375                                              "mmc3_sample";
 376                 };
 377
 378                 ts_clk: clk@01c20098 {
 379                         #clock-cells = <0>;
 380                         compatible = "allwinner,sun4i-a10-mod0-clk";
 381                         reg = <0x01c20098 0x4>;
 382                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 383                         clock-output-names = "ts";
 384                 };
 385
 386                 ss_clk: clk@01c2009c {
 387                         #clock-cells = <0>;
 388                         compatible = "allwinner,sun4i-a10-mod0-clk";
 389                         reg = <0x01c2009c 0x4>;
 390                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 391                         clock-output-names = "ss";
 392                 };
 393
 394                 spi0_clk: clk@01c200a0 {
 395                         #clock-cells = <0>;
 396                         compatible = "allwinner,sun4i-a10-mod0-clk";
 397                         reg = <0x01c200a0 0x4>;
 398                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 399                         clock-output-names = "spi0";
 400                 };
 401
 402                 spi1_clk: clk@01c200a4 {
 403                         #clock-cells = <0>;
 404                         compatible = "allwinner,sun4i-a10-mod0-clk";
 405                         reg = <0x01c200a4 0x4>;
 406                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 407                         clock-output-names = "spi1";
 408                 };
 409
 410                 spi2_clk: clk@01c200a8 {
 411                         #clock-cells = <0>;
 412                         compatible = "allwinner,sun4i-a10-mod0-clk";
 413                         reg = <0x01c200a8 0x4>;
 414                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 415                         clock-output-names = "spi2";
 416                 };
 417
 418                 pata_clk: clk@01c200ac {
 419                         #clock-cells = <0>;
 420                         compatible = "allwinner,sun4i-a10-mod0-clk";
 421                         reg = <0x01c200ac 0x4>;
 422                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 423                         clock-output-names = "pata";
 424                 };
 425
 426                 ir0_clk: clk@01c200b0 {
 427                         #clock-cells = <0>;
 428                         compatible = "allwinner,sun4i-a10-mod0-clk";
 429                         reg = <0x01c200b0 0x4>;
 430                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 431                         clock-output-names = "ir0";
 432                 };
 433
 434                 ir1_clk: clk@01c200b4 {
 435                         #clock-cells = <0>;
 436                         compatible = "allwinner,sun4i-a10-mod0-clk";
 437                         reg = <0x01c200b4 0x4>;
 438                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 439                         clock-output-names = "ir1";
 440                 };
 441
 442                 usb_clk: clk@01c200cc {
 443                         #clock-cells = <1>;
 444                         #reset-cells = <1>;
 445                         compatible = "allwinner,sun4i-a10-usb-clk";
 446                         reg = <0x01c200cc 0x4>;
 447                         clocks = <&pll6 1>;
 448                         clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
 449                 };
 450
 451                 spi3_clk: clk@01c200d4 {
 452                         #clock-cells = <0>;
 453                         compatible = "allwinner,sun4i-a10-mod0-clk";
 454                         reg = <0x01c200d4 0x4>;
 455                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 456                         clock-output-names = "spi3";
 457                 };
 458
 459                 mbus_clk: clk@01c2015c {
 460                         #clock-cells = <0>;
 461                         compatible = "allwinner,sun5i-a13-mbus-clk";
 462                         reg = <0x01c2015c 0x4>;
 463                         clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
 464                         clock-output-names = "mbus";
 465                 };
 466
 467                 /*
 468                  * The following two are dummy clocks, placeholders used in the gmac_tx
 469                  * clock. The gmac driver will choose one parent depending on the PHY
 470                  * interface mode, using clk_set_rate auto-reparenting.
 471                  * The actual TX clock rate is not controlled by the gmac_tx clock.
 472                  */
 473                 mii_phy_tx_clk: clk@2 {
 474                         #clock-cells = <0>;
 475                         compatible = "fixed-clock";
 476                         clock-frequency = <25000000>;
 477                         clock-output-names = "mii_phy_tx";
 478                 };
 479
 480                 gmac_int_tx_clk: clk@3 {
 481                         #clock-cells = <0>;
 482                         compatible = "fixed-clock";
 483                         clock-frequency = <125000000>;
 484                         clock-output-names = "gmac_int_tx";
 485                 };
 486
 487                 gmac_tx_clk: clk@01c20164 {
 488                         #clock-cells = <0>;
 489                         compatible = "allwinner,sun7i-a20-gmac-clk";
 490                         reg = <0x01c20164 0x4>;
 491                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 492                         clock-output-names = "gmac_tx";
 493                 };
 494
 495                 /*
 496                  * Dummy clock used by output clocks
 497                  */
 498                 osc24M_32k: clk@1 {
 499                         #clock-cells = <0>;
 500                         compatible = "fixed-factor-clock";
 501                         clock-div = <750>;
 502                         clock-mult = <1>;
 503                         clocks = <&osc24M>;
 504                         clock-output-names = "osc24M_32k";
 505                 };
 506
 507                 clk_out_a: clk@01c201f0 {
 508                         #clock-cells = <0>;
 509                         compatible = "allwinner,sun7i-a20-out-clk";
 510                         reg = <0x01c201f0 0x4>;
 511                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 512                         clock-output-names = "clk_out_a";
 513                 };
 514
 515                 clk_out_b: clk@01c201f4 {
 516                         #clock-cells = <0>;
 517                         compatible = "allwinner,sun7i-a20-out-clk";
 518                         reg = <0x01c201f4 0x4>;
 519                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 520                         clock-output-names = "clk_out_b";
 521                 };
 522         };
 523
 524         /*
 525          * Note we use the address where the mmio registers start, not where
 526          * the SRAM blocks start, this cannot be changed because that would be
 527          * a devicetree ABI change.
 528          */
 529         soc@01c00000 {
 530                 compatible = "simple-bus";
 531                 #address-cells = <1>;
 532                 #size-cells = <1>;
 533                 ranges;
 534
 535                 sram@00000000 {
 536                         compatible = "allwinner,sun4i-a10-sram";
 537                         reg = <0x00000000 0x4000>;
 538                         allwinner,sram-name = "A1";
 539                 };
 540
 541                 sram@00004000 {
 542                         compatible = "allwinner,sun4i-a10-sram";
 543                         reg = <0x00004000 0x4000>;
 544                         allwinner,sram-name = "A2";
 545                 };
 546
 547                 sram@00008000 {
 548                         compatible = "allwinner,sun4i-a10-sram";
 549                         reg = <0x00008000 0x4000>;
 550                         allwinner,sram-name = "A3-A4";
 551                 };
 552
 553                 sram@00010000 {
 554                         compatible = "allwinner,sun4i-a10-sram";
 555                         reg = <0x00010000 0x1000>;
 556                         allwinner,sram-name = "D";
 557                 };
 558
 559                 sram-controller@01c00000 {
 560                         compatible = "allwinner,sun4i-a10-sram-controller";
 561                         reg = <0x01c00000 0x30>;
 562                 };
 563
 564                 nmi_intc: interrupt-controller@01c00030 {
 565                         compatible = "allwinner,sun7i-a20-sc-nmi";
 566                         interrupt-controller;
 567                         #interrupt-cells = <2>;
 568                         reg = <0x01c00030 0x0c>;
 569                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 570                 };
 571
 572                 dma: dma-controller@01c02000 {
 573                         compatible = "allwinner,sun4i-a10-dma";
 574                         reg = <0x01c02000 0x1000>;
 575                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 576                         clocks = <&ahb_gates 6>;
 577                         #dma-cells = <2>;
 578                 };
 579
 580                 spi0: spi@01c05000 {
 581                         compatible = "allwinner,sun4i-a10-spi";
 582                         reg = <0x01c05000 0x1000>;
 583                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 584                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 585                         clock-names = "ahb", "mod";
 586                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 587                                <&dma SUN4I_DMA_DEDICATED 26>;
 588                         dma-names = "rx", "tx";
 589                         status = "disabled";
 590                         #address-cells = <1>;
 591                         #size-cells = <0>;
 592                 };
 593
 594                 spi1: spi@01c06000 {
 595                         compatible = "allwinner,sun4i-a10-spi";
 596                         reg = <0x01c06000 0x1000>;
 597                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 598                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 599                         clock-names = "ahb", "mod";
 600                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 601                                <&dma SUN4I_DMA_DEDICATED 8>;
 602                         dma-names = "rx", "tx";
 603                         status = "disabled";
 604                         #address-cells = <1>;
 605                         #size-cells = <0>;
 606                 };
 607
 608                 emac: ethernet@01c0b000 {
 609                         compatible = "allwinner,sun4i-a10-emac";
 610                         reg = <0x01c0b000 0x1000>;
 611                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 612                         clocks = <&ahb_gates 17>;
 613                         status = "disabled";
 614                 };
 615
 616                 mdio: mdio@01c0b080 {
 617                         compatible = "allwinner,sun4i-a10-mdio";
 618                         reg = <0x01c0b080 0x14>;
 619                         status = "disabled";
 620                         #address-cells = <1>;
 621                         #size-cells = <0>;
 622                 };
 623
 624                 mmc0: mmc@01c0f000 {
 625                         compatible = "allwinner,sun5i-a13-mmc";
 626                         reg = <0x01c0f000 0x1000>;
 627                         clocks = <&ahb_gates 8>,
 628                                  <&mmc0_clk 0>,
 629                                  <&mmc0_clk 1>,
 630                                  <&mmc0_clk 2>;
 631                         clock-names = "ahb",
 632                                       "mmc",
 633                                       "output",
 634                                       "sample";
 635                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 636                         status = "disabled";
 637                         #address-cells = <1>;
 638                         #size-cells = <0>;
 639                 };
 640
 641                 mmc1: mmc@01c10000 {
 642                         compatible = "allwinner,sun5i-a13-mmc";
 643                         reg = <0x01c10000 0x1000>;
 644                         clocks = <&ahb_gates 9>,
 645                                  <&mmc1_clk 0>,
 646                                  <&mmc1_clk 1>,
 647                                  <&mmc1_clk 2>;
 648                         clock-names = "ahb",
 649                                       "mmc",
 650                                       "output",
 651                                       "sample";
 652                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 653                         status = "disabled";
 654                         #address-cells = <1>;
 655                         #size-cells = <0>;
 656                 };
 657
 658                 mmc2: mmc@01c11000 {
 659                         compatible = "allwinner,sun5i-a13-mmc";
 660                         reg = <0x01c11000 0x1000>;
 661                         clocks = <&ahb_gates 10>,
 662                                  <&mmc2_clk 0>,
 663                                  <&mmc2_clk 1>,
 664                                  <&mmc2_clk 2>;
 665                         clock-names = "ahb",
 666                                       "mmc",
 667                                       "output",
 668                                       "sample";
 669                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 670                         status = "disabled";
 671                         #address-cells = <1>;
 672                         #size-cells = <0>;
 673                 };
 674
 675                 mmc3: mmc@01c12000 {
 676                         compatible = "allwinner,sun5i-a13-mmc";
 677                         reg = <0x01c12000 0x1000>;
 678                         clocks = <&ahb_gates 11>,
 679                                  <&mmc3_clk 0>,
 680                                  <&mmc3_clk 1>,
 681                                  <&mmc3_clk 2>;
 682                         clock-names = "ahb",
 683                                       "mmc",
 684                                       "output",
 685                                       "sample";
 686                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 687                         status = "disabled";
 688                         #address-cells = <1>;
 689                         #size-cells = <0>;
 690                 };
 691
 692                 usbphy: phy@01c13400 {
 693                         #phy-cells = <1>;
 694                         compatible = "allwinner,sun7i-a20-usb-phy";
 695                         reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
 696                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 697                         clocks = <&usb_clk 8>;
 698                         clock-names = "usb_phy";
 699                         resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
 700                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 701                         status = "disabled";
 702                 };
 703
 704                 ehci0: usb@01c14000 {
 705                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 706                         reg = <0x01c14000 0x100>;
 707                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 708                         clocks = <&ahb_gates 1>;
 709                         phys = <&usbphy 1>;
 710                         phy-names = "usb";
 711                         status = "disabled";
 712                 };
 713
 714                 ohci0: usb@01c14400 {
 715                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 716                         reg = <0x01c14400 0x100>;
 717                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 718                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 719                         phys = <&usbphy 1>;
 720                         phy-names = "usb";
 721                         status = "disabled";
 722                 };
 723
 724                 spi2: spi@01c17000 {
 725                         compatible = "allwinner,sun4i-a10-spi";
 726                         reg = <0x01c17000 0x1000>;
 727                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 728                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 729                         clock-names = "ahb", "mod";
 730                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 731                                <&dma SUN4I_DMA_DEDICATED 28>;
 732                         dma-names = "rx", "tx";
 733                         status = "disabled";
 734                         #address-cells = <1>;
 735                         #size-cells = <0>;
 736                 };
 737
 738                 ahci: sata@01c18000 {
 739                         compatible = "allwinner,sun4i-a10-ahci";
 740                         reg = <0x01c18000 0x1000>;
 741                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 742                         clocks = <&pll6 0>, <&ahb_gates 25>;
 743                         status = "disabled";
 744                 };
 745
 746                 ehci1: usb@01c1c000 {
 747                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 748                         reg = <0x01c1c000 0x100>;
 749                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 750                         clocks = <&ahb_gates 3>;
 751                         phys = <&usbphy 2>;
 752                         phy-names = "usb";
 753                         status = "disabled";
 754                 };
 755
 756                 ohci1: usb@01c1c400 {
 757                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 758                         reg = <0x01c1c400 0x100>;
 759                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 760                         clocks = <&usb_clk 7>, <&ahb_gates 4>;
 761                         phys = <&usbphy 2>;
 762                         phy-names = "usb";
 763                         status = "disabled";
 764                 };
 765
 766                 spi3: spi@01c1f000 {
 767                         compatible = "allwinner,sun4i-a10-spi";
 768                         reg = <0x01c1f000 0x1000>;
 769                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 770                         clocks = <&ahb_gates 23>, <&spi3_clk>;
 771                         clock-names = "ahb", "mod";
 772                         dmas = <&dma SUN4I_DMA_DEDICATED 31>,
 773                                <&dma SUN4I_DMA_DEDICATED 30>;
 774                         dma-names = "rx", "tx";
 775                         status = "disabled";
 776                         #address-cells = <1>;
 777                         #size-cells = <0>;
 778                 };
 779
 780                 pio: pinctrl@01c20800 {
 781                         compatible = "allwinner,sun7i-a20-pinctrl";
 782                         reg = <0x01c20800 0x400>;
 783                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 784                         clocks = <&apb0_gates 5>;
 785                         gpio-controller;
 786                         interrupt-controller;
 787                         #interrupt-cells = <2>;
 788                         #size-cells = <0>;
 789                         #gpio-cells = <3>;
 790
 791                         pwm0_pins_a: pwm0@0 {
 792                                 allwinner,pins = "PB2";
 793                                 allwinner,function = "pwm";
 794                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 795                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 796                         };
 797
 798                         pwm1_pins_a: pwm1@0 {
 799                                 allwinner,pins = "PI3";
 800                                 allwinner,function = "pwm";
 801                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 802                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 803                         };
 804
 805                         uart0_pins_a: uart0@0 {
 806                                 allwinner,pins = "PB22", "PB23";
 807                                 allwinner,function = "uart0";
 808                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 809                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 810                         };
 811
 812                         uart2_pins_a: uart2@0 {
 813                                 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
 814                                 allwinner,function = "uart2";
 815                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 816                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 817                         };
 818
 819                         uart3_pins_a: uart3@0 {
 820                                 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
 821                                 allwinner,function = "uart3";
 822                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 823                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 824                         };
 825
 826                         uart3_pins_b: uart3@1 {
 827                                 allwinner,pins = "PH0", "PH1";
 828                                 allwinner,function = "uart3";
 829                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 830                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 831                         };
 832
 833                         uart4_pins_a: uart4@0 {
 834                                 allwinner,pins = "PG10", "PG11";
 835                                 allwinner,function = "uart4";
 836                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 837                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 838                         };
 839
 840                         uart5_pins_a: uart5@0 {
 841                                 allwinner,pins = "PI10", "PI11";
 842                                 allwinner,function = "uart5";
 843                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 844                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 845                         };
 846
 847                         uart6_pins_a: uart6@0 {
 848                                 allwinner,pins = "PI12", "PI13";
 849                                 allwinner,function = "uart6";
 850                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 851                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 852                         };
 853
 854                         uart7_pins_a: uart7@0 {
 855                                 allwinner,pins = "PI20", "PI21";
 856                                 allwinner,function = "uart7";
 857                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 858                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 859                         };
 860
 861                         i2c0_pins_a: i2c0@0 {
 862                                 allwinner,pins = "PB0", "PB1";
 863                                 allwinner,function = "i2c0";
 864                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 865                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 866                         };
 867
 868                         i2c1_pins_a: i2c1@0 {
 869                                 allwinner,pins = "PB18", "PB19";
 870                                 allwinner,function = "i2c1";
 871                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 872                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 873                         };
 874
 875                         i2c2_pins_a: i2c2@0 {
 876                                 allwinner,pins = "PB20", "PB21";
 877                                 allwinner,function = "i2c2";
 878                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 879                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 880                         };
 881
 882                         i2c3_pins_a: i2c3@0 {
 883                                 allwinner,pins = "PI0", "PI1";
 884                                 allwinner,function = "i2c3";
 885                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 886                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 887                         };
 888
 889                         emac_pins_a: emac0@0 {
 890                                 allwinner,pins = "PA0", "PA1", "PA2",
 891                                                 "PA3", "PA4", "PA5", "PA6",
 892                                                 "PA7", "PA8", "PA9", "PA10",
 893                                                 "PA11", "PA12", "PA13", "PA14",
 894                                                 "PA15", "PA16";
 895                                 allwinner,function = "emac";
 896                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 897                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 898                         };
 899
 900                         clk_out_a_pins_a: clk_out_a@0 {
 901                                 allwinner,pins = "PI12";
 902                                 allwinner,function = "clk_out_a";
 903                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 904                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 905                         };
 906
 907                         clk_out_b_pins_a: clk_out_b@0 {
 908                                 allwinner,pins = "PI13";
 909                                 allwinner,function = "clk_out_b";
 910                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 911                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 912                         };
 913
 914                         gmac_pins_mii_a: gmac_mii@0 {
 915                                 allwinner,pins = "PA0", "PA1", "PA2",
 916                                                 "PA3", "PA4", "PA5", "PA6",
 917                                                 "PA7", "PA8", "PA9", "PA10",
 918                                                 "PA11", "PA12", "PA13", "PA14",
 919                                                 "PA15", "PA16";
 920                                 allwinner,function = "gmac";
 921                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 922                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 923                         };
 924
 925                         gmac_pins_rgmii_a: gmac_rgmii@0 {
 926                                 allwinner,pins = "PA0", "PA1", "PA2",
 927                                                 "PA3", "PA4", "PA5", "PA6",
 928                                                 "PA7", "PA8", "PA10",
 929                                                 "PA11", "PA12", "PA13",
 930                                                 "PA15", "PA16";
 931                                 allwinner,function = "gmac";
 932                                 /*
 933                                  * data lines in RGMII mode use DDR mode
 934                                  * and need a higher signal drive strength
 935                                  */
 936                                 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
 937                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 938                         };
 939
 940                         spi0_pins_a: spi0@0 {
 941                                 allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14";
 942                                 allwinner,function = "spi0";
 943                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 944                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 945                         };
 946
 947                         spi1_pins_a: spi1@0 {
 948                                 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
 949                                 allwinner,function = "spi1";
 950                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 951                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 952                         };
 953
 954                         spi2_pins_a: spi2@0 {
 955                                 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
 956                                 allwinner,function = "spi2";
 957                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 958                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 959                         };
 960
 961                         spi2_pins_b: spi2@1 {
 962                                 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
 963                                 allwinner,function = "spi2";
 964                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 965                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 966                         };
 967
 968                         mmc0_pins_a: mmc0@0 {
 969                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 970                                 allwinner,function = "mmc0";
 971                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 972                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 973                         };
 974
 975                         mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
 976                                 allwinner,pins = "PH1";
 977                                 allwinner,function = "gpio_in";
 978                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 979                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 980                         };
 981
 982                         mmc2_pins_a: mmc2@0 {
 983                                 allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11";
 984                                 allwinner,function = "mmc2";
 985                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 986                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 987                         };
 988
 989                         mmc3_pins_a: mmc3@0 {
 990                                 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
 991                                 allwinner,function = "mmc3";
 992                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 993                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 994                         };
 995
 996                         ir0_pins_a: ir0@0 {
 997                                     allwinner,pins = "PB3","PB4";
 998                                     allwinner,function = "ir0";
 999                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1000                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1001                         };
1002
1003                         ir1_pins_a: ir1@0 {
1004                                     allwinner,pins = "PB22","PB23";
1005                                     allwinner,function = "ir1";
1006                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1007                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1008                         };
1009
1010                         ps20_pins_a: ps20@0 {
1011                                 allwinner,pins = "PI20", "PI21";
1012                                 allwinner,function = "ps2";
1013                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1014                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1015                         };
1016
1017                         ps21_pins_a: ps21@0 {
1018                                 allwinner,pins = "PH12", "PH13";
1019                                 allwinner,function = "ps2";
1020                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1021                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1022                         };
1023                 };
1024
1025                 timer@01c20c00 {
1026                         compatible = "allwinner,sun4i-a10-timer";
1027                         reg = <0x01c20c00 0x90>;
1028                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1029                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1030                                      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1031                                      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1032                                      <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1033                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1034                         clocks = <&osc24M>;
1035                 };
1036
1037                 wdt: watchdog@01c20c90 {
1038                         compatible = "allwinner,sun4i-a10-wdt";
1039                         reg = <0x01c20c90 0x10>;
1040                 };
1041
1042                 rtc: rtc@01c20d00 {
1043                         compatible = "allwinner,sun7i-a20-rtc";
1044                         reg = <0x01c20d00 0x20>;
1045                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1046                 };
1047
1048                 pwm: pwm@01c20e00 {
1049                         compatible = "allwinner,sun7i-a20-pwm";
1050                         reg = <0x01c20e00 0xc>;
1051                         clocks = <&osc24M>;
1052                         #pwm-cells = <3>;
1053                         status = "disabled";
1054                 };
1055
1056                 ir0: ir@01c21800 {
1057                         compatible = "allwinner,sun4i-a10-ir";
1058                         clocks = <&apb0_gates 6>, <&ir0_clk>;
1059                         clock-names = "apb", "ir";
1060                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1061                         reg = <0x01c21800 0x40>;
1062                         status = "disabled";
1063                 };
1064
1065                 ir1: ir@01c21c00 {
1066                         compatible = "allwinner,sun4i-a10-ir";
1067                         clocks = <&apb0_gates 7>, <&ir1_clk>;
1068                         clock-names = "apb", "ir";
1069                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1070                         reg = <0x01c21c00 0x40>;
1071                         status = "disabled";
1072                 };
1073
1074                 lradc: lradc@01c22800 {
1075                         compatible = "allwinner,sun4i-a10-lradc-keys";
1076                         reg = <0x01c22800 0x100>;
1077                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1078                         status = "disabled";
1079                 };
1080
1081                 sid: eeprom@01c23800 {
1082                         compatible = "allwinner,sun7i-a20-sid";
1083                         reg = <0x01c23800 0x200>;
1084                 };
1085
1086                 rtp: rtp@01c25000 {
1087                         compatible = "allwinner,sun5i-a13-ts";
1088                         reg = <0x01c25000 0x100>;
1089                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1090                         #thermal-sensor-cells = <0>;
1091                 };
1092
1093                 uart0: serial@01c28000 {
1094                         compatible = "snps,dw-apb-uart";
1095                         reg = <0x01c28000 0x400>;
1096                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1097                         reg-shift = <2>;
1098                         reg-io-width = <4>;
1099                         clocks = <&apb1_gates 16>;
1100                         status = "disabled";
1101                 };
1102
1103                 uart1: serial@01c28400 {
1104                         compatible = "snps,dw-apb-uart";
1105                         reg = <0x01c28400 0x400>;
1106                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1107                         reg-shift = <2>;
1108                         reg-io-width = <4>;
1109                         clocks = <&apb1_gates 17>;
1110                         status = "disabled";
1111                 };
1112
1113                 uart2: serial@01c28800 {
1114                         compatible = "snps,dw-apb-uart";
1115                         reg = <0x01c28800 0x400>;
1116                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1117                         reg-shift = <2>;
1118                         reg-io-width = <4>;
1119                         clocks = <&apb1_gates 18>;
1120                         status = "disabled";
1121                 };
1122
1123                 uart3: serial@01c28c00 {
1124                         compatible = "snps,dw-apb-uart";
1125                         reg = <0x01c28c00 0x400>;
1126                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1127                         reg-shift = <2>;
1128                         reg-io-width = <4>;
1129                         clocks = <&apb1_gates 19>;
1130                         status = "disabled";
1131                 };
1132
1133                 uart4: serial@01c29000 {
1134                         compatible = "snps,dw-apb-uart";
1135                         reg = <0x01c29000 0x400>;
1136                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1137                         reg-shift = <2>;
1138                         reg-io-width = <4>;
1139                         clocks = <&apb1_gates 20>;
1140                         status = "disabled";
1141                 };
1142
1143                 uart5: serial@01c29400 {
1144                         compatible = "snps,dw-apb-uart";
1145                         reg = <0x01c29400 0x400>;
1146                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1147                         reg-shift = <2>;
1148                         reg-io-width = <4>;
1149                         clocks = <&apb1_gates 21>;
1150                         status = "disabled";
1151                 };
1152
1153                 uart6: serial@01c29800 {
1154                         compatible = "snps,dw-apb-uart";
1155                         reg = <0x01c29800 0x400>;
1156                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1157                         reg-shift = <2>;
1158                         reg-io-width = <4>;
1159                         clocks = <&apb1_gates 22>;
1160                         status = "disabled";
1161                 };
1162
1163                 uart7: serial@01c29c00 {
1164                         compatible = "snps,dw-apb-uart";
1165                         reg = <0x01c29c00 0x400>;
1166                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1167                         reg-shift = <2>;
1168                         reg-io-width = <4>;
1169                         clocks = <&apb1_gates 23>;
1170                         status = "disabled";
1171                 };
1172
1173                 i2c0: i2c@01c2ac00 {
1174                         compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1175                         reg = <0x01c2ac00 0x400>;
1176                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1177                         clocks = <&apb1_gates 0>;
1178                         status = "disabled";
1179                         #address-cells = <1>;
1180                         #size-cells = <0>;
1181                 };
1182
1183                 i2c1: i2c@01c2b000 {
1184                         compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1185                         reg = <0x01c2b000 0x400>;
1186                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1187                         clocks = <&apb1_gates 1>;
1188                         status = "disabled";
1189                         #address-cells = <1>;
1190                         #size-cells = <0>;
1191                 };
1192
1193                 i2c2: i2c@01c2b400 {
1194                         compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1195                         reg = <0x01c2b400 0x400>;
1196                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1197                         clocks = <&apb1_gates 2>;
1198                         status = "disabled";
1199                         #address-cells = <1>;
1200                         #size-cells = <0>;
1201                 };
1202
1203                 i2c3: i2c@01c2b800 {
1204                         compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1205                         reg = <0x01c2b800 0x400>;
1206                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1207                         clocks = <&apb1_gates 3>;
1208                         status = "disabled";
1209                         #address-cells = <1>;
1210                         #size-cells = <0>;
1211                 };
1212
1213                 i2c4: i2c@01c2c000 {
1214                         compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1215                         reg = <0x01c2c000 0x400>;
1216                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1217                         clocks = <&apb1_gates 15>;
1218                         status = "disabled";
1219                         #address-cells = <1>;
1220                         #size-cells = <0>;
1221                 };
1222
1223                 gmac: ethernet@01c50000 {
1224                         compatible = "allwinner,sun7i-a20-gmac";
1225                         reg = <0x01c50000 0x10000>;
1226                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1227                         interrupt-names = "macirq";
1228                         clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1229                         clock-names = "stmmaceth", "allwinner_gmac_tx";
1230                         snps,pbl = <2>;
1231                         snps,fixed-burst;
1232                         snps,force_sf_dma_mode;
1233                         status = "disabled";
1234                         #address-cells = <1>;
1235                         #size-cells = <0>;
1236                 };
1237
1238                 hstimer@01c60000 {
1239                         compatible = "allwinner,sun7i-a20-hstimer";
1240                         reg = <0x01c60000 0x1000>;
1241                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1242                                      <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1243                                      <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1244                                      <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1245                         clocks = <&ahb_gates 28>;
1246                 };
1247
1248                 gic: interrupt-controller@01c81000 {
1249                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1250                         reg = <0x01c81000 0x1000>,
1251                               <0x01c82000 0x1000>,
1252                               <0x01c84000 0x2000>,
1253                               <0x01c86000 0x2000>;
1254                         interrupt-controller;
1255                         #interrupt-cells = <3>;
1256                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1257                 };
1258
1259                 ps20: ps2@01c2a000 {
1260                         compatible = "allwinner,sun4i-a10-ps2";
1261                         reg = <0x01c2a000 0x400>;
1262                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1263                         clocks = <&apb1_gates 6>;
1264                         status = "disabled";
1265                 };
1266
1267                 ps21: ps2@01c2a400 {
1268                         compatible = "allwinner,sun4i-a10-ps2";
1269                         reg = <0x01c2a400 0x400>;
1270                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1271                         clocks = <&apb1_gates 7>;
1272                         status = "disabled";
1273                 };
1274         };
1275 };