git.sur5r.net Git - u-boot/blob - arch/arm/dts/sun8i-a23.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "sun8i-a23-a33.dtsi"
  46
  47 / {
  48         memory {
  49                 reg = <0x40000000 0x40000000>;
  50         };
  51
  52         clocks {
  53                 ahb1_gates: clk@01c20060 {
  54                         #clock-cells = <1>;
  55                         compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
  56                         reg = <0x01c20060 0x8>;
  57                         clocks = <&ahb1>;
  58                         clock-indices = <1>, <6>,
  59                                         <8>, <9>, <10>,
  60                                         <13>, <14>,
  61                                         <19>, <20>,
  62                                         <21>, <24>, <26>,
  63                                         <29>, <32>, <36>,
  64                                         <40>, <44>, <46>,
  65                                         <52>, <53>,
  66                                         <54>, <57>;
  67                         clock-output-names = "ahb1_mipidsi", "ahb1_dma",
  68                                         "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
  69                                         "ahb1_nand", "ahb1_sdram",
  70                                         "ahb1_hstimer", "ahb1_spi0",
  71                                         "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
  72                                         "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
  73                                         "ahb1_csi", "ahb1_be",  "ahb1_fe",
  74                                         "ahb1_gpu", "ahb1_msgbox",
  75                                         "ahb1_spinlock", "ahb1_drc";
  76                 };
  77
  78                 mbus_clk: clk@01c2015c {
  79                         #clock-cells = <0>;
  80                         compatible = "allwinner,sun8i-a23-mbus-clk";
  81                         reg = <0x01c2015c 0x4>;
  82                         clocks = <&osc24M>, <&pll6 1>, <&pll5>;
  83                         clock-output-names = "mbus";
  84                 };
  85         };
  86
  87         soc@01c00000 {
  88                 usb_otg: usb@01c19000 {
  89                         compatible = "allwinner,sun6i-a31-musb";
  90                         reg = <0x01c19000 0x0400>;
  91                         clocks = <&ahb1_gates 24>;
  92                         resets = <&ahb1_rst 24>;
  93                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  94                         interrupt-names = "mc";
  95                         phys = <&usbphy 0>;
  96                         phy-names = "usb";
  97                         extcon = <&usbphy 0>;
  98                         status = "disabled";
  99                 };
 100
 101                 usbphy: phy@01c19400 {
 102                         compatible = "allwinner,sun8i-a23-usb-phy";
 103                         reg = <0x01c19400 0x10>,
 104                               <0x01c1a800 0x4>;
 105                         reg-names = "phy_ctrl",
 106                                     "pmu1";
 107                         clocks = <&usb_clk 8>,
 108                                  <&usb_clk 9>;
 109                         clock-names = "usb0_phy",
 110                                       "usb1_phy";
 111                         resets = <&usb_clk 0>,
 112                                  <&usb_clk 1>;
 113                         reset-names = "usb0_reset",
 114                                       "usb1_reset";
 115                         status = "disabled";
 116                         #phy-cells = <1>;
 117                 };
 118         };
 119 };
 120
 121 &pio {
 122         compatible = "allwinner,sun8i-a23-pinctrl";
 123         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 124                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 125                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 126 };