2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "skeleton.dtsi"
45 #include <dt-bindings/clock/sun8i-h3-ccu.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/sun4i-a10.h>
48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
51 interrupt-parent = <&gic>;
62 compatible = "arm,cortex-a7";
68 compatible = "arm,cortex-a7";
74 compatible = "arm,cortex-a7";
80 compatible = "arm,cortex-a7";
87 compatible = "arm,armv7-timer";
88 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
89 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
101 compatible = "fixed-clock";
102 clock-frequency = <24000000>;
103 clock-output-names = "osc24M";
108 compatible = "fixed-clock";
109 clock-frequency = <32768>;
110 clock-output-names = "osc32k";
114 compatible = "fixed-factor-clock";
119 clock-output-names = "apb0";
122 apb0_gates: clk@01f01428 {
123 compatible = "allwinner,sun8i-h3-apb0-gates-clk",
124 "allwinner,sun4i-a10-gates-clk";
125 reg = <0x01f01428 0x4>;
128 clock-indices = <0>, <1>;
129 clock-output-names = "apb0_pio", "apb0_ir";
132 ir_clk: ir_clk@01f01454 {
133 compatible = "allwinner,sun4i-a10-mod0-clk";
134 reg = <0x01f01454 0x4>;
136 clocks = <&osc32k>, <&osc24M>;
137 clock-output-names = "ir";
142 compatible = "simple-bus";
143 #address-cells = <1>;
147 syscon: syscon@1c00000 {
148 compatible = "allwinner,sun8i-h3-system-controller",
150 reg = <0x01c00000 0x1000>;
153 dma: dma-controller@01c02000 {
154 compatible = "allwinner,sun8i-h3-dma";
155 reg = <0x01c02000 0x1000>;
156 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&ccu CLK_BUS_DMA>;
158 resets = <&ccu RST_BUS_DMA>;
163 compatible = "allwinner,sun7i-a20-mmc",
164 "allwinner,sun5i-a13-mmc";
165 reg = <0x01c0f000 0x1000>;
166 clocks = <&ccu CLK_BUS_MMC0>,
168 <&ccu CLK_MMC0_OUTPUT>,
169 <&ccu CLK_MMC0_SAMPLE>;
174 resets = <&ccu RST_BUS_MMC0>;
176 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
178 #address-cells = <1>;
183 compatible = "allwinner,sun7i-a20-mmc",
184 "allwinner,sun5i-a13-mmc";
185 reg = <0x01c10000 0x1000>;
186 clocks = <&ccu CLK_BUS_MMC1>,
188 <&ccu CLK_MMC1_OUTPUT>,
189 <&ccu CLK_MMC1_SAMPLE>;
194 resets = <&ccu RST_BUS_MMC1>;
196 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
198 #address-cells = <1>;
203 compatible = "allwinner,sun7i-a20-mmc",
204 "allwinner,sun5i-a13-mmc";
205 reg = <0x01c11000 0x1000>;
206 clocks = <&ccu CLK_BUS_MMC2>,
208 <&ccu CLK_MMC2_OUTPUT>,
209 <&ccu CLK_MMC2_SAMPLE>;
214 resets = <&ccu RST_BUS_MMC2>;
216 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
218 #address-cells = <1>;
222 usb_otg: usb@1c19000 {
223 compatible = "allwinner,sun8i-h3-musb";
224 reg = <0x01c19000 0x400>;
225 clocks = <&ccu CLK_BUS_OTG>;
226 resets = <&ccu RST_BUS_OTG>;
227 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
228 interrupt-names = "mc";
231 extcon = <&usbphy 0>;
235 usbphy: phy@01c19400 {
236 compatible = "allwinner,sun8i-h3-usb-phy";
237 reg = <0x01c19400 0x2c>,
242 reg-names = "phy_ctrl",
247 clocks = <&ccu CLK_USB_PHY0>,
251 clock-names = "usb0_phy",
255 resets = <&ccu RST_USB_PHY0>,
259 reset-names = "usb0_reset",
268 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
269 reg = <0x01c1a000 0x100>;
270 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
272 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
277 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
278 reg = <0x01c1a400 0x100>;
279 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
281 <&ccu CLK_USB_OHCI0>;
282 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
286 ehci1: usb@01c1b000 {
287 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
288 reg = <0x01c1b000 0x100>;
289 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
291 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
297 ohci1: usb@01c1b400 {
298 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
299 reg = <0x01c1b400 0x100>;
300 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
302 <&ccu CLK_USB_OHCI1>;
303 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
309 ehci2: usb@01c1c000 {
310 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
311 reg = <0x01c1c000 0x100>;
312 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
314 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
320 ohci2: usb@01c1c400 {
321 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
322 reg = <0x01c1c400 0x100>;
323 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
325 <&ccu CLK_USB_OHCI2>;
326 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
332 ehci3: usb@01c1d000 {
333 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
334 reg = <0x01c1d000 0x100>;
335 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
337 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
343 ohci3: usb@01c1d400 {
344 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
345 reg = <0x01c1d400 0x100>;
346 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
348 <&ccu CLK_USB_OHCI3>;
349 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
355 ccu: clock@01c20000 {
356 compatible = "allwinner,sun8i-h3-ccu";
357 reg = <0x01c20000 0x400>;
358 clocks = <&osc24M>, <&osc32k>;
359 clock-names = "hosc", "losc";
364 pio: pinctrl@01c20800 {
365 compatible = "allwinner,sun8i-h3-pinctrl";
366 reg = <0x01c20800 0x400>;
367 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
368 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&ccu CLK_BUS_PIO>;
372 interrupt-controller;
373 #interrupt-cells = <3>;
375 emac_rgmii_pins: emac0 {
376 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
377 "PD5", "PD7", "PD8", "PD9", "PD10",
378 "PD12", "PD13", "PD15", "PD16", "PD17";
380 drive-strength = <40>;
383 mmc0_pins_a: mmc0@0 {
384 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
386 allwinner,function = "mmc0";
387 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
388 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
391 mmc0_cd_pin: mmc0_cd_pin@0 {
392 allwinner,pins = "PF6";
393 allwinner,function = "gpio_in";
394 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
395 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
398 mmc1_pins_a: mmc1@0 {
399 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
401 allwinner,function = "mmc1";
402 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
403 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
406 mmc2_8bit_pins: mmc2_8bit {
407 allwinner,pins = "PC5", "PC6", "PC8",
408 "PC9", "PC10", "PC11",
409 "PC12", "PC13", "PC14",
411 allwinner,function = "mmc2";
412 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
413 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
416 uart0_pins_a: uart0@0 {
417 allwinner,pins = "PA4", "PA5";
418 allwinner,function = "uart0";
419 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
420 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
423 uart1_pins_a: uart1@0 {
424 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
425 allwinner,function = "uart1";
426 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
427 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
432 compatible = "allwinner,sun4i-a10-timer";
433 reg = <0x01c20c00 0xa0>;
434 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
439 wdt0: watchdog@01c20ca0 {
440 compatible = "allwinner,sun6i-a31-wdt";
441 reg = <0x01c20ca0 0x20>;
442 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
445 uart0: serial@01c28000 {
446 compatible = "snps,dw-apb-uart";
447 reg = <0x01c28000 0x400>;
448 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&ccu CLK_BUS_UART0>;
452 resets = <&ccu RST_BUS_UART0>;
453 dmas = <&dma 6>, <&dma 6>;
454 dma-names = "rx", "tx";
458 uart1: serial@01c28400 {
459 compatible = "snps,dw-apb-uart";
460 reg = <0x01c28400 0x400>;
461 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&ccu CLK_BUS_UART1>;
465 resets = <&ccu RST_BUS_UART1>;
466 dmas = <&dma 7>, <&dma 7>;
467 dma-names = "rx", "tx";
471 uart2: serial@01c28800 {
472 compatible = "snps,dw-apb-uart";
473 reg = <0x01c28800 0x400>;
474 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&ccu CLK_BUS_UART2>;
478 resets = <&ccu RST_BUS_UART2>;
479 dmas = <&dma 8>, <&dma 8>;
480 dma-names = "rx", "tx";
484 uart3: serial@01c28c00 {
485 compatible = "snps,dw-apb-uart";
486 reg = <0x01c28c00 0x400>;
487 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&ccu CLK_BUS_UART3>;
491 resets = <&ccu RST_BUS_UART3>;
492 dmas = <&dma 9>, <&dma 9>;
493 dma-names = "rx", "tx";
497 emac: ethernet@1c30000 {
498 compatible = "allwinner,sun8i-h3-emac";
500 reg = <0x01c30000 0x10000>;
501 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
502 interrupt-names = "macirq";
503 resets = <&ccu RST_BUS_EMAC>;
504 reset-names = "stmmaceth";
505 clocks = <&ccu CLK_BUS_EMAC>;
506 clock-names = "stmmaceth";
507 #address-cells = <1>;
512 #address-cells = <1>;
514 compatible = "snps,dwmac-mdio";
518 compatible = "allwinner,sun8i-h3-mdio-mux";
519 #address-cells = <1>;
522 mdio-parent-bus = <&mdio>;
523 /* Only one MDIO is usable at the time */
524 internal_mdio: mdio@1 {
525 compatible = "allwinner,sun8i-h3-mdio-internal";
527 #address-cells = <1>;
530 int_mii_phy: ethernet-phy@1 {
531 compatible = "ethernet-phy-ieee802.3-c22";
533 clocks = <&ccu CLK_BUS_EPHY>;
534 resets = <&ccu RST_BUS_EPHY>;
538 external_mdio: mdio@2 {
540 #address-cells = <1>;
546 gic: interrupt-controller@01c81000 {
547 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
548 reg = <0x01c81000 0x1000>,
552 interrupt-controller;
553 #interrupt-cells = <3>;
554 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
558 compatible = "allwinner,sun6i-a31-rtc";
559 reg = <0x01f00000 0x54>;
560 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
564 apb0_reset: reset@01f014b0 {
565 reg = <0x01f014b0 0x4>;
566 compatible = "allwinner,sun6i-a31-clock-reset";
571 compatible = "allwinner,sun5i-a13-ir";
572 clocks = <&apb0_gates 1>, <&ir_clk>;
573 clock-names = "apb", "ir";
574 resets = <&apb0_reset 1>;
575 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
576 reg = <0x01f02000 0x40>;
580 r_pio: pinctrl@01f02c00 {
581 compatible = "allwinner,sun8i-h3-r-pinctrl";
582 reg = <0x01f02c00 0x400>;
583 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&apb0_gates 0>;
585 resets = <&apb0_reset 0>;
588 interrupt-controller;
589 #interrupt-cells = <3>;
592 allwinner,pins = "PL11";
593 allwinner,function = "s_cir_rx";
594 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
595 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;