2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "skeleton.dtsi"
45 #include <dt-bindings/clock/sun8i-h3-ccu.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/sun4i-a10.h>
48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
51 interrupt-parent = <&gic>;
62 compatible = "arm,cortex-a7";
68 compatible = "arm,cortex-a7";
74 compatible = "arm,cortex-a7";
80 compatible = "arm,cortex-a7";
87 compatible = "arm,armv7-timer";
88 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
89 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
101 compatible = "fixed-clock";
102 clock-frequency = <24000000>;
103 clock-output-names = "osc24M";
108 compatible = "fixed-clock";
109 clock-frequency = <32768>;
110 clock-output-names = "osc32k";
114 compatible = "fixed-factor-clock";
119 clock-output-names = "apb0";
122 apb0_gates: clk@01f01428 {
123 compatible = "allwinner,sun8i-h3-apb0-gates-clk",
124 "allwinner,sun4i-a10-gates-clk";
125 reg = <0x01f01428 0x4>;
128 clock-indices = <0>, <1>;
129 clock-output-names = "apb0_pio", "apb0_ir";
132 ir_clk: ir_clk@01f01454 {
133 compatible = "allwinner,sun4i-a10-mod0-clk";
134 reg = <0x01f01454 0x4>;
136 clocks = <&osc32k>, <&osc24M>;
137 clock-output-names = "ir";
142 compatible = "simple-bus";
143 #address-cells = <1>;
147 syscon: syscon@1c00000 {
148 compatible = "allwinner,sun8i-h3-system-controller",
150 reg = <0x01c00000 0x1000>;
153 dma: dma-controller@01c02000 {
154 compatible = "allwinner,sun8i-h3-dma";
155 reg = <0x01c02000 0x1000>;
156 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&ccu CLK_BUS_DMA>;
158 resets = <&ccu RST_BUS_DMA>;
163 compatible = "allwinner,sun7i-a20-mmc",
164 "allwinner,sun5i-a13-mmc";
165 reg = <0x01c0f000 0x1000>;
166 clocks = <&ccu CLK_BUS_MMC0>,
168 <&ccu CLK_MMC0_OUTPUT>,
169 <&ccu CLK_MMC0_SAMPLE>;
174 resets = <&ccu RST_BUS_MMC0>;
176 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
178 #address-cells = <1>;
183 compatible = "allwinner,sun7i-a20-mmc",
184 "allwinner,sun5i-a13-mmc";
185 reg = <0x01c10000 0x1000>;
186 clocks = <&ccu CLK_BUS_MMC1>,
188 <&ccu CLK_MMC1_OUTPUT>,
189 <&ccu CLK_MMC1_SAMPLE>;
194 resets = <&ccu RST_BUS_MMC1>;
196 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
198 #address-cells = <1>;
203 compatible = "allwinner,sun7i-a20-mmc",
204 "allwinner,sun5i-a13-mmc";
205 reg = <0x01c11000 0x1000>;
206 clocks = <&ccu CLK_BUS_MMC2>,
208 <&ccu CLK_MMC2_OUTPUT>,
209 <&ccu CLK_MMC2_SAMPLE>;
214 resets = <&ccu RST_BUS_MMC2>;
216 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
218 #address-cells = <1>;
222 usbphy: phy@01c19400 {
223 compatible = "allwinner,sun8i-h3-usb-phy";
224 reg = <0x01c19400 0x2c>,
229 reg-names = "phy_ctrl",
234 clocks = <&ccu CLK_USB_PHY0>,
238 clock-names = "usb0_phy",
242 resets = <&ccu RST_USB_PHY0>,
246 reset-names = "usb0_reset",
254 ehci1: usb@01c1b000 {
255 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
256 reg = <0x01c1b000 0x100>;
257 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
259 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
265 ohci1: usb@01c1b400 {
266 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
267 reg = <0x01c1b400 0x100>;
268 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
270 <&ccu CLK_USB_OHCI1>;
271 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
277 ehci2: usb@01c1c000 {
278 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
279 reg = <0x01c1c000 0x100>;
280 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
282 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
288 ohci2: usb@01c1c400 {
289 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
290 reg = <0x01c1c400 0x100>;
291 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
293 <&ccu CLK_USB_OHCI2>;
294 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
300 ehci3: usb@01c1d000 {
301 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
302 reg = <0x01c1d000 0x100>;
303 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
305 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
311 ohci3: usb@01c1d400 {
312 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
313 reg = <0x01c1d400 0x100>;
314 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
316 <&ccu CLK_USB_OHCI3>;
317 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
323 ccu: clock@01c20000 {
324 compatible = "allwinner,sun8i-h3-ccu";
325 reg = <0x01c20000 0x400>;
326 clocks = <&osc24M>, <&osc32k>;
327 clock-names = "hosc", "losc";
332 pio: pinctrl@01c20800 {
333 compatible = "allwinner,sun8i-h3-pinctrl";
334 reg = <0x01c20800 0x400>;
335 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&ccu CLK_BUS_PIO>;
340 interrupt-controller;
341 #interrupt-cells = <3>;
343 emac_rgmii_pins: emac0 {
344 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
345 "PD5", "PD7", "PD8", "PD9", "PD10",
346 "PD12", "PD13", "PD15", "PD16", "PD17";
348 drive-strength = <40>;
351 mmc0_pins_a: mmc0@0 {
352 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
354 allwinner,function = "mmc0";
355 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
356 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
359 mmc0_cd_pin: mmc0_cd_pin@0 {
360 allwinner,pins = "PF6";
361 allwinner,function = "gpio_in";
362 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
363 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
366 mmc1_pins_a: mmc1@0 {
367 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
369 allwinner,function = "mmc1";
370 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
371 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
374 mmc2_8bit_pins: mmc2_8bit {
375 allwinner,pins = "PC5", "PC6", "PC8",
376 "PC9", "PC10", "PC11",
377 "PC12", "PC13", "PC14",
379 allwinner,function = "mmc2";
380 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
381 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
384 uart0_pins_a: uart0@0 {
385 allwinner,pins = "PA4", "PA5";
386 allwinner,function = "uart0";
387 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
388 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
391 uart1_pins_a: uart1@0 {
392 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
393 allwinner,function = "uart1";
394 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
395 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
400 compatible = "allwinner,sun4i-a10-timer";
401 reg = <0x01c20c00 0xa0>;
402 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
407 wdt0: watchdog@01c20ca0 {
408 compatible = "allwinner,sun6i-a31-wdt";
409 reg = <0x01c20ca0 0x20>;
410 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
413 uart0: serial@01c28000 {
414 compatible = "snps,dw-apb-uart";
415 reg = <0x01c28000 0x400>;
416 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&ccu CLK_BUS_UART0>;
420 resets = <&ccu RST_BUS_UART0>;
421 dmas = <&dma 6>, <&dma 6>;
422 dma-names = "rx", "tx";
426 uart1: serial@01c28400 {
427 compatible = "snps,dw-apb-uart";
428 reg = <0x01c28400 0x400>;
429 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&ccu CLK_BUS_UART1>;
433 resets = <&ccu RST_BUS_UART1>;
434 dmas = <&dma 7>, <&dma 7>;
435 dma-names = "rx", "tx";
439 uart2: serial@01c28800 {
440 compatible = "snps,dw-apb-uart";
441 reg = <0x01c28800 0x400>;
442 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&ccu CLK_BUS_UART2>;
446 resets = <&ccu RST_BUS_UART2>;
447 dmas = <&dma 8>, <&dma 8>;
448 dma-names = "rx", "tx";
452 uart3: serial@01c28c00 {
453 compatible = "snps,dw-apb-uart";
454 reg = <0x01c28c00 0x400>;
455 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&ccu CLK_BUS_UART3>;
459 resets = <&ccu RST_BUS_UART3>;
460 dmas = <&dma 9>, <&dma 9>;
461 dma-names = "rx", "tx";
465 emac: ethernet@1c30000 {
466 compatible = "allwinner,sun8i-h3-emac";
468 reg = <0x01c30000 0x10000>;
469 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
470 interrupt-names = "macirq";
471 resets = <&ccu RST_BUS_EMAC>;
472 reset-names = "stmmaceth";
473 clocks = <&ccu CLK_BUS_EMAC>;
474 clock-names = "stmmaceth";
475 #address-cells = <1>;
480 #address-cells = <1>;
482 compatible = "snps,dwmac-mdio";
486 compatible = "allwinner,sun8i-h3-mdio-mux";
487 #address-cells = <1>;
490 mdio-parent-bus = <&mdio>;
491 /* Only one MDIO is usable at the time */
492 internal_mdio: mdio@1 {
493 compatible = "allwinner,sun8i-h3-mdio-internal";
495 #address-cells = <1>;
498 int_mii_phy: ethernet-phy@1 {
499 compatible = "ethernet-phy-ieee802.3-c22";
501 clocks = <&ccu CLK_BUS_EPHY>;
502 resets = <&ccu RST_BUS_EPHY>;
506 external_mdio: mdio@2 {
508 #address-cells = <1>;
514 gic: interrupt-controller@01c81000 {
515 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
516 reg = <0x01c81000 0x1000>,
520 interrupt-controller;
521 #interrupt-cells = <3>;
522 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
526 compatible = "allwinner,sun6i-a31-rtc";
527 reg = <0x01f00000 0x54>;
528 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
532 apb0_reset: reset@01f014b0 {
533 reg = <0x01f014b0 0x4>;
534 compatible = "allwinner,sun6i-a31-clock-reset";
539 compatible = "allwinner,sun5i-a13-ir";
540 clocks = <&apb0_gates 1>, <&ir_clk>;
541 clock-names = "apb", "ir";
542 resets = <&apb0_reset 1>;
543 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
544 reg = <0x01f02000 0x40>;
548 r_pio: pinctrl@01f02c00 {
549 compatible = "allwinner,sun8i-h3-r-pinctrl";
550 reg = <0x01f02c00 0x400>;
551 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&apb0_gates 0>;
553 resets = <&apb0_reset 0>;
556 interrupt-controller;
557 #interrupt-cells = <3>;
560 allwinner,pins = "PL11";
561 allwinner,function = "s_cir_rx";
562 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
563 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;