2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
50 #include "skeleton64.dtsi"
52 #include <dt-bindings/interrupt-controller/arm-gic.h>
54 #include <dt-bindings/pinctrl/sun4i-a10.h>
57 interrupt-parent = <&gic>;
64 compatible = "arm,cortex-a7";
70 compatible = "arm,cortex-a7";
76 compatible = "arm,cortex-a7";
82 compatible = "arm,cortex-a7";
88 compatible = "arm,cortex-a15";
94 compatible = "arm,cortex-a15";
100 compatible = "arm,cortex-a15";
106 compatible = "arm,cortex-a15";
113 /* 8GB max. with LPAE */
114 reg = <0 0x20000000 0x02 0>;
118 compatible = "arm,armv7-timer";
119 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
120 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
121 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
122 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
123 clock-frequency = <24000000>;
124 arm,cpu-registers-not-fw-configured;
128 #address-cells = <1>;
131 * map 64 bit address range down to 32 bits,
132 * as the peripherals are all under 512MB.
134 ranges = <0 0 0 0x20000000>;
138 compatible = "fixed-clock";
139 clock-frequency = <24000000>;
140 clock-output-names = "osc24M";
145 compatible = "fixed-clock";
146 clock-frequency = <32768>;
147 clock-output-names = "osc32k";
150 usb_mod_clk: clk@00a08000 {
153 compatible = "allwinner,sun9i-a80-usb-mod-clk";
154 reg = <0x00a08000 0x4>;
155 clocks = <&ahb1_gates 1>;
156 clock-output-names = "usb0_ahb", "usb_ohci0",
157 "usb1_ahb", "usb_ohci1",
158 "usb2_ahb", "usb_ohci2";
161 usb_phy_clk: clk@00a08004 {
164 compatible = "allwinner,sun9i-a80-usb-phy-clk";
165 reg = <0x00a08004 0x4>;
166 clocks = <&ahb1_gates 1>;
167 clock-output-names = "usb_phy0", "usb_hsic1_480M",
168 "usb_phy1", "usb_hsic2_480M",
169 "usb_phy2", "usb_hsic_12M";
174 compatible = "allwinner,sun9i-a80-pll4-clk";
175 reg = <0x0600000c 0x4>;
177 clock-output-names = "pll4";
180 pll12: clk@0600002c {
182 compatible = "allwinner,sun9i-a80-pll4-clk";
183 reg = <0x0600002c 0x4>;
185 clock-output-names = "pll12";
188 gt_clk: clk@0600005c {
190 compatible = "allwinner,sun9i-a80-gt-clk";
191 reg = <0x0600005c 0x4>;
192 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
193 clock-output-names = "gt";
198 compatible = "allwinner,sun9i-a80-ahb-clk";
199 reg = <0x06000060 0x4>;
200 clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
201 clock-output-names = "ahb0";
206 compatible = "allwinner,sun9i-a80-ahb-clk";
207 reg = <0x06000064 0x4>;
208 clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
209 clock-output-names = "ahb1";
214 compatible = "allwinner,sun9i-a80-ahb-clk";
215 reg = <0x06000068 0x4>;
216 clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
217 clock-output-names = "ahb2";
222 compatible = "allwinner,sun9i-a80-apb0-clk";
223 reg = <0x06000070 0x4>;
224 clocks = <&osc24M>, <&pll4>;
225 clock-output-names = "apb0";
230 compatible = "allwinner,sun9i-a80-apb1-clk";
231 reg = <0x06000074 0x4>;
232 clocks = <&osc24M>, <&pll4>;
233 clock-output-names = "apb1";
236 cci400_clk: clk@06000078 {
238 compatible = "allwinner,sun9i-a80-gt-clk";
239 reg = <0x06000078 0x4>;
240 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
241 clock-output-names = "cci400";
244 mmc0_clk: clk@06000410 {
246 compatible = "allwinner,sun9i-a80-mmc-clk";
247 reg = <0x06000410 0x4>;
248 clocks = <&osc24M>, <&pll4>;
249 clock-output-names = "mmc0", "mmc0_output",
253 mmc1_clk: clk@06000414 {
255 compatible = "allwinner,sun9i-a80-mmc-clk";
256 reg = <0x06000414 0x4>;
257 clocks = <&osc24M>, <&pll4>;
258 clock-output-names = "mmc1", "mmc1_output",
262 mmc2_clk: clk@06000418 {
264 compatible = "allwinner,sun9i-a80-mmc-clk";
265 reg = <0x06000418 0x4>;
266 clocks = <&osc24M>, <&pll4>;
267 clock-output-names = "mmc2", "mmc2_output",
271 mmc3_clk: clk@0600041c {
273 compatible = "allwinner,sun9i-a80-mmc-clk";
274 reg = <0x0600041c 0x4>;
275 clocks = <&osc24M>, <&pll4>;
276 clock-output-names = "mmc3", "mmc3_output",
280 ahb0_gates: clk@06000580 {
282 compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
283 reg = <0x06000580 0x4>;
285 clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>,
286 <14>, <15>, <16>, <18>, <20>, <21>,
288 clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
289 "ahb0_ss", "ahb0_sd", "ahb0_nand1",
290 "ahb0_nand0", "ahb0_sdram",
291 "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
292 "ahb0_spi0","ahb0_spi1", "ahb0_spi2",
296 ahb1_gates: clk@06000584 {
298 compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
299 reg = <0x06000584 0x4>;
301 clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>;
302 clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
303 "ahb1_gmac", "ahb1_msgbox",
304 "ahb1_spinlock", "ahb1_hstimer",
308 ahb2_gates: clk@06000588 {
310 compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
311 reg = <0x06000588 0x4>;
313 clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>,
315 clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
316 "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
317 "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
320 apb0_gates: clk@06000590 {
322 compatible = "allwinner,sun9i-a80-apb0-gates-clk";
323 reg = <0x06000590 0x4>;
325 clock-indices = <1>, <5>, <11>, <12>, <13>, <15>,
327 clock-output-names = "apb0_spdif", "apb0_pio",
328 "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
329 "apb0_lradc", "apb0_gpadc", "apb0_twd",
333 apb1_gates: clk@06000594 {
335 compatible = "allwinner,sun9i-a80-apb1-gates-clk";
336 reg = <0x06000594 0x4>;
338 clock-indices = <0>, <1>, <2>, <3>, <4>,
339 <16>, <17>, <18>, <19>, <20>, <21>;
340 clock-output-names = "apb1_i2c0", "apb1_i2c1",
341 "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
342 "apb1_uart0", "apb1_uart1",
343 "apb1_uart2", "apb1_uart3",
344 "apb1_uart4", "apb1_uart5";
349 compatible = "simple-bus";
350 #address-cells = <1>;
353 * map 64 bit address range down to 32 bits,
354 * as the peripherals are all under 512MB.
356 ranges = <0 0 0 0x20000000>;
358 ehci0: usb@00a00000 {
359 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
360 reg = <0x00a00000 0x100>;
361 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&usb_mod_clk 1>;
363 resets = <&usb_mod_clk 17>;
369 ohci0: usb@00a00400 {
370 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
371 reg = <0x00a00400 0x100>;
372 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>;
374 resets = <&usb_mod_clk 17>;
380 usbphy1: phy@00a00800 {
381 compatible = "allwinner,sun9i-a80-usb-phy";
382 reg = <0x00a00800 0x4>;
383 clocks = <&usb_phy_clk 1>;
385 resets = <&usb_phy_clk 17>;
391 ehci1: usb@00a01000 {
392 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
393 reg = <0x00a01000 0x100>;
394 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&usb_mod_clk 3>;
396 resets = <&usb_mod_clk 18>;
402 usbphy2: phy@00a01800 {
403 compatible = "allwinner,sun9i-a80-usb-phy";
404 reg = <0x00a01800 0x4>;
405 clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>,
407 clock-names = "hsic_480M", "hsic_12M", "phy";
408 resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>;
409 reset-names = "hsic", "phy";
412 /* usb1 is always used with HSIC */
416 ehci2: usb@00a02000 {
417 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
418 reg = <0x00a02000 0x100>;
419 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&usb_mod_clk 5>;
421 resets = <&usb_mod_clk 19>;
427 ohci2: usb@00a02400 {
428 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
429 reg = <0x00a02400 0x100>;
430 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&usb_mod_clk 5>, <&usb_mod_clk 6>;
432 resets = <&usb_mod_clk 19>;
438 usbphy3: phy@00a02800 {
439 compatible = "allwinner,sun9i-a80-usb-phy";
440 reg = <0x00a02800 0x4>;
441 clocks = <&usb_phy_clk 4>, <&usb_phy_clk 10>,
443 clock-names = "hsic_480M", "hsic_12M", "phy";
444 resets = <&usb_phy_clk 20>, <&usb_phy_clk 21>;
445 reset-names = "hsic", "phy";
451 compatible = "allwinner,sun5i-a13-mmc";
452 reg = <0x01c0f000 0x1000>;
453 clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
454 <&mmc0_clk 1>, <&mmc0_clk 2>;
455 clock-names = "ahb", "mmc", "output", "sample";
456 resets = <&mmc_config_clk 0>;
458 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
460 #address-cells = <1>;
465 compatible = "allwinner,sun5i-a13-mmc";
466 reg = <0x01c10000 0x1000>;
467 clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
468 <&mmc1_clk 1>, <&mmc1_clk 2>;
469 clock-names = "ahb", "mmc", "output", "sample";
470 resets = <&mmc_config_clk 1>;
472 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
474 #address-cells = <1>;
479 compatible = "allwinner,sun5i-a13-mmc";
480 reg = <0x01c11000 0x1000>;
481 clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
482 <&mmc2_clk 1>, <&mmc2_clk 2>;
483 clock-names = "ahb", "mmc", "output", "sample";
484 resets = <&mmc_config_clk 2>;
486 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
488 #address-cells = <1>;
493 compatible = "allwinner,sun5i-a13-mmc";
494 reg = <0x01c12000 0x1000>;
495 clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
496 <&mmc3_clk 1>, <&mmc3_clk 2>;
497 clock-names = "ahb", "mmc", "output", "sample";
498 resets = <&mmc_config_clk 3>;
500 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
502 #address-cells = <1>;
506 mmc_config_clk: clk@01c13000 {
507 compatible = "allwinner,sun9i-a80-mmc-config-clk";
508 reg = <0x01c13000 0x10>;
509 clocks = <&ahb0_gates 8>;
511 resets = <&ahb0_resets 8>;
515 clock-output-names = "mmc0_config", "mmc1_config",
516 "mmc2_config", "mmc3_config";
519 gic: interrupt-controller@01c41000 {
520 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
521 reg = <0x01c41000 0x1000>,
525 interrupt-controller;
526 #interrupt-cells = <3>;
527 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
530 ahb0_resets: reset@060005a0 {
532 compatible = "allwinner,sun6i-a31-clock-reset";
533 reg = <0x060005a0 0x4>;
536 ahb1_resets: reset@060005a4 {
538 compatible = "allwinner,sun6i-a31-clock-reset";
539 reg = <0x060005a4 0x4>;
542 ahb2_resets: reset@060005a8 {
544 compatible = "allwinner,sun6i-a31-clock-reset";
545 reg = <0x060005a8 0x4>;
548 apb0_resets: reset@060005b0 {
550 compatible = "allwinner,sun6i-a31-clock-reset";
551 reg = <0x060005b0 0x4>;
554 apb1_resets: reset@060005b4 {
556 compatible = "allwinner,sun6i-a31-clock-reset";
557 reg = <0x060005b4 0x4>;
561 compatible = "allwinner,sun4i-a10-timer";
562 reg = <0x06000c00 0xa0>;
563 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
573 pio: pinctrl@06000800 {
574 compatible = "allwinner,sun9i-a80-pinctrl";
575 reg = <0x06000800 0x400>;
576 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&apb0_gates 5>;
583 interrupt-controller;
584 #interrupt-cells = <2>;
588 i2c3_pins_a: i2c3@0 {
589 allwinner,pins = "PG10", "PG11";
590 allwinner,function = "i2c3";
591 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
592 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
596 allwinner,pins = "PF0", "PF1" ,"PF2", "PF3",
598 allwinner,function = "mmc0";
599 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
600 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
603 mmc2_8bit_pins: mmc2_8bit {
604 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
605 "PC10", "PC11", "PC12",
606 "PC13", "PC14", "PC15";
607 allwinner,function = "mmc2";
608 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
609 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
612 uart0_pins_a: uart0@0 {
613 allwinner,pins = "PH12", "PH13";
614 allwinner,function = "uart0";
615 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
616 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
619 uart4_pins_a: uart4@0 {
620 allwinner,pins = "PG12", "PG13", "PG14", "PG15";
621 allwinner,function = "uart4";
622 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
623 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
627 uart0: serial@07000000 {
628 compatible = "snps,dw-apb-uart";
629 reg = <0x07000000 0x400>;
630 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&apb1_gates 16>;
634 resets = <&apb1_resets 16>;
638 uart1: serial@07000400 {
639 compatible = "snps,dw-apb-uart";
640 reg = <0x07000400 0x400>;
641 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&apb1_gates 17>;
645 resets = <&apb1_resets 17>;
649 uart2: serial@07000800 {
650 compatible = "snps,dw-apb-uart";
651 reg = <0x07000800 0x400>;
652 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&apb1_gates 18>;
656 resets = <&apb1_resets 18>;
660 uart3: serial@07000c00 {
661 compatible = "snps,dw-apb-uart";
662 reg = <0x07000c00 0x400>;
663 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&apb1_gates 19>;
667 resets = <&apb1_resets 19>;
671 uart4: serial@07001000 {
672 compatible = "snps,dw-apb-uart";
673 reg = <0x07001000 0x400>;
674 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&apb1_gates 20>;
678 resets = <&apb1_resets 20>;
682 uart5: serial@07001400 {
683 compatible = "snps,dw-apb-uart";
684 reg = <0x07001400 0x400>;
685 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&apb1_gates 21>;
689 resets = <&apb1_resets 21>;
694 compatible = "allwinner,sun6i-a31-i2c";
695 reg = <0x07002800 0x400>;
696 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&apb1_gates 0>;
698 resets = <&apb1_resets 0>;
700 #address-cells = <1>;
705 compatible = "allwinner,sun6i-a31-i2c";
706 reg = <0x07002c00 0x400>;
707 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&apb1_gates 1>;
709 resets = <&apb1_resets 1>;
711 #address-cells = <1>;
716 compatible = "allwinner,sun6i-a31-i2c";
717 reg = <0x07003000 0x400>;
718 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
719 clocks = <&apb1_gates 2>;
720 resets = <&apb1_resets 2>;
722 #address-cells = <1>;
727 compatible = "allwinner,sun6i-a31-i2c";
728 reg = <0x07003400 0x400>;
729 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&apb1_gates 3>;
731 resets = <&apb1_resets 3>;
733 #address-cells = <1>;
738 compatible = "allwinner,sun6i-a31-i2c";
739 reg = <0x07003800 0x400>;
740 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&apb1_gates 4>;
742 resets = <&apb1_resets 4>;
744 #address-cells = <1>;
748 r_wdt: watchdog@08001000 {
749 compatible = "allwinner,sun6i-a31-wdt";
750 reg = <0x08001000 0x20>;
751 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
754 r_uart: serial@08002800 {
755 compatible = "snps,dw-apb-uart";
756 reg = <0x08002800 0x400>;
757 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;