1 #include <dt-bindings/clock/tegra124-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include "skeleton.dtsi"
10 compatible = "nvidia,tegra124";
11 interrupt-parent = <&gic>;
13 pcie-controller@01003000 {
14 compatible = "nvidia,tegra124-pcie";
16 reg = <0x01003000 0x00000800 /* PADS registers */
17 0x01003800 0x00000800 /* AFI registers */
18 0x02000000 0x10000000>; /* configuration space */
19 reg-names = "pads", "afi", "cs";
20 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
21 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
22 interrupt-names = "intr", "msi";
24 #interrupt-cells = <1>;
25 interrupt-map-mask = <0 0 0 0>;
26 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
28 bus-range = <0x00 0xff>;
32 ranges = <0x82000000 0 0x01000000 0x01000000 0 0x00001000 /* port 0 configuration space */
33 0x82000000 0 0x01001000 0x01001000 0 0x00001000 /* port 1 configuration space */
34 0x81000000 0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
35 0x82000000 0 0x13000000 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
36 0xc2000000 0 0x20000000 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
38 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
39 <&tegra_car TEGRA124_CLK_AFI>,
40 <&tegra_car TEGRA124_CLK_PLL_E>,
41 <&tegra_car TEGRA124_CLK_CML0>;
42 clock-names = "pex", "afi", "pll_e", "cml";
43 resets = <&tegra_car 70>,
46 reset-names = "pex", "afi", "pcie_x";
49 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
54 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
55 reg = <0x000800 0 0 0 0>;
62 nvidia,num-lanes = <2>;
67 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
68 reg = <0x001000 0 0 0 0>;
75 nvidia,num-lanes = <1>;
80 compatible = "nvidia,tegra124-host1x", "simple-bus";
81 reg = <0x50000000 0x00034000>;
82 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
83 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
84 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
85 resets = <&tegra_car 28>;
86 reset-names = "host1x";
91 ranges = <0x54000000 0x54000000 0x01000000>;
94 compatible = "nvidia,tegra124-dc";
95 reg = <0x54200000 0x00040000>;
96 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
97 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
98 <&tegra_car TEGRA124_CLK_PLL_P>;
99 clock-names = "dc", "parent";
100 resets = <&tegra_car 27>;
107 compatible = "nvidia,tegra124-dc";
108 reg = <0x54240000 0x00040000>;
109 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
111 <&tegra_car TEGRA124_CLK_PLL_P>;
112 clock-names = "dc", "parent";
113 resets = <&tegra_car 26>;
120 compatible = "nvidia,tegra124-hdmi";
121 reg = <0x54280000 0x00040000>;
122 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
123 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
124 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
125 clock-names = "hdmi", "parent";
126 resets = <&tegra_car 51>;
127 reset-names = "hdmi";
132 compatible = "nvidia,tegra124-sor";
133 reg = <0x54540000 0x00040000>;
134 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
135 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
136 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
137 <&tegra_car TEGRA124_CLK_PLL_DP>,
138 <&tegra_car TEGRA124_CLK_CLK_M>;
139 clock-names = "sor", "parent", "dp", "safe";
140 resets = <&tegra_car 182>;
145 dpaux: dpaux@545c0000 {
146 compatible = "nvidia,tegra124-dpaux";
147 reg = <0x545c0000 0x00040000>;
148 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
149 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
150 <&tegra_car TEGRA124_CLK_PLL_DP>;
151 clock-names = "dpaux", "parent";
152 resets = <&tegra_car 181>;
153 reset-names = "dpaux";
158 gic: interrupt-controller@50041000 {
159 compatible = "arm,cortex-a15-gic";
160 #interrupt-cells = <3>;
161 interrupt-controller;
162 reg = <0x50041000 0x1000>,
166 interrupts = <GIC_PPI 9
167 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
170 tegra_car: clock@60006000 {
171 compatible = "nvidia,tegra124-car";
172 reg = <0x60006000 0x1000>;
176 apbdma: dma@60020000 {
177 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
178 reg = <0x60020000 0x1400>;
179 interrupts = <0 104 0x04
213 gpio: gpio@6000d000 {
214 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
215 reg = <0x6000d000 0x1000>;
216 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
226 #interrupt-cells = <2>;
227 interrupt-controller;
231 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
232 reg = <0x7000c000 0x100>;
233 interrupts = <0 38 0x04>;
234 #address-cells = <1>;
236 clocks = <&tegra_car 12>;
241 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
242 reg = <0x7000c400 0x100>;
243 interrupts = <0 84 0x04>;
244 #address-cells = <1>;
246 clocks = <&tegra_car 54>;
251 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
252 reg = <0x7000c500 0x100>;
253 interrupts = <0 92 0x04>;
254 #address-cells = <1>;
256 clocks = <&tegra_car 67>;
261 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
262 reg = <0x7000c700 0x100>;
263 interrupts = <0 120 0x04>;
264 #address-cells = <1>;
266 clocks = <&tegra_car 103>;
271 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
272 reg = <0x7000d000 0x100>;
273 interrupts = <0 53 0x04>;
274 #address-cells = <1>;
276 clocks = <&tegra_car 47>;
281 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
282 reg = <0x7000d100 0x100>;
283 interrupts = <0 53 0x04>;
284 #address-cells = <1>;
286 clocks = <&tegra_car 47>;
290 uarta: serial@70006000 {
291 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
292 reg = <0x70006000 0x40>;
294 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
296 resets = <&tegra_car 6>;
297 reset-names = "serial";
298 dmas = <&apbdma 8>, <&apbdma 8>;
299 dma-names = "rx", "tx";
303 uartb: serial@70006040 {
304 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
305 reg = <0x70006040 0x40>;
307 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
309 resets = <&tegra_car 7>;
310 reset-names = "serial";
311 dmas = <&apbdma 9>, <&apbdma 9>;
312 dma-names = "rx", "tx";
316 uartc: serial@70006200 {
317 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
318 reg = <0x70006200 0x40>;
320 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
322 resets = <&tegra_car 55>;
323 reset-names = "serial";
324 dmas = <&apbdma 10>, <&apbdma 10>;
325 dma-names = "rx", "tx";
329 uartd: serial@70006300 {
330 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
331 reg = <0x70006300 0x40>;
333 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
335 resets = <&tegra_car 65>;
336 reset-names = "serial";
337 dmas = <&apbdma 19>, <&apbdma 19>;
338 dma-names = "rx", "tx";
342 uarte: serial@70006400 {
343 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
344 reg = <0x70006400 0x40>;
346 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&tegra_car TEGRA124_CLK_UARTE>;
348 resets = <&tegra_car 66>;
349 reset-names = "serial";
350 dmas = <&apbdma 20>, <&apbdma 20>;
351 dma-names = "rx", "tx";
356 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
357 reg = <0x7000a000 0x100>;
359 clocks = <&tegra_car TEGRA124_CLK_PWM>;
360 resets = <&tegra_car 17>;
366 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
367 reg = <0x7000d400 0x200>;
368 interrupts = <0 59 0x04>;
369 nvidia,dma-request-selector = <&apbdma 15>;
370 #address-cells = <1>;
373 clocks = <&tegra_car 41>;
377 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
378 reg = <0x7000d600 0x200>;
379 interrupts = <0 82 0x04>;
380 nvidia,dma-request-selector = <&apbdma 16>;
381 #address-cells = <1>;
384 clocks = <&tegra_car 44>;
388 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
389 reg = <0x7000d800 0x200>;
390 interrupts = <0 83 0x04>;
391 nvidia,dma-request-selector = <&apbdma 17>;
392 #address-cells = <1>;
395 clocks = <&tegra_car 46>;
399 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
400 reg = <0x7000da00 0x200>;
401 interrupts = <0 93 0x04>;
402 nvidia,dma-request-selector = <&apbdma 18>;
403 #address-cells = <1>;
406 clocks = <&tegra_car 68>;
410 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
411 reg = <0x7000dc00 0x200>;
412 interrupts = <0 94 0x04>;
413 nvidia,dma-request-selector = <&apbdma 27>;
414 #address-cells = <1>;
417 clocks = <&tegra_car 104>;
421 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
422 reg = <0x7000de00 0x200>;
423 interrupts = <0 79 0x04>;
424 nvidia,dma-request-selector = <&apbdma 28>;
425 #address-cells = <1>;
428 clocks = <&tegra_car 105>;
432 compatible = "nvidia,tegra124-pmc";
433 reg = <0x7000e400 0x400>;
436 padctl: padctl@7009f000 {
437 compatible = "nvidia,tegra124-xusb-padctl";
438 reg = <0x7009f000 0x1000>;
439 resets = <&tegra_car 142>;
440 reset-names = "padctl";
446 compatible = "nvidia,tegra124-sdhci";
447 reg = <0x700b0000 0x200>;
448 interrupts = <0 14 0x04>;
449 clocks = <&tegra_car 14>;
454 compatible = "nvidia,tegra124-sdhci";
455 reg = <0x700b0200 0x200>;
456 interrupts = <0 15 0x04>;
457 clocks = <&tegra_car 9>;
462 compatible = "nvidia,tegra124-sdhci";
463 reg = <0x700b0400 0x200>;
464 interrupts = <0 19 0x04>;
465 clocks = <&tegra_car 69>;
470 compatible = "nvidia,tegra124-sdhci";
471 reg = <0x700b0600 0x200>;
472 interrupts = <0 31 0x04>;
473 clocks = <&tegra_car 15>;
478 compatible = "nvidia,tegra124-ahub";
479 reg = <0x70300000 0x200>,
482 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
484 <&tegra_car TEGRA124_CLK_APBIF>;
485 clock-names = "d_audio", "apbif";
486 resets = <&tegra_car 106>, /* d_audio */
487 <&tegra_car 107>, /* apbif */
488 <&tegra_car 30>, /* i2s0 */
489 <&tegra_car 11>, /* i2s1 */
490 <&tegra_car 18>, /* i2s2 */
491 <&tegra_car 101>, /* i2s3 */
492 <&tegra_car 102>, /* i2s4 */
493 <&tegra_car 108>, /* dam0 */
494 <&tegra_car 109>, /* dam1 */
495 <&tegra_car 110>, /* dam2 */
496 <&tegra_car 10>, /* spdif */
497 <&tegra_car 153>, /* amx */
498 <&tegra_car 185>, /* amx1 */
499 <&tegra_car 154>, /* adx */
500 <&tegra_car 180>, /* adx1 */
501 <&tegra_car 186>, /* afc0 */
502 <&tegra_car 187>, /* afc1 */
503 <&tegra_car 188>, /* afc2 */
504 <&tegra_car 189>, /* afc3 */
505 <&tegra_car 190>, /* afc4 */
506 <&tegra_car 191>; /* afc5 */
507 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
508 "i2s3", "i2s4", "dam0", "dam1", "dam2",
509 "spdif", "amx", "amx1", "adx", "adx1",
510 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
511 dmas = <&apbdma 1>, <&apbdma 1>,
512 <&apbdma 2>, <&apbdma 2>,
513 <&apbdma 3>, <&apbdma 3>,
514 <&apbdma 4>, <&apbdma 4>,
515 <&apbdma 6>, <&apbdma 6>,
516 <&apbdma 7>, <&apbdma 7>,
517 <&apbdma 12>, <&apbdma 12>,
518 <&apbdma 13>, <&apbdma 13>,
519 <&apbdma 14>, <&apbdma 14>,
520 <&apbdma 29>, <&apbdma 29>;
521 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
522 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
523 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
526 #address-cells = <1>;
529 tegra_i2s0: i2s@70301000 {
530 compatible = "nvidia,tegra124-i2s";
531 reg = <0x70301000 0x100>;
532 nvidia,ahub-cif-ids = <4 4>;
533 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
534 resets = <&tegra_car 30>;
539 tegra_i2s1: i2s@70301100 {
540 compatible = "nvidia,tegra124-i2s";
541 reg = <0x70301100 0x100>;
542 nvidia,ahub-cif-ids = <5 5>;
543 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
544 resets = <&tegra_car 11>;
549 tegra_i2s2: i2s@70301200 {
550 compatible = "nvidia,tegra124-i2s";
551 reg = <0x70301200 0x100>;
552 nvidia,ahub-cif-ids = <6 6>;
553 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
554 resets = <&tegra_car 18>;
559 tegra_i2s3: i2s@70301300 {
560 compatible = "nvidia,tegra124-i2s";
561 reg = <0x70301300 0x100>;
562 nvidia,ahub-cif-ids = <7 7>;
563 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
564 resets = <&tegra_car 101>;
569 tegra_i2s4: i2s@70301400 {
570 compatible = "nvidia,tegra124-i2s";
571 reg = <0x70301400 0x100>;
572 nvidia,ahub-cif-ids = <8 8>;
573 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
574 resets = <&tegra_car 102>;
581 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
582 reg = <0x7d000000 0x4000>;
585 clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
590 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
591 reg = <0x7d004000 0x4000>;
594 clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
599 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
600 reg = <0x7d008000 0x4000>;
601 interrupts = < 129 >;
603 clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */