git.sur5r.net Git - u-boot/blob - arch/arm/dts/tegra20-seaboard.dts

   1 /dts-v1/;
   2
   3 #include "tegra20.dtsi"
   4
   5 / {
   6         model = "NVIDIA Seaboard";
   7         compatible = "nvidia,seaboard", "nvidia,tegra20";
   8
   9         chosen {
  10                 bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
  11         };
  12
  13         chosen {
  14                 stdout-path = &uartd;
  15         };
  16
  17         aliases {
  18                 /* This defines the order of our ports */
  19                 usb0 = "/usb@c5008000";
  20                 usb1 = "/usb@c5000000";
  21                 i2c0 = "/i2c@7000d000";
  22                 i2c1 = "/i2c@7000c000";
  23                 i2c2 = "/i2c@7000c400";
  24                 i2c3 = "/i2c@7000c500";
  25                 sdhci0 = "/sdhci@c8000600";
  26                 sdhci1 = "/sdhci@c8000400";
  27         };
  28
  29         memory {
  30                 device_type = "memory";
  31                 reg = < 0x00000000 0x40000000 >;
  32         };
  33
  34         host1x@50000000 {
  35                 status = "okay";
  36                 dc@54200000 {
  37                         status = "okay";
  38                         rgb {
  39                                 status = "okay";
  40                                 nvidia,panel = <&lcd_panel>;
  41                         };
  42                 };
  43
  44                 dc@54240000 {
  45                         status = "disabled";
  46                 };
  47         };
  48
  49         /* This is not used in U-Boot, but is expected to be in kernel .dts */
  50         i2c@7000d000 {
  51                 status = "okay";
  52                 clock-frequency = <100000>;
  53                 pmic@34 {
  54                         compatible = "ti,tps6586x";
  55                         reg = <0x34>;
  56
  57                         clk_32k: clock {
  58                                 compatible = "fixed-clock";
  59                                 /*
  60                                  * leave out for now due to CPP:
  61                                  * #clock-cells = <0>;
  62                                  */
  63                                 clock-frequency = <32768>;
  64                         };
  65                 };
  66         };
  67
  68         serial@70006300 {
  69                 clock-frequency = < 216000000 >;
  70         };
  71
  72         nand-controller@70008000 {
  73                 nvidia,wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
  74                 nvidia,width = <8>;
  75                 nvidia,timing = <26 100 20 80 20 10 12 10 70>;
  76                 nand@0 {
  77                         reg = <0>;
  78                         compatible = "hynix,hy27uf4g2b", "nand-flash";
  79                 };
  80         };
  81
  82         i2c@7000c000 {
  83                 status = "okay";
  84                 clock-frequency = <100000>;
  85         };
  86
  87         i2c@7000c400 {
  88                 status = "okay";
  89         };
  90
  91         i2c@7000c500 {
  92                 status = "okay";
  93                 clock-frequency = <100000>;
  94         };
  95
  96         kbc@7000e200 {
  97                 status = "okay";
  98                 linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c
  99                         0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006
 100                         0x03010005 0x03020013 0x03030012 0x03040021 0x03050020
 101                         0x0306002d 0x04000008 0x04010007 0x04020014 0x04030023
 102                         0x04040022 0x0405002f 0x0406002e 0x04070039 0x0500000a
 103                         0x05010009 0x05020016 0x05030015 0x05040024 0x05050031
 104                         0x05060030 0x0507002b 0x0600000c 0x0601000b 0x06020018
 105                         0x06030017 0x06040026 0x06050025 0x06060033 0x06070032
 106                         0x0701000d 0x0702001b 0x0703001c 0x0707008b 0x08040036
 107                         0x0805002a 0x09050061 0x0907001d 0x0b00001a 0x0b010019
 108                         0x0b020028 0x0b030027 0x0b040035 0x0b050034 0x0c000044
 109                         0x0c010043 0x0c02000e 0x0c030004 0x0c040003 0x0c050067
 110                         0x0c0600d2 0x0c070077 0x0d00006e 0x0d01006f 0x0d030068
 111                         0x0d04006d 0x0d05006a 0x0d06006c 0x0d070069 0x0e000057
 112                         0x0e010058 0x0e020042 0x0e030010 0x0e04003e 0x0e05003d
 113                         0x0e060002 0x0e070041 0x0f000001 0x0f010029 0x0f02003f
 114                         0x0f03000f 0x0f04003b 0x0f05003c 0x0f06003a 0x0f070040
 115                         0x14000047 0x15000049 0x15010048 0x1502004b 0x1504004f
 116                         0x16010062 0x1602004d 0x1603004c 0x16040051 0x16050050
 117                         0x16070052 0x1b010037 0x1b03004a 0x1b04004e 0x1b050053
 118                         0x1c050073 0x1d030066 0x1d04006b 0x1d0500e0 0x1d060072
 119                         0x1d0700e1 0x1e000045 0x1e010046 0x1e020071
 120                         0x1f04008a>;
 121                 linux,fn-keymap = <0x05040002>;
 122         };
 123
 124         emc@7000f400 {
 125                 #address-cells = <1>;
 126                 #size-cells = <0>;
 127                 emc-table@190000 {
 128                         reg = < 190000 >;
 129                         compatible = "nvidia,tegra20-emc-table";
 130                         clock-frequency = < 190000 >;
 131                         nvidia,emc-registers = < 0x0000000c 0x00000026
 132                                 0x00000009 0x00000003 0x00000004 0x00000004
 133                                 0x00000002 0x0000000c 0x00000003 0x00000003
 134                                 0x00000002 0x00000001 0x00000004 0x00000005
 135                                 0x00000004 0x00000009 0x0000000d 0x0000059f
 136                                 0x00000000 0x00000003 0x00000003 0x00000003
 137                                 0x00000003 0x00000001 0x0000000b 0x000000c8
 138                                 0x00000003 0x00000007 0x00000004 0x0000000f
 139                                 0x00000002 0x00000000 0x00000000 0x00000002
 140                                 0x00000000 0x00000000 0x00000083 0xa06204ae
 141                                 0x007dc010 0x00000000 0x00000000 0x00000000
 142                                 0x00000000 0x00000000 0x00000000 0x00000000 >;
 143                 };
 144                 emc-table@380000 {
 145                         reg = < 380000 >;
 146                         compatible = "nvidia,tegra20-emc-table";
 147                         clock-frequency = < 380000 >;
 148                         nvidia,emc-registers = < 0x00000017 0x0000004b
 149                                 0x00000012 0x00000006 0x00000004 0x00000005
 150                                 0x00000003 0x0000000c 0x00000006 0x00000006
 151                                 0x00000003 0x00000001 0x00000004 0x00000005
 152                                 0x00000004 0x00000009 0x0000000d 0x00000b5f
 153                                 0x00000000 0x00000003 0x00000003 0x00000006
 154                                 0x00000006 0x00000001 0x00000011 0x000000c8
 155                                 0x00000003 0x0000000e 0x00000007 0x0000000f
 156                                 0x00000002 0x00000000 0x00000000 0x00000002
 157                                 0x00000000 0x00000000 0x00000083 0xe044048b
 158                                 0x007d8010 0x00000000 0x00000000 0x00000000
 159                                 0x00000000 0x00000000 0x00000000 0x00000000 >;
 160                 };
 161         };
 162
 163         usb@c5000000 {
 164                 status = "okay";
 165                 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
 166                 dr_mode = "otg";
 167         };
 168
 169         usb@c5004000 {
 170                 status = "disabled";
 171         };
 172
 173         usb@c5008000 {
 174                 status = "okay";
 175         };
 176
 177         sdhci@c8000400 {
 178                 status = "okay";
 179                 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
 180                 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
 181                 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
 182                 bus-width = <4>;
 183         };
 184
 185         sdhci@c8000600 {
 186                 status = "okay";
 187                 bus-width = <8>;
 188         };
 189
 190         clocks {
 191                 compatible = "simple-bus";
 192                 #address-cells = <1>;
 193                 #size-cells = <0>;
 194
 195                 clk32k_in: clock@0 {
 196                         compatible = "fixed-clock";
 197                         reg=<0>;
 198                         #clock-cells = <0>;
 199                         clock-frequency = <32768>;
 200                 };
 201         };
 202
 203         pwm: pwm@7000a000 {
 204                 status = "okay";
 205         };
 206
 207         lcd_panel: panel {
 208                 /* Seaboard has 1366x768 */
 209                 clock = <70600000>;
 210                 xres = <1366>;
 211                 yres = <768>;
 212                 left-margin = <58>;
 213                 right-margin = <58>;
 214                 hsync-len = <58>;
 215                 lower-margin = <4>;
 216                 upper-margin = <4>;
 217                 vsync-len = <4>;
 218                 hsync-active-high;
 219                 nvidia,bits-per-pixel = <16>;
 220                 nvidia,pwm = <&pwm 2 0>;
 221                 nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4)
 222                                                         GPIO_ACTIVE_HIGH>;
 223                 nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
 224                                                         GPIO_ACTIVE_HIGH>;
 225                 nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
 226                                                         GPIO_ACTIVE_HIGH>;
 227                 nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
 228                                                         GPIO_ACTIVE_HIGH>;
 229                 nvidia,panel-timings = <400 4 203 17 15>;
 230         };
 231 };