git.sur5r.net Git - u-boot/blob - arch/arm/dts/tegra20-tamonten.dtsi

   1 #include "tegra20.dtsi"
   2
   3 / {
   4         model = "Avionic Design Tamonten SOM";
   5         compatible = "ad,tamonten", "nvidia,tegra20";
   6
   7         memory {
   8                 reg = <0x00000000 0x20000000>;
   9         };
  10
  11         host1x {
  12                 hdmi {
  13                         vdd-supply = <&hdmi_vdd_reg>;
  14                         pll-supply = <&hdmi_pll_reg>;
  15
  16                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  17                         nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
  18                 };
  19         };
  20
  21         pinmux {
  22                 pinctrl-names = "default";
  23                 pinctrl-0 = <&state_default>;
  24
  25                 state_default: pinmux {
  26                         ata {
  27                                 nvidia,pins = "ata";
  28                                 nvidia,function = "ide";
  29                         };
  30                         atb {
  31                                 nvidia,pins = "atb", "gma", "gme";
  32                                 nvidia,function = "sdio4";
  33                         };
  34                         atc {
  35                                 nvidia,pins = "atc";
  36                                 nvidia,function = "nand";
  37                         };
  38                         atd {
  39                                 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
  40                                         "spia", "spib", "spic";
  41                                 nvidia,function = "gmi";
  42                         };
  43                         cdev1 {
  44                                 nvidia,pins = "cdev1";
  45                                 nvidia,function = "plla_out";
  46                         };
  47                         cdev2 {
  48                                 nvidia,pins = "cdev2";
  49                                 nvidia,function = "pllp_out4";
  50                         };
  51                         crtp {
  52                                 nvidia,pins = "crtp";
  53                                 nvidia,function = "crt";
  54                         };
  55                         csus {
  56                                 nvidia,pins = "csus";
  57                                 nvidia,function = "vi_sensor_clk";
  58                         };
  59                         dap1 {
  60                                 nvidia,pins = "dap1";
  61                                 nvidia,function = "dap1";
  62                         };
  63                         dap2 {
  64                                 nvidia,pins = "dap2";
  65                                 nvidia,function = "dap2";
  66                         };
  67                         dap3 {
  68                                 nvidia,pins = "dap3";
  69                                 nvidia,function = "dap3";
  70                         };
  71                         dap4 {
  72                                 nvidia,pins = "dap4";
  73                                 nvidia,function = "dap4";
  74                         };
  75                         dta {
  76                                 nvidia,pins = "dta", "dtd";
  77                                 nvidia,function = "sdio2";
  78                         };
  79                         dtb {
  80                                 nvidia,pins = "dtb", "dtc", "dte";
  81                                 nvidia,function = "rsvd1";
  82                         };
  83                         dtf {
  84                                 nvidia,pins = "dtf";
  85                                 nvidia,function = "i2c3";
  86                         };
  87                         gmc {
  88                                 nvidia,pins = "gmc";
  89                                 nvidia,function = "uartd";
  90                         };
  91                         gpu7 {
  92                                 nvidia,pins = "gpu7";
  93                                 nvidia,function = "rtck";
  94                         };
  95                         gpv {
  96                                 nvidia,pins = "gpv", "slxa", "slxk";
  97                                 nvidia,function = "pcie";
  98                         };
  99                         hdint {
 100                                 nvidia,pins = "hdint";
 101                                 nvidia,function = "hdmi";
 102                         };
 103                         i2cp {
 104                                 nvidia,pins = "i2cp";
 105                                 nvidia,function = "i2cp";
 106                         };
 107                         irrx {
 108                                 nvidia,pins = "irrx", "irtx";
 109                                 nvidia,function = "uarta";
 110                         };
 111                         kbca {
 112                                 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
 113                                         "kbce", "kbcf";
 114                                 nvidia,function = "kbc";
 115                         };
 116                         lcsn {
 117                                 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
 118                                         "ld3", "ld4", "ld5", "ld6", "ld7",
 119                                         "ld8", "ld9", "ld10", "ld11", "ld12",
 120                                         "ld13", "ld14", "ld15", "ld16", "ld17",
 121                                         "ldc", "ldi", "lhp0", "lhp1", "lhp2",
 122                                         "lhs", "lm0", "lm1", "lpp", "lpw0",
 123                                         "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
 124                                         "lsda", "lsdi", "lspi", "lvp0", "lvp1",
 125                                         "lvs";
 126                                 nvidia,function = "displaya";
 127                         };
 128                         owc {
 129                                 nvidia,pins = "owc", "spdi", "spdo", "uac";
 130                                 nvidia,function = "rsvd2";
 131                         };
 132                         pmc {
 133                                 nvidia,pins = "pmc";
 134                                 nvidia,function = "pwr_on";
 135                         };
 136                         rm {
 137                                 nvidia,pins = "rm";
 138                                 nvidia,function = "i2c1";
 139                         };
 140                         sdb {
 141                                 nvidia,pins = "sdb", "sdc", "sdd";
 142                                 nvidia,function = "pwm";
 143                         };
 144                         sdio1 {
 145                                 nvidia,pins = "sdio1";
 146                                 nvidia,function = "sdio1";
 147                         };
 148                         slxc {
 149                                 nvidia,pins = "slxc", "slxd";
 150                                 nvidia,function = "spdif";
 151                         };
 152                         spid {
 153                                 nvidia,pins = "spid", "spie", "spif";
 154                                 nvidia,function = "spi1";
 155                         };
 156                         spig {
 157                                 nvidia,pins = "spig", "spih";
 158                                 nvidia,function = "spi2_alt";
 159                         };
 160                         uaa {
 161                                 nvidia,pins = "uaa", "uab", "uda";
 162                                 nvidia,function = "ulpi";
 163                         };
 164                         uad {
 165                                 nvidia,pins = "uad";
 166                                 nvidia,function = "irda";
 167                         };
 168                         uca {
 169                                 nvidia,pins = "uca", "ucb";
 170                                 nvidia,function = "uartc";
 171                         };
 172                         conf_ata {
 173                                 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
 174                                         "cdev1", "cdev2", "dap1", "dtb", "gma",
 175                                         "gmb", "gmc", "gmd", "gme", "gpu7",
 176                                         "gpv", "i2cp", "pta", "rm", "slxa",
 177                                         "slxk", "spia", "spib", "uac";
 178                                 nvidia,pull = <0>;
 179                                 nvidia,tristate = <0>;
 180                         };
 181                         conf_ck32 {
 182                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
 183                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
 184                                 nvidia,pull = <0>;
 185                         };
 186                         conf_csus {
 187                                 nvidia,pins = "csus", "spid", "spif";
 188                                 nvidia,pull = <1>;
 189                                 nvidia,tristate = <1>;
 190                         };
 191                         conf_crtp {
 192                                 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
 193                                         "dtc", "dte", "dtf", "gpu", "sdio1",
 194                                         "slxc", "slxd", "spdi", "spdo", "spig",
 195                                         "uda";
 196                                 nvidia,pull = <0>;
 197                                 nvidia,tristate = <1>;
 198                         };
 199                         conf_ddc {
 200                                 nvidia,pins = "ddc", "dta", "dtd", "kbca",
 201                                         "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
 202                                         "sdc";
 203                                 nvidia,pull = <2>;
 204                                 nvidia,tristate = <0>;
 205                         };
 206                         conf_hdint {
 207                                 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
 208                                         "lpw1", "lsc1", "lsck", "lsda", "lsdi",
 209                                         "lvp0", "owc", "sdb";
 210                                 nvidia,tristate = <1>;
 211                         };
 212                         conf_irrx {
 213                                 nvidia,pins = "irrx", "irtx", "sdd", "spic",
 214                                         "spie", "spih", "uaa", "uab", "uad",
 215                                         "uca", "ucb";
 216                                 nvidia,pull = <2>;
 217                                 nvidia,tristate = <1>;
 218                         };
 219                         conf_lc {
 220                                 nvidia,pins = "lc", "ls";
 221                                 nvidia,pull = <2>;
 222                         };
 223                         conf_ld0 {
 224                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
 225                                         "ld5", "ld6", "ld7", "ld8", "ld9",
 226                                         "ld10", "ld11", "ld12", "ld13", "ld14",
 227                                         "ld15", "ld16", "ld17", "ldi", "lhp0",
 228                                         "lhp1", "lhp2", "lhs", "lm0", "lpp",
 229                                         "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
 230                                         "lvs", "pmc";
 231                                 nvidia,tristate = <0>;
 232                         };
 233                         conf_ld17_0 {
 234                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
 235                                         "ld23_22";
 236                                 nvidia,pull = <1>;
 237                         };
 238                 };
 239
 240                 state_i2cmux_ddc: pinmux_i2cmux_ddc {
 241                         ddc {
 242                                 nvidia,pins = "ddc";
 243                                 nvidia,function = "i2c2";
 244                         };
 245                         pta {
 246                                 nvidia,pins = "pta";
 247                                 nvidia,function = "rsvd4";
 248                         };
 249                 };
 250
 251                 state_i2cmux_pta: pinmux_i2cmux_pta {
 252                         ddc {
 253                                 nvidia,pins = "ddc";
 254                                 nvidia,function = "rsvd4";
 255                         };
 256                         pta {
 257                                 nvidia,pins = "pta";
 258                                 nvidia,function = "i2c2";
 259                         };
 260                 };
 261
 262                 state_i2cmux_idle: pinmux_i2cmux_idle {
 263                         ddc {
 264                                 nvidia,pins = "ddc";
 265                                 nvidia,function = "rsvd4";
 266                         };
 267                         pta {
 268                                 nvidia,pins = "pta";
 269                                 nvidia,function = "rsvd4";
 270                         };
 271                 };
 272         };
 273
 274         i2s@70002800 {
 275                 status = "okay";
 276         };
 277
 278         serial@70006300 {
 279                 status = "okay";
 280         };
 281
 282         nand-controller@70008000 {
 283                 nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
 284                 nvidia,width = <8>;
 285                 nvidia,timing = <26 100 20 80 20 10 12 10 70>;
 286
 287                 nand@0 {
 288                         reg = <0>;
 289                         compatible = "hynix,hy27uf4g2b", "nand-flash";
 290                 };
 291         };
 292
 293         i2c@7000c000 {
 294                 clock-frequency = <400000>;
 295                 status = "okay";
 296         };
 297
 298         i2c@7000c400 {
 299                 clock-frequency = <100000>;
 300                 status = "okay";
 301         };
 302
 303         i2cmux {
 304                 compatible = "i2c-mux-pinctrl";
 305                 #address-cells = <1>;
 306                 #size-cells = <0>;
 307
 308                 i2c-parent = <&{/i2c@7000c400}>;
 309
 310                 pinctrl-names = "ddc", "pta", "idle";
 311                 pinctrl-0 = <&state_i2cmux_ddc>;
 312                 pinctrl-1 = <&state_i2cmux_pta>;
 313                 pinctrl-2 = <&state_i2cmux_idle>;
 314
 315                 hdmi_ddc: i2c@0 {
 316                         reg = <0>;
 317                         #address-cells = <1>;
 318                         #size-cells = <0>;
 319                 };
 320
 321                 i2c@1 {
 322                         reg = <1>;
 323                         #address-cells = <1>;
 324                         #size-cells = <0>;
 325                 };
 326         };
 327
 328         i2c@7000d000 {
 329                 clock-frequency = <400000>;
 330                 status = "okay";
 331
 332                 pmic: tps6586x@34 {
 333                         compatible = "ti,tps6586x";
 334                         reg = <0x34>;
 335                         interrupts = <0 86 0x4>;
 336
 337                         ti,system-power-controller;
 338
 339                         #gpio-cells = <2>;
 340                         gpio-controller;
 341
 342                         sys-supply = <&vdd_5v0_reg>;
 343                         vin-sm0-supply = <&sys_reg>;
 344                         vin-sm1-supply = <&sys_reg>;
 345                         vin-sm2-supply = <&sys_reg>;
 346                         vinldo01-supply = <&sm2_reg>;
 347                         vinldo23-supply = <&sm2_reg>;
 348                         vinldo4-supply = <&sm2_reg>;
 349                         vinldo678-supply = <&sm2_reg>;
 350                         vinldo9-supply = <&sm2_reg>;
 351
 352                         regulators {
 353                                 sys_reg: sys {
 354                                         regulator-name = "vdd_sys";
 355                                         regulator-always-on;
 356                                 };
 357
 358                                 sm0 {
 359                                         regulator-name = "vdd_sys_sm0,vdd_core";
 360                                         regulator-min-microvolt = <1200000>;
 361                                         regulator-max-microvolt = <1200000>;
 362                                         regulator-always-on;
 363                                 };
 364
 365                                 sm1 {
 366                                         regulator-name = "vdd_sys_sm1,vdd_cpu";
 367                                         regulator-min-microvolt = <1000000>;
 368                                         regulator-max-microvolt = <1000000>;
 369                                         regulator-always-on;
 370                                 };
 371
 372                                 sm2_reg: sm2 {
 373                                         regulator-name = "vdd_sys_sm2,vin_ldo*";
 374                                         regulator-min-microvolt = <3700000>;
 375                                         regulator-max-microvolt = <3700000>;
 376                                         regulator-always-on;
 377                                 };
 378
 379                                 ldo0 {
 380                                         regulator-name = "vdd_ldo0,vddio_pex_clk";
 381                                         regulator-min-microvolt = <3300000>;
 382                                         regulator-max-microvolt = <3300000>;
 383                                 };
 384
 385                                 ldo1 {
 386                                         regulator-name = "vdd_ldo1,avdd_pll*";
 387                                         regulator-min-microvolt = <1100000>;
 388                                         regulator-max-microvolt = <1100000>;
 389                                         regulator-always-on;
 390                                 };
 391
 392                                 ldo2 {
 393                                         regulator-name = "vdd_ldo2,vdd_rtc";
 394                                         regulator-min-microvolt = <1200000>;
 395                                         regulator-max-microvolt = <1200000>;
 396                                 };
 397
 398                                 ldo3 {
 399                                         regulator-name = "vdd_ldo3,avdd_usb*";
 400                                         regulator-min-microvolt = <3300000>;
 401                                         regulator-max-microvolt = <3300000>;
 402                                         regulator-always-on;
 403                                 };
 404
 405                                 ldo4 {
 406                                         regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
 407                                         regulator-min-microvolt = <1800000>;
 408                                         regulator-max-microvolt = <1800000>;
 409                                         regulator-always-on;
 410                                 };
 411
 412                                 ldo5 {
 413                                         regulator-name = "vdd_ldo5,vcore_mmc";
 414                                         regulator-min-microvolt = <2850000>;
 415                                         regulator-max-microvolt = <2850000>;
 416                                 };
 417
 418                                 ldo6 {
 419                                         regulator-name = "vdd_ldo6,avdd_vdac";
 420                                         /*
 421                                          * According to the Tegra 2 Automotive
 422                                          * DataSheet, a typical value for this
 423                                          * would be 2.8V, but the PMIC only
 424                                          * supports 2.85V.
 425                                          */
 426                                         regulator-min-microvolt = <2850000>;
 427                                         regulator-max-microvolt = <2850000>;
 428                                 };
 429
 430                                 hdmi_vdd_reg: ldo7 {
 431                                         regulator-name = "vdd_ldo7,avdd_hdmi";
 432                                         regulator-min-microvolt = <3300000>;
 433                                         regulator-max-microvolt = <3300000>;
 434                                 };
 435
 436                                 hdmi_pll_reg: ldo8 {
 437                                         regulator-name = "vdd_ldo8,avdd_hdmi_pll";
 438                                         regulator-min-microvolt = <1800000>;
 439                                         regulator-max-microvolt = <1800000>;
 440                                 };
 441
 442                                 ldo9 {
 443                                         regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
 444                                         /*
 445                                          * According to the Tegra 2 Automotive
 446                                          * DataSheet, a typical value for this
 447                                          * would be 2.8V, but the PMIC only
 448                                          * supports 2.85V.
 449                                          */
 450                                         regulator-min-microvolt = <2850000>;
 451                                         regulator-max-microvolt = <2850000>;
 452                                         regulator-always-on;
 453                                 };
 454
 455                                 ldo_rtc {
 456                                         regulator-name = "vdd_rtc_out";
 457                                         regulator-min-microvolt = <3300000>;
 458                                         regulator-max-microvolt = <3300000>;
 459                                         regulator-always-on;
 460                                 };
 461                         };
 462                 };
 463
 464                 temperature-sensor@4c {
 465                         compatible = "onnn,nct1008";
 466                         reg = <0x4c>;
 467                 };
 468         };
 469
 470         pmc {
 471                 nvidia,invert-interrupt;
 472         };
 473
 474         usb@c5008000 {
 475                 status = "okay";
 476         };
 477
 478         sdhci@c8000600 {
 479                 cd-gpios = <&gpio 58 1>; /* gpio PH2 */
 480                 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
 481                 bus-width = <4>;
 482                 status = "okay";
 483         };
 484
 485         regulators {
 486                 compatible = "simple-bus";
 487
 488                 #address-cells = <1>;
 489                 #size-cells = <0>;
 490
 491                 vdd_5v0_reg: regulator@0 {
 492                         compatible = "regulator-fixed";
 493                         reg = <0>;
 494                         regulator-name = "vdd_5v0";
 495                         regulator-min-microvolt = <5000000>;
 496                         regulator-max-microvolt = <5000000>;
 497                         regulator-always-on;
 498                 };
 499         };
 500 };