git.sur5r.net Git - u-boot/blob - arch/arm/dts/tegra20-ventana.dts

   1 /dts-v1/;
   2
   3 #include "tegra20.dtsi"
   4
   5 / {
   6         model = "NVIDIA Tegra20 Ventana evaluation board";
   7         compatible = "nvidia,ventana", "nvidia,tegra20";
   8
   9         chosen {
  10                 stdout-path = &uartd;
  11         };
  12
  13         aliases {
  14                 usb0 = "/usb@c5008000";
  15                 sdhci0 = "/sdhci@c8000600";
  16                 sdhci1 = "/sdhci@c8000400";
  17         };
  18
  19         memory {
  20                 reg = <0x00000000 0x40000000>;
  21         };
  22
  23         host1x@50000000 {
  24                 status = "okay";
  25                 dc@54200000 {
  26                         status = "okay";
  27                         rgb {
  28                                 status = "okay";
  29                                 nvidia,panel = <&lcd_panel>;
  30                         };
  31                 };
  32         };
  33
  34         serial@70006300 {
  35                 clock-frequency = < 216000000 >;
  36         };
  37
  38         usb@c5008000 {
  39                 status = "okay";
  40         };
  41
  42         sdhci@c8000400 {
  43                 status = "okay";
  44                 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  45                 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  46                 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
  47                 bus-width = <4>;
  48         };
  49
  50         sdhci@c8000600 {
  51                 status = "okay";
  52                 bus-width = <8>;
  53         };
  54
  55         clocks {
  56                 compatible = "simple-bus";
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 clk32k_in: clock@0 {
  61                         compatible = "fixed-clock";
  62                         reg=<0>;
  63                         #clock-cells = <0>;
  64                         clock-frequency = <32768>;
  65                 };
  66         };
  67
  68         pwm: pwm@7000a000 {
  69                 status = "okay";
  70         };
  71
  72         lcd_panel: panel {
  73                 clock = <72072000>;
  74                 xres = <1366>;
  75                 yres = <768>;
  76                 left-margin = <58>;
  77                 right-margin = <58>;
  78                 hsync-len = <58>;
  79                 lower-margin = <4>;
  80                 upper-margin = <4>;
  81                 vsync-len = <4>;
  82                 hsync-active-high;
  83                 vsync-active-high;
  84                 nvidia,bits-per-pixel = <16>;
  85                 nvidia,pwm = <&pwm 2 0>;
  86                 nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4)
  87                                                         GPIO_ACTIVE_HIGH>;
  88                 nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
  89                                                         GPIO_ACTIVE_HIGH>;
  90                 nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
  91                                                         GPIO_ACTIVE_HIGH>;
  92                 nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
  93                                                         GPIO_ACTIVE_HIGH>;
  94                 nvidia,panel-timings = <0 0 200 0 0>;
  95         };
  96 };