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arm: socfpga: Fix typos in DT files (environmnet -> environment)
[u-boot] / arch / arm / dts / tegra30.dtsi
1 #include <dt-bindings/clock/tegra30-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/interrupt-controller/arm-gic.h>
4
5 #include "skeleton.dtsi"
6
7 / {
8         compatible = "nvidia,tegra30";
9         interrupt-parent = <&intc>;
10
11         intc: interrupt-controller@50041000 {
12                 compatible = "arm,cortex-a9-gic";
13                 reg = <0x50041000 0x1000
14                        0x50040100 0x0100>;
15                 interrupt-controller;
16                 #interrupt-cells = <3>;
17         };
18
19         pcie-controller@00003000 {
20                 compatible = "nvidia,tegra30-pcie";
21                 device_type = "pci";
22                 reg = <0x00003000 0x00000800   /* PADS registers */
23                        0x00003800 0x00000200   /* AFI registers */
24                        0x10000000 0x10000000>; /* configuration space */
25                 reg-names = "pads", "afi", "cs";
26                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
27                               GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
28                 interrupt-names = "intr", "msi";
29
30                 #interrupt-cells = <1>;
31                 interrupt-map-mask = <0 0 0 0>;
32                 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33
34                 bus-range = <0x00 0xff>;
35                 #address-cells = <3>;
36                 #size-cells = <2>;
37
38                 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
39                           0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
40                           0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
41                           0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
42                           0x82000000 0 0x20000000 0x20000000 0 0x10000000   /* non-prefetchable memory */
43                           0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */
44
45                 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
46                          <&tegra_car TEGRA30_CLK_AFI>,
47                          <&tegra_car TEGRA30_CLK_PCIEX>,
48                          <&tegra_car TEGRA30_CLK_PLL_E>,
49                          <&tegra_car TEGRA30_CLK_CML0>;
50                 clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
51                 status = "disabled";
52
53                 pci@1,0 {
54                         device_type = "pci";
55                         assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
56                         reg = <0x000800 0 0 0 0>;
57                         status = "disabled";
58
59                         #address-cells = <3>;
60                         #size-cells = <2>;
61                         ranges;
62
63                         nvidia,num-lanes = <2>;
64                 };
65
66                 pci@2,0 {
67                         device_type = "pci";
68                         assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
69                         reg = <0x001000 0 0 0 0>;
70                         status = "disabled";
71
72                         #address-cells = <3>;
73                         #size-cells = <2>;
74                         ranges;
75
76                         nvidia,num-lanes = <2>;
77                 };
78
79                 pci@3,0 {
80                         device_type = "pci";
81                         assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
82                         reg = <0x001800 0 0 0 0>;
83                         status = "disabled";
84
85                         #address-cells = <3>;
86                         #size-cells = <2>;
87                         ranges;
88
89                         nvidia,num-lanes = <2>;
90                 };
91         };
92
93         tegra_car: clock {
94                 compatible = "nvidia,tegra30-car";
95                 reg = <0x60006000 0x1000>;
96                 #clock-cells = <1>;
97         };
98
99         apbdma: dma {
100                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
101                 reg = <0x6000a000 0x1400>;
102                 interrupts = <0 104 0x04
103                               0 105 0x04
104                               0 106 0x04
105                               0 107 0x04
106                               0 108 0x04
107                               0 109 0x04
108                               0 110 0x04
109                               0 111 0x04
110                               0 112 0x04
111                               0 113 0x04
112                               0 114 0x04
113                               0 115 0x04
114                               0 116 0x04
115                               0 117 0x04
116                               0 118 0x04
117                               0 119 0x04
118                               0 128 0x04
119                               0 129 0x04
120                               0 130 0x04
121                               0 131 0x04
122                               0 132 0x04
123                               0 133 0x04
124                               0 134 0x04
125                               0 135 0x04
126                               0 136 0x04
127                               0 137 0x04
128                               0 138 0x04
129                               0 139 0x04
130                               0 140 0x04
131                               0 141 0x04
132                               0 142 0x04
133                               0 143 0x04>;
134                 clocks = <&tegra_car 34>;
135         };
136
137         gpio: gpio@6000d000 {
138                 compatible = "nvidia,tegra30-gpio";
139                 reg = <0x6000d000 0x1000>;
140                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
141                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
142                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
143                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
144                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
145                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
146                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
147                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
148                 #gpio-cells = <2>;
149                 gpio-controller;
150                 #interrupt-cells = <2>;
151                 interrupt-controller;
152         };
153
154         i2c@7000c000 {
155                 compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
156                 reg = <0x7000c000 0x100>;
157                 interrupts = <0 38 0x04>;
158                 #address-cells = <1>;
159                 #size-cells = <0>;
160                 clocks = <&tegra_car 12>, <&tegra_car 182>;
161                 clock-names = "div-clk", "fast-clk";
162                 status = "disabled";
163         };
164
165         i2c@7000c400 {
166                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
167                 reg = <0x7000c400 0x100>;
168                 interrupts = <0 84 0x04>;
169                 #address-cells = <1>;
170                 #size-cells = <0>;
171                 clocks = <&tegra_car 54>, <&tegra_car 182>;
172                 clock-names = "div-clk", "fast-clk";
173                 status = "disabled";
174         };
175
176         i2c@7000c500 {
177                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
178                 reg = <0x7000c500 0x100>;
179                 interrupts = <0 92 0x04>;
180                 #address-cells = <1>;
181                 #size-cells = <0>;
182                 clocks = <&tegra_car 67>, <&tegra_car 182>;
183                 clock-names = "div-clk", "fast-clk";
184                 status = "disabled";
185         };
186
187         i2c@7000c700 {
188                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
189                 reg = <0x7000c700 0x100>;
190                 interrupts = <0 120 0x04>;
191                 #address-cells = <1>;
192                 #size-cells = <0>;
193                 clocks = <&tegra_car 103>, <&tegra_car 182>;
194                 clock-names = "div-clk", "fast-clk";
195                 status = "disabled";
196         };
197
198         i2c@7000d000 {
199                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
200                 reg = <0x7000d000 0x100>;
201                 interrupts = <0 53 0x04>;
202                 #address-cells = <1>;
203                 #size-cells = <0>;
204                 clocks = <&tegra_car 47>, <&tegra_car 182>;
205                 clock-names = "div-clk", "fast-clk";
206                 status = "disabled";
207         };
208
209         uarta: serial@70006000 {
210                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
211                 reg = <0x70006000 0x40>;
212                 reg-shift = <2>;
213                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
214                 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
215                 resets = <&tegra_car 6>;
216                 reset-names = "serial";
217                 dmas = <&apbdma 8>, <&apbdma 8>;
218                 dma-names = "rx", "tx";
219                 status = "disabled";
220         };
221
222         uartb: serial@70006040 {
223                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
224                 reg = <0x70006040 0x40>;
225                 reg-shift = <2>;
226                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
227                 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
228                 resets = <&tegra_car 7>;
229                 reset-names = "serial";
230                 dmas = <&apbdma 9>, <&apbdma 9>;
231                 dma-names = "rx", "tx";
232                 status = "disabled";
233         };
234
235         uartc: serial@70006200 {
236                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
237                 reg = <0x70006200 0x100>;
238                 reg-shift = <2>;
239                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
240                 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
241                 resets = <&tegra_car 55>;
242                 reset-names = "serial";
243                 dmas = <&apbdma 10>, <&apbdma 10>;
244                 dma-names = "rx", "tx";
245                 status = "disabled";
246         };
247
248         uartd: serial@70006300 {
249                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
250                 reg = <0x70006300 0x100>;
251                 reg-shift = <2>;
252                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
253                 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
254                 resets = <&tegra_car 65>;
255                 reset-names = "serial";
256                 dmas = <&apbdma 19>, <&apbdma 19>;
257                 dma-names = "rx", "tx";
258                 status = "disabled";
259         };
260
261         uarte: serial@70006400 {
262                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
263                 reg = <0x70006400 0x100>;
264                 reg-shift = <2>;
265                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
266                 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
267                 resets = <&tegra_car 66>;
268                 reset-names = "serial";
269                 dmas = <&apbdma 20>, <&apbdma 20>;
270                 dma-names = "rx", "tx";
271                 status = "disabled";
272         };
273
274         spi@7000d400 {
275                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
276                 reg = <0x7000d400 0x200>;
277                 interrupts = <0 59 0x04>;
278                 nvidia,dma-request-selector = <&apbdma 15>;
279                 #address-cells = <1>;
280                 #size-cells = <0>;
281                 clocks = <&tegra_car 41>;
282                 status = "disabled";
283         };
284
285         spi@7000d600 {
286                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
287                 reg = <0x7000d600 0x200>;
288                 interrupts = <0 82 0x04>;
289                 nvidia,dma-request-selector = <&apbdma 16>;
290                 #address-cells = <1>;
291                 #size-cells = <0>;
292                 clocks = <&tegra_car 44>;
293                 status = "disabled";
294         };
295
296         spi@7000d800 {
297                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
298                 reg = <0x7000d480 0x200>;
299                 interrupts = <0 83 0x04>;
300                 nvidia,dma-request-selector = <&apbdma 17>;
301                 #address-cells = <1>;
302                 #size-cells = <0>;
303                 clocks = <&tegra_car 46>;
304                 status = "disabled";
305         };
306
307         spi@7000da00 {
308                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
309                 reg = <0x7000da00 0x200>;
310                 interrupts = <0 93 0x04>;
311                 nvidia,dma-request-selector = <&apbdma 18>;
312                 #address-cells = <1>;
313                 #size-cells = <0>;
314                 clocks = <&tegra_car 68>;
315                 status = "disabled";
316         };
317
318         spi@7000dc00 {
319                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
320                 reg = <0x7000dc00 0x200>;
321                 interrupts = <0 94 0x04>;
322                 nvidia,dma-request-selector = <&apbdma 27>;
323                 #address-cells = <1>;
324                 #size-cells = <0>;
325                 clocks = <&tegra_car 104>;
326                 status = "disabled";
327         };
328
329         spi@7000de00 {
330                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
331                 reg = <0x7000de00 0x200>;
332                 interrupts = <0 79 0x04>;
333                 nvidia,dma-request-selector = <&apbdma 28>;
334                 #address-cells = <1>;
335                 #size-cells = <0>;
336                 clocks = <&tegra_car 105>;
337                 status = "disabled";
338         };
339
340         sdhci@78000000 {
341                 compatible = "nvidia,tegra30-sdhci";
342                 reg = <0x78000000 0x200>;
343                 interrupts = <0 14 0x04>;
344                 clocks = <&tegra_car 14>;
345                 status = "disabled";
346         };
347
348         sdhci@78000200 {
349                 compatible = "nvidia,tegra30-sdhci";
350                 reg = <0x78000200 0x200>;
351                 interrupts = <0 15 0x04>;
352                 clocks = <&tegra_car 9>;
353                 status = "disabled";
354         };
355
356         sdhci@78000400 {
357                 compatible = "nvidia,tegra30-sdhci";
358                 reg = <0x78000400 0x200>;
359                 interrupts = <0 19 0x04>;
360                 clocks = <&tegra_car 69>;
361                 status = "disabled";
362         };
363
364         sdhci@78000600 {
365                 compatible = "nvidia,tegra30-sdhci";
366                 reg = <0x78000600 0x200>;
367                 interrupts = <0 31 0x04>;
368                 clocks = <&tegra_car 15>;
369                 status = "disabled";
370         };
371
372         usb@7d000000 {
373                 compatible = "nvidia,tegra30-ehci";
374                 reg = <0x7d000000 0x4000>;
375                 interrupts = <52>;
376                 phy_type = "utmi";
377                 clocks = <&tegra_car 22>;       /* PERIPH_ID_USBD */
378                 status = "disabled";
379         };
380
381         usb@7d004000 {
382                 compatible = "nvidia,tegra30-ehci";
383                 reg = <0x7d004000 0x4000>;
384                 interrupts = <53>;
385                 phy_type = "hsic";
386                 clocks = <&tegra_car 58>;       /* PERIPH_ID_USB2 */
387                 status = "disabled";
388         };
389
390         usb@7d008000 {
391                 compatible = "nvidia,tegra30-ehci";
392                 reg = <0x7d008000 0x4000>;
393                 interrupts = <129>;
394                 phy_type = "utmi";
395                 clocks = <&tegra_car 59>;       /* PERIPH_ID_USB3 */
396                 status = "disabled";
397         };
398 };