1 #include <dt-bindings/clock/tegra30-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include "skeleton.dtsi"
8 compatible = "nvidia,tegra30";
9 interrupt-parent = <&intc>;
11 intc: interrupt-controller@50041000 {
12 compatible = "arm,cortex-a9-gic";
13 reg = <0x50041000 0x1000
16 #interrupt-cells = <3>;
20 compatible = "nvidia,tegra30-car";
21 reg = <0x60006000 0x1000>;
26 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
27 reg = <0x6000a000 0x1400>;
28 interrupts = <0 104 0x04
60 clocks = <&tegra_car 34>;
64 compatible = "nvidia,tegra30-gpio";
65 reg = <0x6000d000 0x1000>;
66 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
76 #interrupt-cells = <2>;
81 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
82 reg = <0x7000c000 0x100>;
83 interrupts = <0 38 0x04>;
86 clocks = <&tegra_car 12>, <&tegra_car 182>;
87 clock-names = "div-clk", "fast-clk";
92 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
93 reg = <0x7000c400 0x100>;
94 interrupts = <0 84 0x04>;
97 clocks = <&tegra_car 54>, <&tegra_car 182>;
98 clock-names = "div-clk", "fast-clk";
103 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
104 reg = <0x7000c500 0x100>;
105 interrupts = <0 92 0x04>;
106 #address-cells = <1>;
108 clocks = <&tegra_car 67>, <&tegra_car 182>;
109 clock-names = "div-clk", "fast-clk";
114 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
115 reg = <0x7000c700 0x100>;
116 interrupts = <0 120 0x04>;
117 #address-cells = <1>;
119 clocks = <&tegra_car 103>, <&tegra_car 182>;
120 clock-names = "div-clk", "fast-clk";
125 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
126 reg = <0x7000d000 0x100>;
127 interrupts = <0 53 0x04>;
128 #address-cells = <1>;
130 clocks = <&tegra_car 47>, <&tegra_car 182>;
131 clock-names = "div-clk", "fast-clk";
135 uarta: serial@70006000 {
136 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
137 reg = <0x70006000 0x40>;
139 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
140 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
141 resets = <&tegra_car 6>;
142 reset-names = "serial";
143 dmas = <&apbdma 8>, <&apbdma 8>;
144 dma-names = "rx", "tx";
148 uartb: serial@70006040 {
149 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
150 reg = <0x70006040 0x40>;
152 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
153 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
154 resets = <&tegra_car 7>;
155 reset-names = "serial";
156 dmas = <&apbdma 9>, <&apbdma 9>;
157 dma-names = "rx", "tx";
161 uartc: serial@70006200 {
162 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
163 reg = <0x70006200 0x100>;
165 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
167 resets = <&tegra_car 55>;
168 reset-names = "serial";
169 dmas = <&apbdma 10>, <&apbdma 10>;
170 dma-names = "rx", "tx";
174 uartd: serial@70006300 {
175 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
176 reg = <0x70006300 0x100>;
178 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
179 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
180 resets = <&tegra_car 65>;
181 reset-names = "serial";
182 dmas = <&apbdma 19>, <&apbdma 19>;
183 dma-names = "rx", "tx";
187 uarte: serial@70006400 {
188 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
189 reg = <0x70006400 0x100>;
191 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
193 resets = <&tegra_car 66>;
194 reset-names = "serial";
195 dmas = <&apbdma 20>, <&apbdma 20>;
196 dma-names = "rx", "tx";
201 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
202 reg = <0x7000d400 0x200>;
203 interrupts = <0 59 0x04>;
204 nvidia,dma-request-selector = <&apbdma 15>;
205 #address-cells = <1>;
207 clocks = <&tegra_car 41>;
212 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
213 reg = <0x7000d600 0x200>;
214 interrupts = <0 82 0x04>;
215 nvidia,dma-request-selector = <&apbdma 16>;
216 #address-cells = <1>;
218 clocks = <&tegra_car 44>;
223 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
224 reg = <0x7000d480 0x200>;
225 interrupts = <0 83 0x04>;
226 nvidia,dma-request-selector = <&apbdma 17>;
227 #address-cells = <1>;
229 clocks = <&tegra_car 46>;
234 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
235 reg = <0x7000da00 0x200>;
236 interrupts = <0 93 0x04>;
237 nvidia,dma-request-selector = <&apbdma 18>;
238 #address-cells = <1>;
240 clocks = <&tegra_car 68>;
245 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
246 reg = <0x7000dc00 0x200>;
247 interrupts = <0 94 0x04>;
248 nvidia,dma-request-selector = <&apbdma 27>;
249 #address-cells = <1>;
251 clocks = <&tegra_car 104>;
256 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
257 reg = <0x7000de00 0x200>;
258 interrupts = <0 79 0x04>;
259 nvidia,dma-request-selector = <&apbdma 28>;
260 #address-cells = <1>;
262 clocks = <&tegra_car 105>;
267 compatible = "nvidia,tegra30-sdhci";
268 reg = <0x78000000 0x200>;
269 interrupts = <0 14 0x04>;
270 clocks = <&tegra_car 14>;
275 compatible = "nvidia,tegra30-sdhci";
276 reg = <0x78000200 0x200>;
277 interrupts = <0 15 0x04>;
278 clocks = <&tegra_car 9>;
283 compatible = "nvidia,tegra30-sdhci";
284 reg = <0x78000400 0x200>;
285 interrupts = <0 19 0x04>;
286 clocks = <&tegra_car 69>;
291 compatible = "nvidia,tegra30-sdhci";
292 reg = <0x78000600 0x200>;
293 interrupts = <0 31 0x04>;
294 clocks = <&tegra_car 15>;
299 compatible = "nvidia,tegra30-ehci";
300 reg = <0x7d000000 0x4000>;
303 clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
308 compatible = "nvidia,tegra30-ehci";
309 reg = <0x7d004000 0x4000>;
312 clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
317 compatible = "nvidia,tegra30-ehci";
318 reg = <0x7d008000 0x4000>;
321 clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */