git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-common32.dtsi

   1 /*
   2  * Device Tree Source commonly used by UniPhier ARM SoCs
   3  *
   4  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10
  11 / {
  12         clocks {
  13                 refclk: ref {
  14                         #clock-cells = <0>;
  15                         compatible = "fixed-clock";
  16                 };
  17         };
  18
  19         soc: soc {
  20                 compatible = "simple-bus";
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23                 ranges;
  24                 interrupt-parent = <&intc>;
  25
  26                 extbus: extbus {
  27                         compatible = "simple-bus";
  28                         #address-cells = <2>;
  29                         #size-cells = <1>;
  30                 };
  31
  32                 serial0: serial@54006800 {
  33                         compatible = "socionext,uniphier-uart";
  34                         status = "disabled";
  35                         reg = <0x54006800 0x40>;
  36                         interrupts = <0 33 4>;
  37                         pinctrl-names = "default";
  38                         pinctrl-0 = <&pinctrl_uart0>;
  39                         clocks = <&uart_clk>;
  40                 };
  41
  42                 serial1: serial@54006900 {
  43                         compatible = "socionext,uniphier-uart";
  44                         status = "disabled";
  45                         reg = <0x54006900 0x40>;
  46                         interrupts = <0 35 4>;
  47                         pinctrl-names = "default";
  48                         pinctrl-0 = <&pinctrl_uart1>;
  49                         clocks = <&uart_clk>;
  50                 };
  51
  52                 serial2: serial@54006a00 {
  53                         compatible = "socionext,uniphier-uart";
  54                         status = "disabled";
  55                         reg = <0x54006a00 0x40>;
  56                         interrupts = <0 37 4>;
  57                         pinctrl-names = "default";
  58                         pinctrl-0 = <&pinctrl_uart2>;
  59                         clocks = <&uart_clk>;
  60                 };
  61
  62                 serial3: serial@54006b00 {
  63                         compatible = "socionext,uniphier-uart";
  64                         status = "disabled";
  65                         reg = <0x54006b00 0x40>;
  66                         interrupts = <0 177 4>;
  67                         pinctrl-names = "default";
  68                         pinctrl-0 = <&pinctrl_uart3>;
  69                         clocks = <&uart_clk>;
  70                 };
  71
  72                 system-bus-controller@58c00000 {
  73                         compatible = "socionext,uniphier-system-bus-controller";
  74                         reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
  75                 };
  76
  77                 mio: mioctrl@59810000 {
  78                         /* specify compatible in each SoC DTSI */
  79                         reg = <0x59810000 0x800>;
  80                         #clock-cells = <1>;
  81                 };
  82
  83                 peri: perictrl@59820000 {
  84                         /* specify compatible in each SoC DTSI */
  85                         reg = <0x59820000 0x200>;
  86                         #clock-cells = <1>;
  87                 };
  88
  89                 timer@60000200 {
  90                         compatible = "arm,cortex-a9-global-timer";
  91                         reg = <0x60000200 0x20>;
  92                         interrupts = <1 11 0x104>;
  93                         clocks = <&arm_timer_clk>;
  94                 };
  95
  96                 timer@60000600 {
  97                         compatible = "arm,cortex-a9-twd-timer";
  98                         reg = <0x60000600 0x20>;
  99                         interrupts = <1 13 0x104>;
 100                         clocks = <&arm_timer_clk>;
 101                 };
 102
 103                 intc: interrupt-controller@60001000 {
 104                         compatible = "arm,cortex-a9-gic";
 105                         reg = <0x60001000 0x1000>,
 106                               <0x60000100 0x100>;
 107                         #interrupt-cells = <3>;
 108                         interrupt-controller;
 109                 };
 110
 111                 pinctrl: pinctrl@5f801000 {
 112                         /* specify compatible in each SoC DTSI */
 113                         reg = <0x5f801000 0xe00>;
 114                 };
 115
 116                 sysctrl: sysctrl@61840000 {
 117                         /* specify compatible in each SoC DTSI */
 118                         reg = <0x61840000 0x4000>;
 119                         #clock-cells = <1>;
 120                         clock-names = "ref";
 121                         clocks = <&refclk>;
 122                 };
 123
 124                 nand: nand@68000000 {
 125                         compatible = "denali,denali-nand-dt";
 126                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 127                         reg-names = "nand_data", "denali_reg";
 128                 };
 129         };
 130 };
 131
 132 /include/ "uniphier-pinctrl.dtsi"