git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-common32.dtsi

   1 /*
   2  * Device Tree Source commonly used by UniPhier ARM SoCs
   3  *
   4  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10
  11 / {
  12         clocks {
  13                 refclk: ref {
  14                         #clock-cells = <0>;
  15                         compatible = "fixed-clock";
  16                 };
  17         };
  18
  19         soc: soc {
  20                 compatible = "simple-bus";
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23                 ranges;
  24                 interrupt-parent = <&intc>;
  25
  26                 serial0: serial@54006800 {
  27                         compatible = "socionext,uniphier-uart";
  28                         status = "disabled";
  29                         reg = <0x54006800 0x40>;
  30                         interrupts = <0 33 4>;
  31                         pinctrl-names = "default";
  32                         pinctrl-0 = <&pinctrl_uart0>;
  33                         clocks = <&uart_clk>;
  34                 };
  35
  36                 serial1: serial@54006900 {
  37                         compatible = "socionext,uniphier-uart";
  38                         status = "disabled";
  39                         reg = <0x54006900 0x40>;
  40                         interrupts = <0 35 4>;
  41                         pinctrl-names = "default";
  42                         pinctrl-0 = <&pinctrl_uart1>;
  43                         clocks = <&uart_clk>;
  44                 };
  45
  46                 serial2: serial@54006a00 {
  47                         compatible = "socionext,uniphier-uart";
  48                         status = "disabled";
  49                         reg = <0x54006a00 0x40>;
  50                         interrupts = <0 37 4>;
  51                         pinctrl-names = "default";
  52                         pinctrl-0 = <&pinctrl_uart2>;
  53                         clocks = <&uart_clk>;
  54                 };
  55
  56                 serial3: serial@54006b00 {
  57                         compatible = "socionext,uniphier-uart";
  58                         status = "disabled";
  59                         reg = <0x54006b00 0x40>;
  60                         interrupts = <0 177 4>;
  61                         pinctrl-names = "default";
  62                         pinctrl-0 = <&pinctrl_uart3>;
  63                         clocks = <&uart_clk>;
  64                 };
  65
  66                 system_bus: system-bus@58c00000 {
  67                         compatible = "socionext,uniphier-system-bus";
  68                         reg = <0x58c00000 0x400>;
  69                         #address-cells = <2>;
  70                         #size-cells = <1>;
  71                 };
  72
  73                 smpctrl@59800000 {
  74                         compatible = "socionext,uniphier-smpctrl";
  75                         reg = <0x59801000 0x400>;
  76                 };
  77
  78                 mio: mioctrl@59810000 {
  79                         /* specify compatible in each SoC DTSI */
  80                         reg = <0x59810000 0x800>;
  81                         #clock-cells = <1>;
  82                 };
  83
  84                 peri: perictrl@59820000 {
  85                         /* specify compatible in each SoC DTSI */
  86                         reg = <0x59820000 0x200>;
  87                         #clock-cells = <1>;
  88                 };
  89
  90                 timer@60000200 {
  91                         compatible = "arm,cortex-a9-global-timer";
  92                         reg = <0x60000200 0x20>;
  93                         interrupts = <1 11 0x104>;
  94                         clocks = <&arm_timer_clk>;
  95                 };
  96
  97                 timer@60000600 {
  98                         compatible = "arm,cortex-a9-twd-timer";
  99                         reg = <0x60000600 0x20>;
 100                         interrupts = <1 13 0x104>;
 101                         clocks = <&arm_timer_clk>;
 102                 };
 103
 104                 intc: interrupt-controller@60001000 {
 105                         compatible = "arm,cortex-a9-gic";
 106                         reg = <0x60001000 0x1000>,
 107                               <0x60000100 0x100>;
 108                         #interrupt-cells = <3>;
 109                         interrupt-controller;
 110                 };
 111
 112                 pinctrl: pinctrl@5f801000 {
 113                         /* specify compatible in each SoC DTSI */
 114                         reg = <0x5f801000 0xe00>;
 115                 };
 116
 117                 sysctrl: sysctrl@61840000 {
 118                         /* specify compatible in each SoC DTSI */
 119                         reg = <0x61840000 0x4000>;
 120                         #clock-cells = <1>;
 121                         clock-names = "ref";
 122                         clocks = <&refclk>;
 123                 };
 124
 125                 nand: nand@68000000 {
 126                         compatible = "denali,denali-nand-dt";
 127                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 128                         reg-names = "nand_data", "denali_reg";
 129                 };
 130         };
 131 };
 132
 133 /include/ "uniphier-pinctrl.dtsi"